Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	36	0	36	100.00
Crosses	128	0	128	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	32	0	32	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	128	0	128	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	4196548	1			T21	123		T22	1		T23	1
all_pins[1]	4196548	1			T21	123		T22	1		T23	1
all_pins[2]	4196548	1			T21	123		T22	1		T23	1
all_pins[3]	4196548	1			T21	123		T22	1		T23	1
all_pins[4]	4196548	1			T21	123		T22	1		T23	1
all_pins[5]	4196548	1			T21	123		T22	1		T23	1
all_pins[6]	4196548	1			T21	123		T22	1		T23	1
all_pins[7]	4196548	1			T21	123		T22	1		T23	1
all_pins[8]	4196548	1			T21	123		T22	1		T23	1
all_pins[9]	4196548	1			T21	123		T22	1		T23	1
all_pins[10]	4196548	1			T21	123		T22	1		T23	1
all_pins[11]	4196548	1			T21	123		T22	1		T23	1
all_pins[12]	4196548	1			T21	123		T22	1		T23	1
all_pins[13]	4196548	1			T21	123		T22	1		T23	1
all_pins[14]	4196548	1			T21	123		T22	1		T23	1
all_pins[15]	4196548	1			T21	123		T22	1		T23	1
all_pins[16]	4196548	1			T21	123		T22	1		T23	1
all_pins[17]	4196548	1			T21	123		T22	1		T23	1
all_pins[18]	4196548	1			T21	123		T22	1		T23	1
all_pins[19]	4196548	1			T21	123		T22	1		T23	1
all_pins[20]	4196548	1			T21	123		T22	1		T23	1
all_pins[21]	4196548	1			T21	123		T22	1		T23	1
all_pins[22]	4196548	1			T21	123		T22	1		T23	1
all_pins[23]	4196548	1			T21	123		T22	1		T23	1
all_pins[24]	4196548	1			T21	123		T22	1		T23	1
all_pins[25]	4196548	1			T21	123		T22	1		T23	1
all_pins[26]	4196548	1			T21	123		T22	1		T23	1
all_pins[27]	4196548	1			T21	123		T22	1		T23	1
all_pins[28]	4196548	1			T21	123		T22	1		T23	1
all_pins[29]	4196548	1			T21	123		T22	1		T23	1
all_pins[30]	4196548	1			T21	123		T22	1		T23	1
all_pins[31]	4196548	1			T21	123		T22	1		T23	1

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	83390279	1			T21	2364		T22	32		T23	32
values[0x1]	50899257	1			T21	1572		T26	811		T28	1489
transitions[0x0=>0x1]	30467463	1			T21	874		T26	431		T28	728
transitions[0x1=>0x0]	30467303	1			T21	873		T26	430		T28	727

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	2611559	1			T21	62		T22	1		T23	1
all_pins[0]	values[0x1]	1584989	1			T21	61		T26	24		T28	43
all_pins[0]	transitions[0x0=>0x1]	980797	1			T21	52		T26	8		T28	21
all_pins[0]	transitions[0x1=>0x0]	987559	1			T21	15		T26	13		T28	20
all_pins[1]	values[0x0]	2605969	1			T21	78		T22	1		T23	1
all_pins[1]	values[0x1]	1590579	1			T21	45		T26	24		T28	48
all_pins[1]	transitions[0x0=>0x1]	956013	1			T21	19		T26	12		T28	25
all_pins[1]	transitions[0x1=>0x0]	950423	1			T21	35		T26	12		T28	20
all_pins[2]	values[0x0]	2609179	1			T21	60		T22	1		T23	1
all_pins[2]	values[0x1]	1587369	1			T21	63		T26	16		T28	44
all_pins[2]	transitions[0x0=>0x1]	948575	1			T21	41		T26	7		T28	20
all_pins[2]	transitions[0x1=>0x0]	951785	1			T21	23		T26	15		T28	24
all_pins[3]	values[0x0]	2603870	1			T21	61		T22	1		T23	1
all_pins[3]	values[0x1]	1592678	1			T21	62		T26	21		T28	57
all_pins[3]	transitions[0x0=>0x1]	954233	1			T21	27		T26	15		T28	29
all_pins[3]	transitions[0x1=>0x0]	948924	1			T21	28		T26	10		T28	16
all_pins[4]	values[0x0]	2608995	1			T21	72		T22	1		T23	1
all_pins[4]	values[0x1]	1587553	1			T21	51		T26	21		T28	49
all_pins[4]	transitions[0x0=>0x1]	947505	1			T21	21		T26	11		T28	19
all_pins[4]	transitions[0x1=>0x0]	952630	1			T21	32		T26	11		T28	27
all_pins[5]	values[0x0]	2607118	1			T21	79		T22	1		T23	1
all_pins[5]	values[0x1]	1589430	1			T21	44		T26	33		T28	42
all_pins[5]	transitions[0x0=>0x1]	951028	1			T21	23		T26	23		T28	18
all_pins[5]	transitions[0x1=>0x0]	949151	1			T21	30		T26	11		T28	25
all_pins[6]	values[0x0]	2605095	1			T21	69		T22	1		T23	1
all_pins[6]	values[0x1]	1591453	1			T21	54		T26	19		T28	51
all_pins[6]	transitions[0x0=>0x1]	949930	1			T21	23		T26	12		T28	26
all_pins[6]	transitions[0x1=>0x0]	947907	1			T21	13		T26	26		T28	17
all_pins[7]	values[0x0]	2607971	1			T21	88		T22	1		T23	1
all_pins[7]	values[0x1]	1588577	1			T21	35		T26	15		T28	43
all_pins[7]	transitions[0x0=>0x1]	948444	1			T21	16		T26	7		T28	16
all_pins[7]	transitions[0x1=>0x0]	951320	1			T21	35		T26	11		T28	24
all_pins[8]	values[0x0]	2604260	1			T21	90		T22	1		T23	1
all_pins[8]	values[0x1]	1592288	1			T21	33		T26	21		T28	42
all_pins[8]	transitions[0x0=>0x1]	954146	1			T21	32		T26	15		T28	19
all_pins[8]	transitions[0x1=>0x0]	950435	1			T21	34		T26	9		T28	20
all_pins[9]	values[0x0]	2595283	1			T21	69		T22	1		T23	1
all_pins[9]	values[0x1]	1601265	1			T21	54		T26	22		T28	51
all_pins[9]	transitions[0x0=>0x1]	955709	1			T21	46		T26	13		T28	25
all_pins[9]	transitions[0x1=>0x0]	946732	1			T21	25		T26	12		T28	16
all_pins[10]	values[0x0]	2609983	1			T21	67		T22	1		T23	1
all_pins[10]	values[0x1]	1586565	1			T21	56		T26	24		T28	38
all_pins[10]	transitions[0x0=>0x1]	943076	1			T21	34		T26	15		T28	20
all_pins[10]	transitions[0x1=>0x0]	957776	1			T21	32		T26	13		T28	33
all_pins[11]	values[0x0]	2608212	1			T21	87		T22	1		T23	1
all_pins[11]	values[0x1]	1588336	1			T21	36		T26	26		T28	32
all_pins[11]	transitions[0x0=>0x1]	951175	1			T21	26		T26	13		T28	17
all_pins[11]	transitions[0x1=>0x0]	949404	1			T21	46		T26	11		T28	23
all_pins[12]	values[0x0]	2607077	1			T21	69		T22	1		T23	1
all_pins[12]	values[0x1]	1589471	1			T21	54		T26	28		T28	50
all_pins[12]	transitions[0x0=>0x1]	951662	1			T21	30		T26	22		T28	31
all_pins[12]	transitions[0x1=>0x0]	950527	1			T21	12		T26	20		T28	13
all_pins[13]	values[0x0]	2605247	1			T21	86		T22	1		T23	1
all_pins[13]	values[0x1]	1591301	1			T21	37		T26	20		T28	50
all_pins[13]	transitions[0x0=>0x1]	953624	1			T21	11		T26	9		T28	20
all_pins[13]	transitions[0x1=>0x0]	951794	1			T21	28		T26	17		T28	20
all_pins[14]	values[0x0]	2604953	1			T21	73		T22	1		T23	1
all_pins[14]	values[0x1]	1591595	1			T21	50		T26	33		T28	53
all_pins[14]	transitions[0x0=>0x1]	950498	1			T21	32		T26	19		T28	26
all_pins[14]	transitions[0x1=>0x0]	950204	1			T21	19		T26	6		T28	23
all_pins[15]	values[0x0]	2611330	1			T21	88		T22	1		T23	1
all_pins[15]	values[0x1]	1585218	1			T21	35		T26	20		T28	41
all_pins[15]	transitions[0x0=>0x1]	945743	1			T21	22		T26	9		T28	19
all_pins[15]	transitions[0x1=>0x0]	952120	1			T21	37		T26	22		T28	31
all_pins[16]	values[0x0]	2608924	1			T21	93		T22	1		T23	1
all_pins[16]	values[0x1]	1587624	1			T21	30		T26	26		T28	52
all_pins[16]	transitions[0x0=>0x1]	952026	1			T21	20		T26	17		T28	30
all_pins[16]	transitions[0x1=>0x0]	949620	1			T21	25		T26	11		T28	19
all_pins[17]	values[0x0]	2602648	1			T21	75		T22	1		T23	1
all_pins[17]	values[0x1]	1593900	1			T21	48		T26	22		T28	52
all_pins[17]	transitions[0x0=>0x1]	954037	1			T21	24		T26	14		T28	25
all_pins[17]	transitions[0x1=>0x0]	947761	1			T21	6		T26	18		T28	25
all_pins[18]	values[0x0]	2610325	1			T21	63		T22	1		T23	1
all_pins[18]	values[0x1]	1586223	1			T21	60		T26	28		T28	37
all_pins[18]	transitions[0x0=>0x1]	948623	1			T21	28		T26	14		T28	14
all_pins[18]	transitions[0x1=>0x0]	956300	1			T21	16		T26	8		T28	29
all_pins[19]	values[0x0]	2608640	1			T21	81		T22	1		T23	1
all_pins[19]	values[0x1]	1587908	1			T21	42		T26	35		T28	48
all_pins[19]	transitions[0x0=>0x1]	951578	1			T21	17		T26	21		T28	27
all_pins[19]	transitions[0x1=>0x0]	949893	1			T21	35		T26	14		T28	16
all_pins[20]	values[0x0]	2610782	1			T21	64		T22	1		T23	1
all_pins[20]	values[0x1]	1585766	1			T21	59		T26	31		T28	44
all_pins[20]	transitions[0x0=>0x1]	949745	1			T21	35		T26	14		T28	22
all_pins[20]	transitions[0x1=>0x0]	951887	1			T21	18		T26	18		T28	26
all_pins[21]	values[0x0]	2605939	1			T21	57		T22	1		T23	1
all_pins[21]	values[0x1]	1590609	1			T21	66		T26	32		T28	46
all_pins[21]	transitions[0x0=>0x1]	953880	1			T21	37		T26	10		T28	23
all_pins[21]	transitions[0x1=>0x0]	949037	1			T21	30		T26	9		T28	21
all_pins[22]	values[0x0]	2603455	1			T21	67		T22	1		T23	1
all_pins[22]	values[0x1]	1593093	1			T21	56		T26	31		T28	47
all_pins[22]	transitions[0x0=>0x1]	954666	1			T21	22		T26	14		T28	25
all_pins[22]	transitions[0x1=>0x0]	952182	1			T21	32		T26	15		T28	24
all_pins[23]	values[0x0]	2610147	1			T21	65		T22	1		T23	1
all_pins[23]	values[0x1]	1586401	1			T21	58		T26	23		T28	54
all_pins[23]	transitions[0x0=>0x1]	947712	1			T21	18		T26	7		T28	30
all_pins[23]	transitions[0x1=>0x0]	954404	1			T21	16		T26	15		T28	23
all_pins[24]	values[0x0]	2605650	1			T21	65		T22	1		T23	1
all_pins[24]	values[0x1]	1590898	1			T21	58		T26	24		T28	57
all_pins[24]	transitions[0x0=>0x1]	952920	1			T21	36		T26	13		T28	27
all_pins[24]	transitions[0x1=>0x0]	948423	1			T21	36		T26	12		T28	24
all_pins[25]	values[0x0]	2606404	1			T21	63		T22	1		T23	1
all_pins[25]	values[0x1]	1590144	1			T21	60		T26	26		T28	46
all_pins[25]	transitions[0x0=>0x1]	948754	1			T21	36		T26	13		T28	21
all_pins[25]	transitions[0x1=>0x0]	949508	1			T21	34		T26	11		T28	32
all_pins[26]	values[0x0]	2600646	1			T21	92		T22	1		T23	1
all_pins[26]	values[0x1]	1595902	1			T21	31		T26	32		T28	35
all_pins[26]	transitions[0x0=>0x1]	956617	1			T21	21		T26	17		T28	20
all_pins[26]	transitions[0x1=>0x0]	950859	1			T21	50		T26	11		T28	31
all_pins[27]	values[0x0]	2599145	1			T21	61		T22	1		T23	1
all_pins[27]	values[0x1]	1597403	1			T21	62		T26	24		T28	46
all_pins[27]	transitions[0x0=>0x1]	952178	1			T21	40		T26	12		T28	28
all_pins[27]	transitions[0x1=>0x0]	950677	1			T21	9		T26	20		T28	17
all_pins[28]	values[0x0]	2602548	1			T21	76		T22	1		T23	1
all_pins[28]	values[0x1]	1594000	1			T21	47		T26	30		T28	51
all_pins[28]	transitions[0x0=>0x1]	949683	1			T21	20		T26	12		T28	21
all_pins[28]	transitions[0x1=>0x0]	953086	1			T21	35		T26	6		T28	16
all_pins[29]	values[0x0]	2603761	1			T21	81		T22	1		T23	1
all_pins[29]	values[0x1]	1592787	1			T21	42		T26	25		T28	50
all_pins[29]	transitions[0x0=>0x1]	950215	1			T21	16		T26	12		T28	23
all_pins[29]	transitions[0x1=>0x0]	951428	1			T21	21		T26	17		T28	24
all_pins[30]	values[0x0]	2600527	1			T21	65		T22	1		T23	1
all_pins[30]	values[0x1]	1596021	1			T21	58		T26	25		T28	47
all_pins[30]	transitions[0x0=>0x1]	952541	1			T21	31		T26	13		T28	23
all_pins[30]	transitions[0x1=>0x0]	949307	1			T21	15		T26	13		T28	26
all_pins[31]	values[0x0]	2604637	1			T21	98		T22	1		T23	1
all_pins[31]	values[0x1]	1591911	1			T21	25		T26	30		T28	43
all_pins[31]	transitions[0x0=>0x1]	950130	1			T21	18		T26	18		T28	18
all_pins[31]	transitions[0x1=>0x0]	954240	1			T21	51		T26	13		T28	22