Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	192	0	192	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	32	0	32	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	192	0	192	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	14030231	1			T21	207		T22	204		T23	128
all_values[1]	14030231	1			T21	207		T22	204		T23	128
all_values[2]	14030231	1			T21	207		T22	204		T23	128
all_values[3]	14030231	1			T21	207		T22	204		T23	128
all_values[4]	14030231	1			T21	207		T22	204		T23	128
all_values[5]	14030231	1			T21	207		T22	204		T23	128
all_values[6]	14030231	1			T21	207		T22	204		T23	128
all_values[7]	14030231	1			T21	207		T22	204		T23	128
all_values[8]	14030231	1			T21	207		T22	204		T23	128
all_values[9]	14030231	1			T21	207		T22	204		T23	128
all_values[10]	14030231	1			T21	207		T22	204		T23	128
all_values[11]	14030231	1			T21	207		T22	204		T23	128
all_values[12]	14030231	1			T21	207		T22	204		T23	128
all_values[13]	14030231	1			T21	207		T22	204		T23	128
all_values[14]	14030231	1			T21	207		T22	204		T23	128
all_values[15]	14030231	1			T21	207		T22	204		T23	128
all_values[16]	14030231	1			T21	207		T22	204		T23	128
all_values[17]	14030231	1			T21	207		T22	204		T23	128
all_values[18]	14030231	1			T21	207		T22	204		T23	128
all_values[19]	14030231	1			T21	207		T22	204		T23	128
all_values[20]	14030231	1			T21	207		T22	204		T23	128
all_values[21]	14030231	1			T21	207		T22	204		T23	128
all_values[22]	14030231	1			T21	207		T22	204		T23	128
all_values[23]	14030231	1			T21	207		T22	204		T23	128
all_values[24]	14030231	1			T21	207		T22	204		T23	128
all_values[25]	14030231	1			T21	207		T22	204		T23	128
all_values[26]	14030231	1			T21	207		T22	204		T23	128
all_values[27]	14030231	1			T21	207		T22	204		T23	128
all_values[28]	14030231	1			T21	207		T22	204		T23	128
all_values[29]	14030231	1			T21	207		T22	204		T23	128
all_values[30]	14030231	1			T21	207		T22	204		T23	128
all_values[31]	14030231	1			T21	207		T22	204		T23	128

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

258399675

1

T21

3206

T22

6528

T23

4096

auto[1]

190567717

1

T21

3418

T29

20666

T31

512303

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

104212728

1

T21

1048

T22

6528

T23

4096

auto[1]

344754664

1

T21

5576

T29

40895

T31

915669

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

444039227

1

T21

6624

T22

6528

T23

4096

auto[1]

4928165

1

T31

5915

T32

45594

T33

3601

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	192	0	192	100.00
Automatically Generated Cross Bins	192	0	192	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	2677813	1			T21	9		T22	204		T23	128
all_values[0]	auto[0]	auto[0]	auto[1]	5326377	1			T21	82		T29	866		T31	14083
all_values[0]	auto[0]	auto[1]	auto[0]	567523	1			T21	4		T29	61		T31	1583
all_values[0]	auto[0]	auto[1]	auto[1]	5304447	1			T21	112		T29	391		T31	14598
all_values[0]	auto[1]	auto[0]	auto[1]	77107	1			T31	98		T32	736		T33	53
all_values[0]	auto[1]	auto[1]	auto[1]	76964	1			T31	82		T32	725		T33	61
all_values[1]	auto[0]	auto[0]	auto[0]	2677266	1			T21	16		T22	204		T23	128
all_values[1]	auto[0]	auto[0]	auto[1]	5326107	1			T21	101		T29	620		T31	14165
all_values[1]	auto[0]	auto[1]	auto[0]	570993	1			T21	13		T29	38		T31	1532
all_values[1]	auto[0]	auto[1]	auto[1]	5301978	1			T21	77		T29	676		T31	14469
all_values[1]	auto[1]	auto[0]	auto[1]	77492	1			T31	94		T32	710		T33	55
all_values[1]	auto[1]	auto[1]	auto[1]	76395	1			T31	97		T32	709		T33	56
all_values[2]	auto[0]	auto[0]	auto[0]	2674903	1			T21	8		T22	204		T23	128
all_values[2]	auto[0]	auto[0]	auto[1]	5302934	1			T21	70		T29	713		T31	14601
all_values[2]	auto[0]	auto[1]	auto[0]	582305	1			T21	16		T29	51		T31	1745
all_values[2]	auto[0]	auto[1]	auto[1]	5316194	1			T21	113		T29	570		T31	13741
all_values[2]	auto[1]	auto[0]	auto[1]	77104	1			T31	100		T32	725		T33	53
all_values[2]	auto[1]	auto[1]	auto[1]	76791	1			T31	82		T32	693		T33	80
all_values[3]	auto[0]	auto[0]	auto[0]	2685578	1			T21	7		T22	204		T23	128
all_values[3]	auto[0]	auto[0]	auto[1]	5276550	1			T21	73		T29	341		T31	13825
all_values[3]	auto[0]	auto[1]	auto[0]	570838	1			T21	15		T29	57		T31	1985
all_values[3]	auto[0]	auto[1]	auto[1]	5342992	1			T21	112		T29	956		T31	14219
all_values[3]	auto[1]	auto[0]	auto[1]	77073	1			T31	102		T32	699		T33	43
all_values[3]	auto[1]	auto[1]	auto[1]	77200	1			T31	95		T32	742		T33	60
all_values[4]	auto[0]	auto[0]	auto[0]	2687833	1			T21	22		T22	204		T23	128
all_values[4]	auto[0]	auto[0]	auto[1]	5303295	1			T21	87		T29	777		T31	13609
all_values[4]	auto[0]	auto[1]	auto[0]	571395	1			T21	5		T29	16		T31	1791
all_values[4]	auto[0]	auto[1]	auto[1]	5313829	1			T21	93		T29	543		T31	14562
all_values[4]	auto[1]	auto[0]	auto[1]	77361	1			T31	92		T32	665		T33	55
all_values[4]	auto[1]	auto[1]	auto[1]	76518	1			T31	106		T32	699		T33	50
all_values[5]	auto[0]	auto[0]	auto[0]	2682975	1			T21	10		T22	204		T23	128
all_values[5]	auto[0]	auto[0]	auto[1]	5308932	1			T21	103		T29	664		T31	13721
all_values[5]	auto[0]	auto[1]	auto[0]	570012	1			T21	6		T29	23		T31	1598
all_values[5]	auto[0]	auto[1]	auto[1]	5314112	1			T21	88		T29	647		T31	14914
all_values[5]	auto[1]	auto[0]	auto[1]	77319	1			T31	79		T32	726		T33	66
all_values[5]	auto[1]	auto[1]	auto[1]	76881	1			T31	107		T32	702		T33	57
all_values[6]	auto[0]	auto[0]	auto[0]	2679968	1			T21	24		T22	204		T23	128
all_values[6]	auto[0]	auto[0]	auto[1]	5324677	1			T21	54		T29	714		T31	14226
all_values[6]	auto[0]	auto[1]	auto[0]	582574	1			T21	18		T29	69		T31	1661
all_values[6]	auto[0]	auto[1]	auto[1]	5289480	1			T21	111		T29	517		T31	14319
all_values[6]	auto[1]	auto[0]	auto[1]	77284	1			T31	93		T32	720		T33	61
all_values[6]	auto[1]	auto[1]	auto[1]	76248	1			T31	75		T32	705		T33	61
all_values[7]	auto[0]	auto[0]	auto[0]	2688490	1			T21	22		T22	204		T23	128
all_values[7]	auto[0]	auto[0]	auto[1]	5320615	1			T21	100		T29	895		T31	13092
all_values[7]	auto[0]	auto[1]	auto[0]	572851	1			T21	19		T29	89		T31	1784
all_values[7]	auto[0]	auto[1]	auto[1]	5294429	1			T21	66		T29	339		T31	15316
all_values[7]	auto[1]	auto[0]	auto[1]	77355	1			T31	79		T32	706		T33	59
all_values[7]	auto[1]	auto[1]	auto[1]	76491	1			T31	116		T32	719		T33	52
all_values[8]	auto[0]	auto[0]	auto[0]	2678845	1			T21	39		T22	204		T23	128
all_values[8]	auto[0]	auto[0]	auto[1]	5322385	1			T21	87		T29	760		T31	15810
all_values[8]	auto[0]	auto[1]	auto[0]	570566	1			T21	19		T29	68		T31	1395
all_values[8]	auto[0]	auto[1]	auto[1]	5304219	1			T21	62		T29	517		T31	12971
all_values[8]	auto[1]	auto[0]	auto[1]	76880	1			T31	105		T32	716		T33	56
all_values[8]	auto[1]	auto[1]	auto[1]	77336	1			T31	77		T32	716		T33	63
all_values[9]	auto[0]	auto[0]	auto[0]	2676353	1			T21	11		T22	204		T23	128
all_values[9]	auto[0]	auto[0]	auto[1]	5286277	1			T21	84		T29	560		T31	14531
all_values[9]	auto[0]	auto[1]	auto[0]	568198	1			T21	19		T29	30		T31	1664
all_values[9]	auto[0]	auto[1]	auto[1]	5344959	1			T21	93		T29	763		T31	13987
all_values[9]	auto[1]	auto[0]	auto[1]	77788	1			T31	82		T32	700		T33	53
all_values[9]	auto[1]	auto[1]	auto[1]	76656	1			T31	112		T32	728		T33	70
all_values[10]	auto[0]	auto[0]	auto[0]	2686949	1			T21	19		T22	204		T23	128
all_values[10]	auto[0]	auto[0]	auto[1]	5304883	1			T21	65		T29	588		T31	14150
all_values[10]	auto[0]	auto[1]	auto[0]	579173	1			T21	28		T29	39		T31	1836
all_values[10]	auto[0]	auto[1]	auto[1]	5305182	1			T21	95		T29	720		T31	14081
all_values[10]	auto[1]	auto[0]	auto[1]	77022	1			T31	100		T32	694		T33	70
all_values[10]	auto[1]	auto[1]	auto[1]	77022	1			T31	91		T32	761		T33	48
all_values[11]	auto[0]	auto[0]	auto[0]	2677324	1			T21	16		T22	204		T23	128
all_values[11]	auto[0]	auto[0]	auto[1]	5321504	1			T21	105		T29	587		T31	15459
all_values[11]	auto[0]	auto[1]	auto[0]	572867	1			T21	13		T29	74		T31	1691
all_values[11]	auto[0]	auto[1]	auto[1]	5304281	1			T21	73		T29	694		T31	12898
all_values[11]	auto[1]	auto[0]	auto[1]	77251	1			T31	96		T32	715		T33	70
all_values[11]	auto[1]	auto[1]	auto[1]	77004	1			T31	95		T32	752		T33	42
all_values[12]	auto[0]	auto[0]	auto[0]	2686809	1			T21	6		T22	204		T23	128
all_values[12]	auto[0]	auto[0]	auto[1]	5332329	1			T21	79		T29	761		T31	12331
all_values[12]	auto[0]	auto[1]	auto[0]	573644	1			T21	15		T29	59		T31	1763
all_values[12]	auto[0]	auto[1]	auto[1]	5283687	1			T21	107		T29	437		T31	15770
all_values[12]	auto[1]	auto[0]	auto[1]	77181	1			T31	64		T32	664		T33	54
all_values[12]	auto[1]	auto[1]	auto[1]	76581	1			T31	114		T32	764		T33	45
all_values[13]	auto[0]	auto[0]	auto[0]	2679069	1			T21	15		T22	204		T23	128
all_values[13]	auto[0]	auto[0]	auto[1]	5308158	1			T21	99		T29	579		T31	13908
all_values[13]	auto[0]	auto[1]	auto[0]	582271	1			T21	21		T29	48		T31	1566
all_values[13]	auto[0]	auto[1]	auto[1]	5306528	1			T21	72		T29	730		T31	14534
all_values[13]	auto[1]	auto[0]	auto[1]	77124	1			T31	95		T32	723		T33	69
all_values[13]	auto[1]	auto[1]	auto[1]	77081	1			T31	92		T32	727		T33	57
all_values[14]	auto[0]	auto[0]	auto[0]	2684155	1			T21	17		T22	204		T23	128
all_values[14]	auto[0]	auto[0]	auto[1]	5347492	1			T21	87		T29	741		T31	14914
all_values[14]	auto[0]	auto[1]	auto[0]	570610	1			T21	17		T29	27		T31	1676
all_values[14]	auto[0]	auto[1]	auto[1]	5273969	1			T21	86		T29	575		T31	13442
all_values[14]	auto[1]	auto[0]	auto[1]	77377	1			T31	91		T32	697		T33	75
all_values[14]	auto[1]	auto[1]	auto[1]	76628	1			T31	84		T32	680		T33	47
all_values[15]	auto[0]	auto[0]	auto[0]	2688367	1			T21	28		T22	204		T23	128
all_values[15]	auto[0]	auto[0]	auto[1]	5329962	1			T21	106		T29	557		T31	14646
all_values[15]	auto[0]	auto[1]	auto[0]	574570	1			T21	5		T29	83		T31	1539
all_values[15]	auto[0]	auto[1]	auto[1]	5284010	1			T21	68		T29	682		T31	14080
all_values[15]	auto[1]	auto[0]	auto[1]	77276	1			T31	85		T32	737		T33	63
all_values[15]	auto[1]	auto[1]	auto[1]	76046	1			T31	100		T32	660		T33	40
all_values[16]	auto[0]	auto[0]	auto[0]	2682135	1			T21	15		T22	204		T23	128
all_values[16]	auto[0]	auto[0]	auto[1]	5301404	1			T21	103		T29	733		T31	13680
all_values[16]	auto[0]	auto[1]	auto[0]	563961	1			T21	29		T29	117		T31	1492
all_values[16]	auto[0]	auto[1]	auto[1]	5328155	1			T21	60		T29	495		T31	15177
all_values[16]	auto[1]	auto[0]	auto[1]	77555	1			T31	81		T32	765		T33	41
all_values[16]	auto[1]	auto[1]	auto[1]	77021	1			T31	89		T32	651		T33	59
all_values[17]	auto[0]	auto[0]	auto[0]	2676420	1			T21	49		T22	204		T23	128
all_values[17]	auto[0]	auto[0]	auto[1]	5307952	1			T21	52		T29	580		T31	14387
all_values[17]	auto[0]	auto[1]	auto[0]	573665	1			T21	16		T29	65		T31	1388
all_values[17]	auto[0]	auto[1]	auto[1]	5318107	1			T21	90		T29	687		T31	14430
all_values[17]	auto[1]	auto[0]	auto[1]	77448	1			T31	102		T32	708		T33	50
all_values[17]	auto[1]	auto[1]	auto[1]	76639	1			T31	85		T32	695		T33	51
all_values[18]	auto[0]	auto[0]	auto[0]	2684609	1			T21	13		T22	204		T23	128
all_values[18]	auto[0]	auto[0]	auto[1]	5344323	1			T21	42		T29	814		T31	15028
all_values[18]	auto[0]	auto[1]	auto[0]	581463	1			T21	34		T29	24		T31	1549
all_values[18]	auto[0]	auto[1]	auto[1]	5265771	1			T21	118		T29	485		T31	13333
all_values[18]	auto[1]	auto[0]	auto[1]	77431	1			T31	94		T32	708		T33	57
all_values[18]	auto[1]	auto[1]	auto[1]	76634	1			T31	93		T32	693		T33	51
all_values[19]	auto[0]	auto[0]	auto[0]	2686491	1			T21	16		T22	204		T23	128
all_values[19]	auto[0]	auto[0]	auto[1]	5344071	1			T21	83		T29	682		T31	14887
all_values[19]	auto[0]	auto[1]	auto[0]	571654	1			T21	27		T29	31		T31	1556
all_values[19]	auto[0]	auto[1]	auto[1]	5274236	1			T21	81		T29	642		T31	13511
all_values[19]	auto[1]	auto[0]	auto[1]	76823	1			T31	86		T32	797		T33	71
all_values[19]	auto[1]	auto[1]	auto[1]	76956	1			T31	98		T32	660		T33	42
all_values[20]	auto[0]	auto[0]	auto[0]	2691068	1			T21	9		T22	204		T23	128
all_values[20]	auto[0]	auto[0]	auto[1]	5318912	1			T21	78		T29	879		T31	13868
all_values[20]	auto[0]	auto[1]	auto[0]	573645	1			T21	2		T29	30		T31	1891
all_values[20]	auto[0]	auto[1]	auto[1]	5292296	1			T21	118		T29	423		T31	14377
all_values[20]	auto[1]	auto[0]	auto[1]	77096	1			T31	81		T32	702		T33	45
all_values[20]	auto[1]	auto[1]	auto[1]	77214	1			T31	106		T32	717		T33	63
all_values[21]	auto[0]	auto[0]	auto[0]	2689494	1			T21	15		T22	204		T23	128
all_values[21]	auto[0]	auto[0]	auto[1]	5296984	1			T21	43		T29	906		T31	13433
all_values[21]	auto[0]	auto[1]	auto[0]	578036	1			T21	29		T29	66		T31	1595
all_values[21]	auto[0]	auto[1]	auto[1]	5311843	1			T21	120		T29	303		T31	15229
all_values[21]	auto[1]	auto[0]	auto[1]	76626	1			T31	96		T32	745		T33	56
all_values[21]	auto[1]	auto[1]	auto[1]	77248	1			T31	105		T32	734		T33	70
all_values[22]	auto[0]	auto[0]	auto[0]	2678311	1			T21	7		T22	204		T23	128
all_values[22]	auto[0]	auto[0]	auto[1]	5302973	1			T21	87		T29	596		T31	14318
all_values[22]	auto[0]	auto[1]	auto[0]	579166	1			T21	5		T29	94		T31	1703
all_values[22]	auto[0]	auto[1]	auto[1]	5315676	1			T21	108		T29	658		T31	13284
all_values[22]	auto[1]	auto[0]	auto[1]	77392	1			T31	88		T32	702		T33	52
all_values[22]	auto[1]	auto[1]	auto[1]	76713	1			T31	90		T32	688		T33	70
all_values[23]	auto[0]	auto[0]	auto[0]	2691547	1			T21	11		T22	204		T23	128
all_values[23]	auto[0]	auto[0]	auto[1]	5322842	1			T21	85		T29	847		T31	14228
all_values[23]	auto[0]	auto[1]	auto[0]	576535	1			T21	9		T29	49		T31	1841
all_values[23]	auto[0]	auto[1]	auto[1]	5285454	1			T21	102		T29	441		T31	14019
all_values[23]	auto[1]	auto[0]	auto[1]	77648	1			T31	88		T32	688		T33	61
all_values[23]	auto[1]	auto[1]	auto[1]	76205	1			T31	98		T32	724		T33	49
all_values[24]	auto[0]	auto[0]	auto[0]	2683432	1			T21	14		T22	204		T23	128
all_values[24]	auto[0]	auto[0]	auto[1]	5310093	1			T21	90		T29	445		T31	12393
all_values[24]	auto[0]	auto[1]	auto[0]	579362	1			T21	3		T29	54		T31	1846
all_values[24]	auto[0]	auto[1]	auto[1]	5303167	1			T21	100		T29	826		T31	15812
all_values[24]	auto[1]	auto[0]	auto[1]	76957	1			T31	74		T32	734		T33	53
all_values[24]	auto[1]	auto[1]	auto[1]	77220	1			T31	95		T32	711		T33	53
all_values[25]	auto[0]	auto[0]	auto[0]	2679129	1			T21	10		T22	204		T23	128
all_values[25]	auto[0]	auto[0]	auto[1]	5315889	1			T21	97		T29	825		T31	13929
all_values[25]	auto[0]	auto[1]	auto[0]	580276	1			T21	5		T29	63		T31	1597
all_values[25]	auto[0]	auto[1]	auto[1]	5300776	1			T21	95		T29	406		T31	14501
all_values[25]	auto[1]	auto[0]	auto[1]	77204	1			T31	71		T32	714		T33	63
all_values[25]	auto[1]	auto[1]	auto[1]	76957	1			T31	95		T32	699		T33	65
all_values[26]	auto[0]	auto[0]	auto[0]	2681525	1			T21	28		T22	204		T23	128
all_values[26]	auto[0]	auto[0]	auto[1]	5307517	1			T21	71		T29	749		T31	13738
all_values[26]	auto[0]	auto[1]	auto[0]	580030	1			T21	39		T29	66		T31	1618
all_values[26]	auto[0]	auto[1]	auto[1]	5307774	1			T21	69		T29	503		T31	14683
all_values[26]	auto[1]	auto[0]	auto[1]	76445	1			T31	66		T32	748		T33	56
all_values[26]	auto[1]	auto[1]	auto[1]	76940	1			T31	108		T32	703		T33	51
all_values[27]	auto[0]	auto[0]	auto[0]	2671403	1			T21	9		T22	204		T23	128
all_values[27]	auto[0]	auto[0]	auto[1]	5321499	1			T21	76		T29	413		T31	14326
all_values[27]	auto[0]	auto[1]	auto[0]	568549	1			T21	11		T29	46		T31	1715
all_values[27]	auto[0]	auto[1]	auto[1]	5314637	1			T21	111		T29	905		T31	14087
all_values[27]	auto[1]	auto[0]	auto[1]	77100	1			T31	103		T32	715		T33	55
all_values[27]	auto[1]	auto[1]	auto[1]	77043	1			T31	104		T32	697		T33	67
all_values[28]	auto[0]	auto[0]	auto[0]	2679618	1			T21	11		T22	204		T23	128
all_values[28]	auto[0]	auto[0]	auto[1]	5290192	1			T21	111		T29	497		T31	13472
all_values[28]	auto[0]	auto[1]	auto[0]	578120	1			T21	8		T29	63		T31	1577
all_values[28]	auto[0]	auto[1]	auto[1]	5328080	1			T21	77		T29	805		T31	14976
all_values[28]	auto[1]	auto[0]	auto[1]	77394	1			T31	79		T32	707		T33	53
all_values[28]	auto[1]	auto[1]	auto[1]	76827	1			T31	92		T32	719		T33	61
all_values[29]	auto[0]	auto[0]	auto[0]	2675019	1			T21	34		T22	204		T23	128
all_values[29]	auto[0]	auto[0]	auto[1]	5333578	1			T21	60		T29	652		T31	14163
all_values[29]	auto[0]	auto[1]	auto[0]	579586	1			T21	38		T29	55		T31	1699
all_values[29]	auto[0]	auto[1]	auto[1]	5287976	1			T21	75		T29	612		T31	14361
all_values[29]	auto[1]	auto[0]	auto[1]	77449	1			T31	96		T32	682		T33	54
all_values[29]	auto[1]	auto[1]	auto[1]	76623	1			T31	75		T32	731		T33	45
all_values[30]	auto[0]	auto[0]	auto[0]	2682775	1			T21	11		T22	204		T23	128
all_values[30]	auto[0]	auto[0]	auto[1]	5312236	1			T21	86		T29	781		T31	14614
all_values[30]	auto[0]	auto[1]	auto[0]	567915	1			T21	2		T29	24		T31	1473
all_values[30]	auto[0]	auto[1]	auto[1]	5313571	1			T21	108		T29	535		T31	14077
all_values[30]	auto[1]	auto[0]	auto[1]	77398	1			T31	83		T32	761		T33	52
all_values[30]	auto[1]	auto[1]	auto[1]	76336	1			T31	113		T32	676		T33	58
all_values[31]	auto[0]	auto[0]	auto[0]	2678481	1			T21	16		T22	204		T23	128
all_values[31]	auto[0]	auto[0]	auto[1]	5331315	1			T21	123		T29	812		T31	15818
all_values[31]	auto[0]	auto[1]	auto[0]	576221	1			T21	21		T29	26		T31	1498
all_values[31]	auto[0]	auto[1]	auto[1]	5290427	1			T21	47		T29	478		T31	12643
all_values[31]	auto[1]	auto[0]	auto[1]	77304	1			T31	117		T32	752		T33	36
all_values[31]	auto[1]	auto[1]	auto[1]	76483	1			T31	84		T32	653		T33	47

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal