Unified Coverage Report :: Group :: gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

Group : gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_gpio_env_0.1/gpio_env_cov.sv

---

Summary for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	192	0	192	100.00

Variables for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_pin	32	0	32	100.00	100	1	1	0
data_in	2	0	2	100.00	100	1	1	2
data_oe	2	0	2	100.00	100	1	1	2
data_out	2	0	2	100.00	100	1	1	2

Crosses for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_cross_all	192	0	192	100.00	100	1	1	0

Summary for Variable cp_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	13816073	1			T21	127		T22	366		T23	230
bins_for_gpio_bits[1]	13816073	1			T21	127		T22	366		T23	230
bins_for_gpio_bits[2]	13816073	1			T21	127		T22	366		T23	230
bins_for_gpio_bits[3]	13816073	1			T21	127		T22	366		T23	230
bins_for_gpio_bits[4]	13816073	1			T21	127		T22	366		T23	230
bins_for_gpio_bits[5]	13816073	1			T21	127		T22	366		T23	230
bins_for_gpio_bits[6]	13816073	1			T21	127		T22	366		T23	230
bins_for_gpio_bits[7]	13816073	1			T21	127		T22	366		T23	230
bins_for_gpio_bits[8]	13816073	1			T21	127		T22	366		T23	230
bins_for_gpio_bits[9]	13816073	1			T21	127		T22	366		T23	230
bins_for_gpio_bits[10]	13816073	1			T21	127		T22	366		T23	230
bins_for_gpio_bits[11]	13816073	1			T21	127		T22	366		T23	230
bins_for_gpio_bits[12]	13816073	1			T21	127		T22	366		T23	230
bins_for_gpio_bits[13]	13816073	1			T21	127		T22	366		T23	230
bins_for_gpio_bits[14]	13816073	1			T21	127		T22	366		T23	230
bins_for_gpio_bits[15]	13816073	1			T21	127		T22	366		T23	230
bins_for_gpio_bits[16]	13816073	1			T21	127		T22	366		T23	230
bins_for_gpio_bits[17]	13816073	1			T21	127		T22	366		T23	230
bins_for_gpio_bits[18]	13816073	1			T21	127		T22	366		T23	230
bins_for_gpio_bits[19]	13816073	1			T21	127		T22	366		T23	230
bins_for_gpio_bits[20]	13816073	1			T21	127		T22	366		T23	230
bins_for_gpio_bits[21]	13816073	1			T21	127		T22	366		T23	230
bins_for_gpio_bits[22]	13816073	1			T21	127		T22	366		T23	230
bins_for_gpio_bits[23]	13816073	1			T21	127		T22	366		T23	230
bins_for_gpio_bits[24]	13816073	1			T21	127		T22	366		T23	230
bins_for_gpio_bits[25]	13816073	1			T21	127		T22	366		T23	230
bins_for_gpio_bits[26]	13816073	1			T21	127		T22	366		T23	230
bins_for_gpio_bits[27]	13816073	1			T21	127		T22	366		T23	230
bins_for_gpio_bits[28]	13816073	1			T21	127		T22	366		T23	230
bins_for_gpio_bits[29]	13816073	1			T21	127		T22	366		T23	230
bins_for_gpio_bits[30]	13816073	1			T21	127		T22	366		T23	230
bins_for_gpio_bits[31]	13816073	1			T21	127		T22	366		T23	230

---

Summary for Variable data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

265780282

1

T21

1990

T22

3183

T23

5938

auto[1]

176334054

1

T21

2074

T22

8529

T23

1422

---

Summary for Variable data_oe

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_oe

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

354464782

1

T21

4064

T22

6396

T23

6849

auto[1]

87649554

1

T22

5316

T23

511

T25

7018

---

Summary for Variable data_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_out

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

328869093

1

T21

4064

T22

6307

T23

3825

auto[1]

113245243

1

T22

5405

T23

3535

T25

6986

---

Summary for Cross cp_cross_all

Samples crossed: cp_pin data_out data_oe data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	192	0	192	100.00
Automatically Generated Cross Bins	192	0	192	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cp_cross_all

Bins

cp_pin	data_out	data_oe	data_in	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	auto[0]	auto[0]	auto[0]	5164706	1			T21	60		T22	16		T23	83
bins_for_gpio_bits[0]	auto[0]	auto[0]	auto[1]	3734029	1			T21	67		T22	115		T23	19
bins_for_gpio_bits[0]	auto[0]	auto[1]	auto[0]	1376849	1			T22	56		T23	7		T25	122
bins_for_gpio_bits[0]	auto[1]	auto[0]	auto[0]	1771822	1			T23	97		T25	72		T30	181
bins_for_gpio_bits[0]	auto[1]	auto[0]	auto[1]	400090	1			T22	87		T23	22		T30	16
bins_for_gpio_bits[0]	auto[1]	auto[1]	auto[1]	1368577	1			T22	92		T23	2		T25	123
bins_for_gpio_bits[1]	auto[0]	auto[0]	auto[0]	5143727	1			T21	64		T22	19		T23	51
bins_for_gpio_bits[1]	auto[0]	auto[0]	auto[1]	3745458	1			T21	63		T22	88		T23	14
bins_for_gpio_bits[1]	auto[0]	auto[1]	auto[0]	1381771	1			T22	84		T23	6		T25	108
bins_for_gpio_bits[1]	auto[1]	auto[0]	auto[0]	1775877	1			T23	122		T25	100		T30	183
bins_for_gpio_bits[1]	auto[1]	auto[0]	auto[1]	400462	1			T22	87		T23	30		T30	18
bins_for_gpio_bits[1]	auto[1]	auto[1]	auto[1]	1368778	1			T22	88		T23	7		T25	128
bins_for_gpio_bits[2]	auto[0]	auto[0]	auto[0]	5153135	1			T21	65		T22	23		T23	116
bins_for_gpio_bits[2]	auto[0]	auto[0]	auto[1]	3744830	1			T21	62		T22	88		T23	22
bins_for_gpio_bits[2]	auto[0]	auto[1]	auto[0]	1381757	1			T22	92		T23	6		T25	96
bins_for_gpio_bits[2]	auto[1]	auto[0]	auto[0]	1769242	1			T23	67		T25	126		T30	129
bins_for_gpio_bits[2]	auto[1]	auto[0]	auto[1]	401032	1			T22	78		T23	15		T30	8
bins_for_gpio_bits[2]	auto[1]	auto[1]	auto[1]	1366077	1			T22	85		T23	4		T25	125
bins_for_gpio_bits[3]	auto[0]	auto[0]	auto[0]	5159440	1			T21	67		T22	13		T23	102
bins_for_gpio_bits[3]	auto[0]	auto[0]	auto[1]	3742163	1			T21	60		T22	100		T23	22
bins_for_gpio_bits[3]	auto[0]	auto[1]	auto[0]	1379302	1			T22	86		T23	4		T25	114
bins_for_gpio_bits[3]	auto[1]	auto[0]	auto[0]	1770831	1			T23	78		T25	112		T30	161
bins_for_gpio_bits[3]	auto[1]	auto[0]	auto[1]	401450	1			T22	69		T23	16		T30	24
bins_for_gpio_bits[3]	auto[1]	auto[1]	auto[1]	1362887	1			T22	98		T23	8		T25	119
bins_for_gpio_bits[4]	auto[0]	auto[0]	auto[0]	5162592	1			T21	57		T22	19		T23	163
bins_for_gpio_bits[4]	auto[0]	auto[0]	auto[1]	3734606	1			T21	70		T22	94		T23	39
bins_for_gpio_bits[4]	auto[0]	auto[1]	auto[0]	1375011	1			T22	66		T23	10		T25	104
bins_for_gpio_bits[4]	auto[1]	auto[0]	auto[0]	1771744	1			T23	11		T25	122		T30	127
bins_for_gpio_bits[4]	auto[1]	auto[0]	auto[1]	402994	1			T22	93		T23	1		T30	13
bins_for_gpio_bits[4]	auto[1]	auto[1]	auto[1]	1369126	1			T22	94		T23	6		T25	117
bins_for_gpio_bits[5]	auto[0]	auto[0]	auto[0]	5148297	1			T21	60		T22	24		T23	139
bins_for_gpio_bits[5]	auto[0]	auto[0]	auto[1]	3753575	1			T21	67		T22	93		T23	31
bins_for_gpio_bits[5]	auto[0]	auto[1]	auto[0]	1381640	1			T22	73		T23	14		T25	112
bins_for_gpio_bits[5]	auto[1]	auto[0]	auto[0]	1767389	1			T23	38		T25	107		T30	111
bins_for_gpio_bits[5]	auto[1]	auto[0]	auto[1]	401401	1			T22	100		T23	8		T30	11
bins_for_gpio_bits[5]	auto[1]	auto[1]	auto[1]	1363771	1			T22	76		T25	116		T30	46
bins_for_gpio_bits[6]	auto[0]	auto[0]	auto[0]	5150502	1			T21	56		T22	17		T23	81
bins_for_gpio_bits[6]	auto[0]	auto[0]	auto[1]	3750242	1			T21	71		T22	123		T23	17
bins_for_gpio_bits[6]	auto[0]	auto[1]	auto[0]	1376106	1			T22	58		T25	107		T30	76
bins_for_gpio_bits[6]	auto[1]	auto[0]	auto[0]	1773134	1			T23	99		T25	118		T30	149
bins_for_gpio_bits[6]	auto[1]	auto[0]	auto[1]	402466	1			T22	102		T23	17		T30	9
bins_for_gpio_bits[6]	auto[1]	auto[1]	auto[1]	1363623	1			T22	66		T23	16		T25	94
bins_for_gpio_bits[7]	auto[0]	auto[0]	auto[0]	5149505	1			T21	65		T22	20		T23	101
bins_for_gpio_bits[7]	auto[0]	auto[0]	auto[1]	3749928	1			T21	62		T22	83		T23	26
bins_for_gpio_bits[7]	auto[0]	auto[1]	auto[0]	1378612	1			T22	80		T23	13		T25	104
bins_for_gpio_bits[7]	auto[1]	auto[0]	auto[0]	1770027	1			T23	69		T25	119		T30	95
bins_for_gpio_bits[7]	auto[1]	auto[0]	auto[1]	404121	1			T22	94		T23	15		T30	17
bins_for_gpio_bits[7]	auto[1]	auto[1]	auto[1]	1363880	1			T22	89		T23	6		T25	88
bins_for_gpio_bits[8]	auto[0]	auto[0]	auto[0]	5150920	1			T21	65		T22	22		T23	128
bins_for_gpio_bits[8]	auto[0]	auto[0]	auto[1]	3750189	1			T21	62		T22	83		T23	26
bins_for_gpio_bits[8]	auto[0]	auto[1]	auto[0]	1375739	1			T22	86		T23	6		T25	148
bins_for_gpio_bits[8]	auto[1]	auto[0]	auto[0]	1774105	1			T23	55		T25	78		T30	157
bins_for_gpio_bits[8]	auto[1]	auto[0]	auto[1]	400267	1			T22	80		T23	11		T30	17
bins_for_gpio_bits[8]	auto[1]	auto[1]	auto[1]	1364853	1			T22	95		T23	4		T25	105
bins_for_gpio_bits[9]	auto[0]	auto[0]	auto[0]	5148928	1			T21	57		T22	21		T23	16
bins_for_gpio_bits[9]	auto[0]	auto[0]	auto[1]	3743707	1			T21	70		T22	86		T23	3
bins_for_gpio_bits[9]	auto[0]	auto[1]	auto[0]	1375823	1			T22	71		T25	122		T30	41
bins_for_gpio_bits[9]	auto[1]	auto[0]	auto[0]	1774456	1			T23	153		T25	86		T30	134
bins_for_gpio_bits[9]	auto[1]	auto[0]	auto[1]	402777	1			T22	102		T23	34		T30	15
bins_for_gpio_bits[9]	auto[1]	auto[1]	auto[1]	1370382	1			T22	86		T23	24		T25	102
bins_for_gpio_bits[10]	auto[0]	auto[0]	auto[0]	5155556	1			T21	52		T22	17		T23	72
bins_for_gpio_bits[10]	auto[0]	auto[0]	auto[1]	3742601	1			T21	75		T22	106		T23	12
bins_for_gpio_bits[10]	auto[0]	auto[1]	auto[0]	1379342	1			T22	100		T23	3		T25	111
bins_for_gpio_bits[10]	auto[1]	auto[0]	auto[0]	1773093	1			T23	122		T25	110		T30	127
bins_for_gpio_bits[10]	auto[1]	auto[0]	auto[1]	400939	1			T22	47		T23	19		T30	11
bins_for_gpio_bits[10]	auto[1]	auto[1]	auto[1]	1364542	1			T22	96		T23	2		T25	138
bins_for_gpio_bits[11]	auto[0]	auto[0]	auto[0]	5156834	1			T21	51		T22	20		T23	142
bins_for_gpio_bits[11]	auto[0]	auto[0]	auto[1]	3744018	1			T21	76		T22	97		T23	29
bins_for_gpio_bits[11]	auto[0]	auto[1]	auto[0]	1382966	1			T22	66		T23	17		T25	92
bins_for_gpio_bits[11]	auto[1]	auto[0]	auto[0]	1765179	1			T23	34		T25	104		T30	213
bins_for_gpio_bits[11]	auto[1]	auto[0]	auto[1]	402431	1			T22	96		T23	6		T30	21
bins_for_gpio_bits[11]	auto[1]	auto[1]	auto[1]	1364645	1			T22	87		T23	2		T25	104
bins_for_gpio_bits[12]	auto[0]	auto[0]	auto[0]	5142287	1			T21	70		T22	26		T23	154
bins_for_gpio_bits[12]	auto[0]	auto[0]	auto[1]	3749793	1			T21	57		T22	105		T23	20
bins_for_gpio_bits[12]	auto[0]	auto[1]	auto[0]	1379183	1			T22	92		T23	16		T25	124
bins_for_gpio_bits[12]	auto[1]	auto[0]	auto[0]	1770886	1			T23	34		T25	104		T30	170
bins_for_gpio_bits[12]	auto[1]	auto[0]	auto[1]	402920	1			T22	70		T23	4		T30	12
bins_for_gpio_bits[12]	auto[1]	auto[1]	auto[1]	1371004	1			T22	73		T23	2		T25	96
bins_for_gpio_bits[13]	auto[0]	auto[0]	auto[0]	5142988	1			T21	67		T22	20		T23	36
bins_for_gpio_bits[13]	auto[0]	auto[0]	auto[1]	3752153	1			T21	60		T22	81		T23	8
bins_for_gpio_bits[13]	auto[0]	auto[1]	auto[0]	1376965	1			T22	102		T23	4		T25	142
bins_for_gpio_bits[13]	auto[1]	auto[0]	auto[0]	1774044	1			T23	127		T25	84		T30	119
bins_for_gpio_bits[13]	auto[1]	auto[0]	auto[1]	403136	1			T22	73		T23	39		T30	14
bins_for_gpio_bits[13]	auto[1]	auto[1]	auto[1]	1366787	1			T22	90		T23	16		T25	115
bins_for_gpio_bits[14]	auto[0]	auto[0]	auto[0]	5150487	1			T21	59		T22	14		T23	65
bins_for_gpio_bits[14]	auto[0]	auto[0]	auto[1]	3748250	1			T21	68		T22	98		T23	14
bins_for_gpio_bits[14]	auto[0]	auto[1]	auto[0]	1378013	1			T22	94		T23	5		T25	98
bins_for_gpio_bits[14]	auto[1]	auto[0]	auto[0]	1768770	1			T23	110		T25	121		T30	52
bins_for_gpio_bits[14]	auto[1]	auto[0]	auto[1]	403357	1			T22	82		T23	26		T30	11
bins_for_gpio_bits[14]	auto[1]	auto[1]	auto[1]	1367196	1			T22	78		T23	10		T25	118
bins_for_gpio_bits[15]	auto[0]	auto[0]	auto[0]	5142536	1			T21	66		T22	24		T23	43
bins_for_gpio_bits[15]	auto[0]	auto[0]	auto[1]	3757806	1			T21	61		T22	91		T23	5
bins_for_gpio_bits[15]	auto[0]	auto[1]	auto[0]	1381533	1			T22	88		T25	116		T30	49
bins_for_gpio_bits[15]	auto[1]	auto[0]	auto[0]	1768425	1			T23	154		T25	87		T30	133
bins_for_gpio_bits[15]	auto[1]	auto[0]	auto[1]	399456	1			T22	71		T23	22		T30	18
bins_for_gpio_bits[15]	auto[1]	auto[1]	auto[1]	1366317	1			T22	92		T23	6		T25	96
bins_for_gpio_bits[16]	auto[0]	auto[0]	auto[0]	5152950	1			T21	62		T22	22		T23	101
bins_for_gpio_bits[16]	auto[0]	auto[0]	auto[1]	3747699	1			T21	65		T22	101		T23	18
bins_for_gpio_bits[16]	auto[0]	auto[1]	auto[0]	1370863	1			T22	83		T23	14		T25	74
bins_for_gpio_bits[16]	auto[1]	auto[0]	auto[0]	1779180	1			T23	77		T25	125		T30	153
bins_for_gpio_bits[16]	auto[1]	auto[0]	auto[1]	403808	1			T22	70		T23	14		T30	13
bins_for_gpio_bits[16]	auto[1]	auto[1]	auto[1]	1361573	1			T22	90		T23	6		T25	110
bins_for_gpio_bits[17]	auto[0]	auto[0]	auto[0]	5157066	1			T21	63		T22	27		T23	117
bins_for_gpio_bits[17]	auto[0]	auto[0]	auto[1]	3745132	1			T21	64		T22	72		T23	21
bins_for_gpio_bits[17]	auto[0]	auto[1]	auto[0]	1372930	1			T22	100		T23	10		T25	105
bins_for_gpio_bits[17]	auto[1]	auto[0]	auto[0]	1780373	1			T23	68		T25	128		T30	136
bins_for_gpio_bits[17]	auto[1]	auto[0]	auto[1]	402198	1			T22	66		T23	5		T30	22
bins_for_gpio_bits[17]	auto[1]	auto[1]	auto[1]	1358374	1			T22	101		T23	9		T25	112
bins_for_gpio_bits[18]	auto[0]	auto[0]	auto[0]	5165210	1			T21	60		T22	20		T23	100
bins_for_gpio_bits[18]	auto[0]	auto[0]	auto[1]	3740915	1			T21	67		T22	123		T23	20
bins_for_gpio_bits[18]	auto[0]	auto[1]	auto[0]	1371495	1			T22	83		T23	12		T25	112
bins_for_gpio_bits[18]	auto[1]	auto[0]	auto[0]	1777215	1			T23	67		T25	120		T30	128
bins_for_gpio_bits[18]	auto[1]	auto[0]	auto[1]	402132	1			T22	70		T23	20		T30	15
bins_for_gpio_bits[18]	auto[1]	auto[1]	auto[1]	1359106	1			T22	70		T23	11		T25	108
bins_for_gpio_bits[19]	auto[0]	auto[0]	auto[0]	5155973	1			T21	54		T22	12		T23	96
bins_for_gpio_bits[19]	auto[0]	auto[0]	auto[1]	3744487	1			T21	73		T22	97		T23	16
bins_for_gpio_bits[19]	auto[0]	auto[1]	auto[0]	1372854	1			T22	86		T23	15		T25	92
bins_for_gpio_bits[19]	auto[1]	auto[0]	auto[0]	1777270	1			T23	76		T25	98		T30	114
bins_for_gpio_bits[19]	auto[1]	auto[0]	auto[1]	400204	1			T22	85		T23	19		T30	15
bins_for_gpio_bits[19]	auto[1]	auto[1]	auto[1]	1365285	1			T22	86		T23	8		T25	149
bins_for_gpio_bits[20]	auto[0]	auto[0]	auto[0]	5164186	1			T21	59		T22	25		T23	107
bins_for_gpio_bits[20]	auto[0]	auto[0]	auto[1]	3737660	1			T21	68		T22	79		T23	26
bins_for_gpio_bits[20]	auto[0]	auto[1]	auto[0]	1374721	1			T22	86		T23	12		T25	111
bins_for_gpio_bits[20]	auto[1]	auto[0]	auto[0]	1776782	1			T23	69		T25	118		T30	170
bins_for_gpio_bits[20]	auto[1]	auto[0]	auto[1]	402721	1			T22	94		T23	16		T30	20
bins_for_gpio_bits[20]	auto[1]	auto[1]	auto[1]	1360003	1			T22	82		T25	110		T30	66
bins_for_gpio_bits[21]	auto[0]	auto[0]	auto[0]	5168483	1			T21	70		T22	22		T23	46
bins_for_gpio_bits[21]	auto[0]	auto[0]	auto[1]	3738165	1			T21	57		T22	99		T23	8
bins_for_gpio_bits[21]	auto[0]	auto[1]	auto[0]	1374604	1			T22	70		T23	4		T25	88
bins_for_gpio_bits[21]	auto[1]	auto[0]	auto[0]	1771484	1			T23	138		T25	116		T30	140
bins_for_gpio_bits[21]	auto[1]	auto[0]	auto[1]	401901	1			T22	100		T23	26		T30	10
bins_for_gpio_bits[21]	auto[1]	auto[1]	auto[1]	1361436	1			T22	75		T23	8		T25	112
bins_for_gpio_bits[22]	auto[0]	auto[0]	auto[0]	5170740	1			T21	62		T22	22		T23	76
bins_for_gpio_bits[22]	auto[0]	auto[0]	auto[1]	3734523	1			T21	65		T22	89		T23	18
bins_for_gpio_bits[22]	auto[0]	auto[1]	auto[0]	1370862	1			T22	76		T23	2		T25	123
bins_for_gpio_bits[22]	auto[1]	auto[0]	auto[0]	1776311	1			T23	91		T25	106		T30	155
bins_for_gpio_bits[22]	auto[1]	auto[0]	auto[1]	403733	1			T22	79		T23	23		T30	24
bins_for_gpio_bits[22]	auto[1]	auto[1]	auto[1]	1359904	1			T22	100		T23	20		T25	102
bins_for_gpio_bits[23]	auto[0]	auto[0]	auto[0]	5162499	1			T21	65		T22	19		T23	113
bins_for_gpio_bits[23]	auto[0]	auto[0]	auto[1]	3742229	1			T21	62		T22	82		T23	36
bins_for_gpio_bits[23]	auto[0]	auto[1]	auto[0]	1374664	1			T22	70		T23	10		T25	131
bins_for_gpio_bits[23]	auto[1]	auto[0]	auto[0]	1771891	1			T23	57		T25	82		T30	128
bins_for_gpio_bits[23]	auto[1]	auto[0]	auto[1]	402813	1			T22	73		T23	8		T30	20
bins_for_gpio_bits[23]	auto[1]	auto[1]	auto[1]	1361977	1			T22	122		T23	6		T25	98
bins_for_gpio_bits[24]	auto[0]	auto[0]	auto[0]	5156221	1			T21	67		T22	19		T23	40
bins_for_gpio_bits[24]	auto[0]	auto[0]	auto[1]	3751744	1			T21	60		T22	90		T23	9
bins_for_gpio_bits[24]	auto[0]	auto[1]	auto[0]	1373470	1			T22	94		T23	5		T25	121
bins_for_gpio_bits[24]	auto[1]	auto[0]	auto[0]	1775870	1			T23	128		T25	104		T30	128
bins_for_gpio_bits[24]	auto[1]	auto[0]	auto[1]	401557	1			T22	72		T23	34		T30	20
bins_for_gpio_bits[24]	auto[1]	auto[1]	auto[1]	1357211	1			T22	91		T23	14		T25	100
bins_for_gpio_bits[25]	auto[0]	auto[0]	auto[0]	5154328	1			T21	58		T22	22		T23	170
bins_for_gpio_bits[25]	auto[0]	auto[0]	auto[1]	3752192	1			T21	69		T22	111		T23	37
bins_for_gpio_bits[25]	auto[0]	auto[1]	auto[0]	1374749	1			T22	78		T23	17		T25	128
bins_for_gpio_bits[25]	auto[1]	auto[0]	auto[0]	1774676	1			T23	4		T25	111		T30	117
bins_for_gpio_bits[25]	auto[1]	auto[0]	auto[1]	400685	1			T22	65		T30	17		T31	3707
bins_for_gpio_bits[25]	auto[1]	auto[1]	auto[1]	1359443	1			T22	90		T23	2		T25	100
bins_for_gpio_bits[26]	auto[0]	auto[0]	auto[0]	5160630	1			T21	64		T22	14		T23	109
bins_for_gpio_bits[26]	auto[0]	auto[0]	auto[1]	3747248	1			T21	63		T22	113		T23	21
bins_for_gpio_bits[26]	auto[0]	auto[1]	auto[0]	1372127	1			T22	40		T23	7		T25	90
bins_for_gpio_bits[26]	auto[1]	auto[0]	auto[0]	1775779	1			T23	76		T25	137		T30	198
bins_for_gpio_bits[26]	auto[1]	auto[0]	auto[1]	403401	1			T22	110		T23	13		T30	24
bins_for_gpio_bits[26]	auto[1]	auto[1]	auto[1]	1356888	1			T22	89		T23	4		T25	74
bins_for_gpio_bits[27]	auto[0]	auto[0]	auto[0]	5164215	1			T21	76		T22	19		T23	37
bins_for_gpio_bits[27]	auto[0]	auto[0]	auto[1]	3743116	1			T21	51		T22	118		T23	9
bins_for_gpio_bits[27]	auto[0]	auto[1]	auto[0]	1372742	1			T22	66		T23	6		T25	102
bins_for_gpio_bits[27]	auto[1]	auto[0]	auto[0]	1777710	1			T23	143		T25	117		T30	143
bins_for_gpio_bits[27]	auto[1]	auto[0]	auto[1]	403483	1			T22	85		T23	28		T30	17
bins_for_gpio_bits[27]	auto[1]	auto[1]	auto[1]	1354807	1			T22	78		T23	7		T25	98
bins_for_gpio_bits[28]	auto[0]	auto[0]	auto[0]	5147604	1			T21	70		T22	25		T23	97
bins_for_gpio_bits[28]	auto[0]	auto[0]	auto[1]	3753490	1			T21	57		T22	124		T23	14
bins_for_gpio_bits[28]	auto[0]	auto[1]	auto[0]	1375674	1			T22	69		T23	4		T25	88
bins_for_gpio_bits[28]	auto[1]	auto[0]	auto[0]	1774312	1			T23	96		T25	131		T30	184
bins_for_gpio_bits[28]	auto[1]	auto[0]	auto[1]	402416	1			T22	76		T23	11		T30	26
bins_for_gpio_bits[28]	auto[1]	auto[1]	auto[1]	1362577	1			T22	72		T23	8		T25	108
bins_for_gpio_bits[29]	auto[0]	auto[0]	auto[0]	5167903	1			T21	51		T22	21		T23	55
bins_for_gpio_bits[29]	auto[0]	auto[0]	auto[1]	3735794	1			T21	76		T22	84		T23	18
bins_for_gpio_bits[29]	auto[0]	auto[1]	auto[0]	1372153	1			T22	86		T23	11		T25	100
bins_for_gpio_bits[29]	auto[1]	auto[0]	auto[0]	1777339	1			T23	105		T25	143		T30	108
bins_for_gpio_bits[29]	auto[1]	auto[0]	auto[1]	400799	1			T22	76		T23	27		T30	9
bins_for_gpio_bits[29]	auto[1]	auto[1]	auto[1]	1362085	1			T22	99		T23	14		T25	100
bins_for_gpio_bits[30]	auto[0]	auto[0]	auto[0]	5156481	1			T21	61		T22	18		T23	32
bins_for_gpio_bits[30]	auto[0]	auto[0]	auto[1]	3743310	1			T21	66		T22	112		T23	7
bins_for_gpio_bits[30]	auto[0]	auto[1]	auto[0]	1371009	1			T22	76		T23	10		T25	106
bins_for_gpio_bits[30]	auto[1]	auto[0]	auto[0]	1776870	1			T23	140		T25	93		T30	102
bins_for_gpio_bits[30]	auto[1]	auto[0]	auto[1]	406488	1			T22	104		T23	31		T30	12
bins_for_gpio_bits[30]	auto[1]	auto[1]	auto[1]	1361915	1			T22	56		T23	10		T25	118
bins_for_gpio_bits[31]	auto[0]	auto[0]	auto[0]	5168725	1			T21	67		T22	18		T23	159
bins_for_gpio_bits[31]	auto[0]	auto[0]	auto[1]	3742920	1			T21	60		T22	99		T23	27
bins_for_gpio_bits[31]	auto[0]	auto[1]	auto[0]	1373938	1			T22	86		T23	16		T25	134
bins_for_gpio_bits[31]	auto[1]	auto[0]	auto[0]	1773075	1			T23	20		T25	114		T30	150
bins_for_gpio_bits[31]	auto[1]	auto[0]	auto[1]	402357	1			T22	76		T23	5		T30	21
bins_for_gpio_bits[31]	auto[1]	auto[1]	auto[1]	1355058	1			T22	87		T23	3		T25	110

User Defined Cross Bins for cp_cross_all

Excluded/Illegal bins

NAME	COUNT	STATUS
data_oe_1_data_out_0_data_in_1	0	Illegal
data_oe_1_data_out_1_data_in_0	0	Illegal