Unified Coverage Report :: Group :: gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

Group : gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_gpio_env_0.1/gpio_env_cov.sv

---

Summary for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	36	0	36	100.00
Crosses	128	0	128	100.00

Variables for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_pin	32	0	32	100.00	100	1	1	0
data_in	2	0	2	100.00	100	1	1	2
gpio_value	2	0	2	100.00	100	1	1	2

Crosses for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_cross_pins_data_in	128	0	128	100.00	100	1	1	0

Summary for Variable cp_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	13816073	1			T21	127		T22	366		T23	230
bins_for_gpio_bits[1]	13816073	1			T21	127		T22	366		T23	230
bins_for_gpio_bits[2]	13816073	1			T21	127		T22	366		T23	230
bins_for_gpio_bits[3]	13816073	1			T21	127		T22	366		T23	230
bins_for_gpio_bits[4]	13816073	1			T21	127		T22	366		T23	230
bins_for_gpio_bits[5]	13816073	1			T21	127		T22	366		T23	230
bins_for_gpio_bits[6]	13816073	1			T21	127		T22	366		T23	230
bins_for_gpio_bits[7]	13816073	1			T21	127		T22	366		T23	230
bins_for_gpio_bits[8]	13816073	1			T21	127		T22	366		T23	230
bins_for_gpio_bits[9]	13816073	1			T21	127		T22	366		T23	230
bins_for_gpio_bits[10]	13816073	1			T21	127		T22	366		T23	230
bins_for_gpio_bits[11]	13816073	1			T21	127		T22	366		T23	230
bins_for_gpio_bits[12]	13816073	1			T21	127		T22	366		T23	230
bins_for_gpio_bits[13]	13816073	1			T21	127		T22	366		T23	230
bins_for_gpio_bits[14]	13816073	1			T21	127		T22	366		T23	230
bins_for_gpio_bits[15]	13816073	1			T21	127		T22	366		T23	230
bins_for_gpio_bits[16]	13816073	1			T21	127		T22	366		T23	230
bins_for_gpio_bits[17]	13816073	1			T21	127		T22	366		T23	230
bins_for_gpio_bits[18]	13816073	1			T21	127		T22	366		T23	230
bins_for_gpio_bits[19]	13816073	1			T21	127		T22	366		T23	230
bins_for_gpio_bits[20]	13816073	1			T21	127		T22	366		T23	230
bins_for_gpio_bits[21]	13816073	1			T21	127		T22	366		T23	230
bins_for_gpio_bits[22]	13816073	1			T21	127		T22	366		T23	230
bins_for_gpio_bits[23]	13816073	1			T21	127		T22	366		T23	230
bins_for_gpio_bits[24]	13816073	1			T21	127		T22	366		T23	230
bins_for_gpio_bits[25]	13816073	1			T21	127		T22	366		T23	230
bins_for_gpio_bits[26]	13816073	1			T21	127		T22	366		T23	230
bins_for_gpio_bits[27]	13816073	1			T21	127		T22	366		T23	230
bins_for_gpio_bits[28]	13816073	1			T21	127		T22	366		T23	230
bins_for_gpio_bits[29]	13816073	1			T21	127		T22	366		T23	230
bins_for_gpio_bits[30]	13816073	1			T21	127		T22	366		T23	230
bins_for_gpio_bits[31]	13816073	1			T21	127		T22	366		T23	230

---

Summary for Variable data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

265780282

1

T21

1990

T22

3183

T23

5938

auto[1]

176334054

1

T21

2074

T22

8529

T23

1422

---

Summary for Variable gpio_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for gpio_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

265771603

1

T21

1990

T22

3188

T23

5938

auto[1]

176342733

1

T21

2074

T22

8524

T23

1422

---

Summary for Cross cp_cross_pins_data_in

Samples crossed: cp_pin gpio_value data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cp_cross_pins_data_in

Bins

cp_pin	gpio_value	data_in	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	auto[0]	auto[0]	8068393	1			T21	60		T22	53		T23	186
bins_for_gpio_bits[0]	auto[0]	auto[1]	244728	1			T22	19		T23	1		T25	25
bins_for_gpio_bits[0]	auto[1]	auto[0]	244984	1			T22	19		T23	1		T25	26
bins_for_gpio_bits[0]	auto[1]	auto[1]	5257968	1			T21	67		T22	275		T23	42
bins_for_gpio_bits[1]	auto[0]	auto[0]	8056231	1			T21	64		T22	79		T23	176
bins_for_gpio_bits[1]	auto[0]	auto[1]	244852	1			T22	24		T23	3		T25	28
bins_for_gpio_bits[1]	auto[1]	auto[0]	245144	1			T22	24		T23	3		T25	28
bins_for_gpio_bits[1]	auto[1]	auto[1]	5269846	1			T21	63		T22	239		T23	48
bins_for_gpio_bits[2]	auto[0]	auto[0]	8058772	1			T21	65		T22	93		T23	188
bins_for_gpio_bits[2]	auto[0]	auto[1]	245117	1			T22	22		T23	1		T25	30
bins_for_gpio_bits[2]	auto[1]	auto[0]	245362	1			T22	22		T23	1		T25	31
bins_for_gpio_bits[2]	auto[1]	auto[1]	5266822	1			T21	62		T22	229		T23	40
bins_for_gpio_bits[3]	auto[0]	auto[0]	8064707	1			T21	67		T22	76		T23	180
bins_for_gpio_bits[3]	auto[0]	auto[1]	244605	1			T22	23		T23	4		T25	33
bins_for_gpio_bits[3]	auto[1]	auto[0]	244866	1			T22	23		T23	4		T25	34
bins_for_gpio_bits[3]	auto[1]	auto[1]	5261895	1			T21	60		T22	244		T23	42
bins_for_gpio_bits[4]	auto[0]	auto[0]	8064098	1			T21	57		T22	65		T23	183
bins_for_gpio_bits[4]	auto[0]	auto[1]	244947	1			T22	20		T23	1		T25	31
bins_for_gpio_bits[4]	auto[1]	auto[0]	245249	1			T22	20		T23	1		T25	32
bins_for_gpio_bits[4]	auto[1]	auto[1]	5261779	1			T21	70		T22	261		T23	45
bins_for_gpio_bits[5]	auto[0]	auto[0]	8051951	1			T21	60		T22	77		T23	191
bins_for_gpio_bits[5]	auto[0]	auto[1]	245138	1			T22	21		T25	32		T30	10
bins_for_gpio_bits[5]	auto[1]	auto[0]	245375	1			T22	20		T25	32		T30	10
bins_for_gpio_bits[5]	auto[1]	auto[1]	5273609	1			T21	67		T22	248		T23	39
bins_for_gpio_bits[6]	auto[0]	auto[0]	8055048	1			T21	56		T22	56		T23	176
bins_for_gpio_bits[6]	auto[0]	auto[1]	244414	1			T22	19		T23	4		T25	26
bins_for_gpio_bits[6]	auto[1]	auto[0]	244694	1			T22	19		T23	4		T25	26
bins_for_gpio_bits[6]	auto[1]	auto[1]	5271917	1			T21	71		T22	272		T23	46
bins_for_gpio_bits[7]	auto[0]	auto[0]	8053147	1			T21	65		T22	80		T23	181
bins_for_gpio_bits[7]	auto[0]	auto[1]	244766	1			T22	20		T23	2		T25	29
bins_for_gpio_bits[7]	auto[1]	auto[0]	244997	1			T22	20		T23	2		T25	29
bins_for_gpio_bits[7]	auto[1]	auto[1]	5273163	1			T21	62		T22	246		T23	45
bins_for_gpio_bits[8]	auto[0]	auto[0]	8055324	1			T21	65		T22	88		T23	187
bins_for_gpio_bits[8]	auto[0]	auto[1]	245162	1			T22	20		T23	2		T25	27
bins_for_gpio_bits[8]	auto[1]	auto[0]	245440	1			T22	20		T23	2		T25	28
bins_for_gpio_bits[8]	auto[1]	auto[1]	5270147	1			T21	62		T22	238		T23	39
bins_for_gpio_bits[9]	auto[0]	auto[0]	8054131	1			T21	57		T22	76		T23	164
bins_for_gpio_bits[9]	auto[0]	auto[1]	244780	1			T22	17		T23	5		T25	26
bins_for_gpio_bits[9]	auto[1]	auto[0]	245076	1			T22	16		T23	5		T25	26
bins_for_gpio_bits[9]	auto[1]	auto[1]	5272086	1			T21	70		T22	257		T23	56
bins_for_gpio_bits[10]	auto[0]	auto[0]	8063021	1			T21	52		T22	93		T23	196
bins_for_gpio_bits[10]	auto[0]	auto[1]	244701	1			T22	24		T23	1		T25	28
bins_for_gpio_bits[10]	auto[1]	auto[0]	244970	1			T22	24		T23	1		T25	28
bins_for_gpio_bits[10]	auto[1]	auto[1]	5263381	1			T21	75		T22	225		T23	32
bins_for_gpio_bits[11]	auto[0]	auto[0]	8059911	1			T21	51		T22	60		T23	192
bins_for_gpio_bits[11]	auto[0]	auto[1]	244794	1			T22	26		T23	1		T25	28
bins_for_gpio_bits[11]	auto[1]	auto[0]	245068	1			T22	26		T23	1		T25	28
bins_for_gpio_bits[11]	auto[1]	auto[1]	5266300	1			T21	76		T22	254		T23	36
bins_for_gpio_bits[12]	auto[0]	auto[0]	8046885	1			T21	70		T22	94		T23	203
bins_for_gpio_bits[12]	auto[0]	auto[1]	245193	1			T22	24		T23	1		T25	25
bins_for_gpio_bits[12]	auto[1]	auto[0]	245471	1			T22	24		T23	1		T25	25
bins_for_gpio_bits[12]	auto[1]	auto[1]	5278524	1			T21	57		T22	224		T23	25
bins_for_gpio_bits[13]	auto[0]	auto[0]	8048861	1			T21	67		T22	104		T23	162
bins_for_gpio_bits[13]	auto[0]	auto[1]	244856	1			T22	18		T23	5		T25	25
bins_for_gpio_bits[13]	auto[1]	auto[0]	245136	1			T22	18		T23	5		T25	26
bins_for_gpio_bits[13]	auto[1]	auto[1]	5277220	1			T21	60		T22	226		T23	58
bins_for_gpio_bits[14]	auto[0]	auto[0]	8052720	1			T21	59		T22	90		T23	177
bins_for_gpio_bits[14]	auto[0]	auto[1]	244308	1			T22	18		T23	3		T25	33
bins_for_gpio_bits[14]	auto[1]	auto[0]	244550	1			T22	18		T23	3		T25	33
bins_for_gpio_bits[14]	auto[1]	auto[1]	5274495	1			T21	68		T22	240		T23	47
bins_for_gpio_bits[15]	auto[0]	auto[0]	8047575	1			T21	66		T22	91		T23	194
bins_for_gpio_bits[15]	auto[0]	auto[1]	244621	1			T22	21		T23	3		T25	29
bins_for_gpio_bits[15]	auto[1]	auto[0]	244919	1			T22	21		T23	3		T25	29
bins_for_gpio_bits[15]	auto[1]	auto[1]	5278958	1			T21	61		T22	233		T23	30
bins_for_gpio_bits[16]	auto[0]	auto[0]	8057844	1			T21	62		T22	85		T23	190
bins_for_gpio_bits[16]	auto[0]	auto[1]	244850	1			T22	21		T23	2		T25	24
bins_for_gpio_bits[16]	auto[1]	auto[0]	245149	1			T22	20		T23	2		T25	24
bins_for_gpio_bits[16]	auto[1]	auto[1]	5268230	1			T21	65		T22	240		T23	36
bins_for_gpio_bits[17]	auto[0]	auto[0]	8064936	1			T21	63		T22	108		T23	192
bins_for_gpio_bits[17]	auto[0]	auto[1]	245157	1			T22	19		T23	3		T25	27
bins_for_gpio_bits[17]	auto[1]	auto[0]	245433	1			T22	19		T23	3		T25	27
bins_for_gpio_bits[17]	auto[1]	auto[1]	5260547	1			T21	64		T22	220		T23	32
bins_for_gpio_bits[18]	auto[0]	auto[0]	8068473	1			T21	60		T22	86		T23	177
bins_for_gpio_bits[18]	auto[0]	auto[1]	245188	1			T22	18		T23	2		T25	24
bins_for_gpio_bits[18]	auto[1]	auto[0]	245447	1			T22	17		T23	2		T25	24
bins_for_gpio_bits[18]	auto[1]	auto[1]	5256965	1			T21	67		T22	245		T23	49
bins_for_gpio_bits[19]	auto[0]	auto[0]	8060533	1			T21	54		T22	77		T23	184
bins_for_gpio_bits[19]	auto[0]	auto[1]	245312	1			T22	21		T23	3		T25	31
bins_for_gpio_bits[19]	auto[1]	auto[0]	245564	1			T22	21		T23	3		T25	32
bins_for_gpio_bits[19]	auto[1]	auto[1]	5264664	1			T21	73		T22	247		T23	40
bins_for_gpio_bits[20]	auto[0]	auto[0]	8070555	1			T21	59		T22	87		T23	188
bins_for_gpio_bits[20]	auto[0]	auto[1]	244849	1			T22	24		T25	31		T30	16
bins_for_gpio_bits[20]	auto[1]	auto[0]	245134	1			T22	24		T25	31		T30	16
bins_for_gpio_bits[20]	auto[1]	auto[1]	5255535	1			T21	68		T22	231		T23	42
bins_for_gpio_bits[21]	auto[0]	auto[0]	8069319	1			T21	70		T22	72		T23	185
bins_for_gpio_bits[21]	auto[0]	auto[1]	244965	1			T22	20		T23	3		T25	23
bins_for_gpio_bits[21]	auto[1]	auto[0]	245252	1			T22	20		T23	3		T25	23
bins_for_gpio_bits[21]	auto[1]	auto[1]	5256537	1			T21	57		T22	254		T23	39
bins_for_gpio_bits[22]	auto[0]	auto[0]	8072435	1			T21	62		T22	79		T23	163
bins_for_gpio_bits[22]	auto[0]	auto[1]	245205	1			T22	19		T23	6		T25	23
bins_for_gpio_bits[22]	auto[1]	auto[0]	245478	1			T22	19		T23	6		T25	23
bins_for_gpio_bits[22]	auto[1]	auto[1]	5252955	1			T21	65		T22	249		T23	55
bins_for_gpio_bits[23]	auto[0]	auto[0]	8063405	1			T21	65		T22	75		T23	178
bins_for_gpio_bits[23]	auto[0]	auto[1]	245354	1			T22	14		T23	2		T25	25
bins_for_gpio_bits[23]	auto[1]	auto[0]	245649	1			T22	14		T23	2		T25	25
bins_for_gpio_bits[23]	auto[1]	auto[1]	5261665	1			T21	62		T22	263		T23	48
bins_for_gpio_bits[24]	auto[0]	auto[0]	8060776	1			T21	67		T22	88		T23	169
bins_for_gpio_bits[24]	auto[0]	auto[1]	244531	1			T22	25		T23	4		T25	26
bins_for_gpio_bits[24]	auto[1]	auto[0]	244785	1			T22	25		T23	4		T25	26
bins_for_gpio_bits[24]	auto[1]	auto[1]	5265981	1			T21	60		T22	228		T23	53
bins_for_gpio_bits[25]	auto[0]	auto[0]	8058624	1			T21	58		T22	78		T23	190
bins_for_gpio_bits[25]	auto[0]	auto[1]	244878	1			T22	22		T23	1		T25	27
bins_for_gpio_bits[25]	auto[1]	auto[0]	245129	1			T22	22		T23	1		T25	27
bins_for_gpio_bits[25]	auto[1]	auto[1]	5267442	1			T21	69		T22	244		T23	38
bins_for_gpio_bits[26]	auto[0]	auto[0]	8063469	1			T21	64		T22	42		T23	191
bins_for_gpio_bits[26]	auto[0]	auto[1]	244794	1			T22	12		T23	1		T25	22
bins_for_gpio_bits[26]	auto[1]	auto[0]	245067	1			T22	12		T23	1		T25	22
bins_for_gpio_bits[26]	auto[1]	auto[1]	5262743	1			T21	63		T22	300		T23	37
bins_for_gpio_bits[27]	auto[0]	auto[0]	8070471	1			T21	76		T22	68		T23	183
bins_for_gpio_bits[27]	auto[0]	auto[1]	243913	1			T22	17		T23	3		T25	29
bins_for_gpio_bits[27]	auto[1]	auto[0]	244196	1			T22	17		T23	3		T25	29
bins_for_gpio_bits[27]	auto[1]	auto[1]	5257493	1			T21	51		T22	264		T23	41
bins_for_gpio_bits[28]	auto[0]	auto[0]	8052061	1			T21	70		T22	75		T23	193
bins_for_gpio_bits[28]	auto[0]	auto[1]	245266	1			T22	20		T23	4		T25	26
bins_for_gpio_bits[28]	auto[1]	auto[0]	245529	1			T22	19		T23	4		T25	26
bins_for_gpio_bits[28]	auto[1]	auto[1]	5273217	1			T21	57		T22	252		T23	29
bins_for_gpio_bits[29]	auto[0]	auto[0]	8072054	1			T21	51		T22	85		T23	167
bins_for_gpio_bits[29]	auto[0]	auto[1]	245081	1			T22	22		T23	4		T25	23
bins_for_gpio_bits[29]	auto[1]	auto[0]	245341	1			T22	22		T23	4		T25	23
bins_for_gpio_bits[29]	auto[1]	auto[1]	5253597	1			T21	76		T22	237		T23	55
bins_for_gpio_bits[30]	auto[0]	auto[0]	8058525	1			T21	61		T22	76		T23	177
bins_for_gpio_bits[30]	auto[0]	auto[1]	245551	1			T22	18		T23	5		T25	30
bins_for_gpio_bits[30]	auto[1]	auto[0]	245835	1			T22	18		T23	5		T25	30
bins_for_gpio_bits[30]	auto[1]	auto[1]	5266162	1			T21	66		T22	254		T23	43
bins_for_gpio_bits[31]	auto[0]	auto[0]	8071227	1			T21	67		T22	81		T23	194
bins_for_gpio_bits[31]	auto[0]	auto[1]	244245	1			T22	23		T23	1		T25	29
bins_for_gpio_bits[31]	auto[1]	auto[0]	244511	1			T22	23		T23	1		T25	29
bins_for_gpio_bits[31]	auto[1]	auto[1]	5256090	1			T21	60		T22	239		T23	34