Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8081297 |
1 |
|
|
T21 |
91 |
|
T22 |
204 |
|
T23 |
128 |
| auto[1] |
5948934 |
1 |
|
|
T21 |
116 |
|
T29 |
452 |
|
T31 |
16263 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13272179 |
1 |
|
|
T21 |
198 |
|
T22 |
204 |
|
T23 |
128 |
| auto[1] |
758052 |
1 |
|
|
T21 |
9 |
|
T29 |
151 |
|
T31 |
2465 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8101862 |
1 |
|
|
T21 |
72 |
|
T22 |
204 |
|
T23 |
128 |
| auto[1] |
5928369 |
1 |
|
|
T21 |
135 |
|
T29 |
817 |
|
T31 |
15704 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2576550 |
1 |
|
|
T21 |
67 |
|
T29 |
383 |
|
T31 |
6613 |
| auto[1] |
auto[0] |
auto[1] |
376819 |
1 |
|
|
T21 |
4 |
|
T29 |
89 |
|
T31 |
1192 |
| auto[1] |
auto[1] |
auto[0] |
2593767 |
1 |
|
|
T21 |
59 |
|
T29 |
283 |
|
T31 |
6626 |
| auto[1] |
auto[1] |
auto[1] |
381233 |
1 |
|
|
T21 |
5 |
|
T29 |
62 |
|
T31 |
1273 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8080865 |
1 |
|
|
T21 |
117 |
|
T22 |
204 |
|
T23 |
128 |
| auto[1] |
5949366 |
1 |
|
|
T21 |
90 |
|
T29 |
714 |
|
T31 |
16098 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13265228 |
1 |
|
|
T21 |
197 |
|
T22 |
204 |
|
T23 |
128 |
| auto[1] |
765003 |
1 |
|
|
T21 |
10 |
|
T29 |
167 |
|
T31 |
2509 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8060694 |
1 |
|
|
T21 |
99 |
|
T22 |
204 |
|
T23 |
128 |
| auto[1] |
5969537 |
1 |
|
|
T21 |
108 |
|
T29 |
868 |
|
T31 |
16283 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2609893 |
1 |
|
|
T21 |
60 |
|
T29 |
327 |
|
T31 |
6771 |
| auto[1] |
auto[0] |
auto[1] |
383974 |
1 |
|
|
T21 |
7 |
|
T29 |
82 |
|
T31 |
1252 |
| auto[1] |
auto[1] |
auto[0] |
2594641 |
1 |
|
|
T21 |
38 |
|
T29 |
374 |
|
T31 |
7003 |
| auto[1] |
auto[1] |
auto[1] |
381029 |
1 |
|
|
T21 |
3 |
|
T29 |
85 |
|
T31 |
1257 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8068854 |
1 |
|
|
T21 |
84 |
|
T22 |
204 |
|
T23 |
128 |
| auto[1] |
5961377 |
1 |
|
|
T21 |
123 |
|
T29 |
759 |
|
T31 |
16008 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13270077 |
1 |
|
|
T21 |
200 |
|
T22 |
204 |
|
T23 |
128 |
| auto[1] |
760154 |
1 |
|
|
T21 |
7 |
|
T29 |
126 |
|
T31 |
2332 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8088891 |
1 |
|
|
T21 |
130 |
|
T22 |
204 |
|
T23 |
128 |
| auto[1] |
5941340 |
1 |
|
|
T21 |
77 |
|
T29 |
626 |
|
T31 |
15318 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2593973 |
1 |
|
|
T21 |
26 |
|
T29 |
254 |
|
T31 |
6481 |
| auto[1] |
auto[0] |
auto[1] |
381804 |
1 |
|
|
T21 |
3 |
|
T29 |
67 |
|
T31 |
1107 |
| auto[1] |
auto[1] |
auto[0] |
2587213 |
1 |
|
|
T21 |
44 |
|
T29 |
246 |
|
T31 |
6505 |
| auto[1] |
auto[1] |
auto[1] |
378350 |
1 |
|
|
T21 |
4 |
|
T29 |
59 |
|
T31 |
1225 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8076079 |
1 |
|
|
T21 |
121 |
|
T22 |
204 |
|
T23 |
128 |
| auto[1] |
5954152 |
1 |
|
|
T21 |
86 |
|
T29 |
768 |
|
T31 |
14684 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13268795 |
1 |
|
|
T21 |
196 |
|
T22 |
204 |
|
T23 |
128 |
| auto[1] |
761436 |
1 |
|
|
T21 |
11 |
|
T29 |
115 |
|
T31 |
2395 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8090604 |
1 |
|
|
T21 |
116 |
|
T22 |
204 |
|
T23 |
128 |
| auto[1] |
5939627 |
1 |
|
|
T21 |
91 |
|
T29 |
604 |
|
T31 |
15620 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2600261 |
1 |
|
|
T21 |
41 |
|
T29 |
227 |
|
T31 |
7372 |
| auto[1] |
auto[0] |
auto[1] |
382155 |
1 |
|
|
T21 |
6 |
|
T29 |
55 |
|
T31 |
1385 |
| auto[1] |
auto[1] |
auto[0] |
2577930 |
1 |
|
|
T21 |
39 |
|
T29 |
262 |
|
T31 |
5853 |
| auto[1] |
auto[1] |
auto[1] |
379281 |
1 |
|
|
T21 |
5 |
|
T29 |
60 |
|
T31 |
1010 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8096319 |
1 |
|
|
T21 |
85 |
|
T22 |
204 |
|
T23 |
128 |
| auto[1] |
5933912 |
1 |
|
|
T21 |
122 |
|
T29 |
496 |
|
T31 |
17647 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13265455 |
1 |
|
|
T21 |
203 |
|
T22 |
204 |
|
T23 |
128 |
| auto[1] |
764776 |
1 |
|
|
T21 |
4 |
|
T29 |
120 |
|
T31 |
2282 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8076934 |
1 |
|
|
T21 |
129 |
|
T22 |
204 |
|
T23 |
128 |
| auto[1] |
5953297 |
1 |
|
|
T21 |
78 |
|
T29 |
590 |
|
T31 |
15069 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2610071 |
1 |
|
|
T21 |
23 |
|
T29 |
271 |
|
T31 |
5649 |
| auto[1] |
auto[0] |
auto[1] |
385777 |
1 |
|
|
T21 |
1 |
|
T29 |
76 |
|
T31 |
998 |
| auto[1] |
auto[1] |
auto[0] |
2578450 |
1 |
|
|
T21 |
51 |
|
T29 |
199 |
|
T31 |
7138 |
| auto[1] |
auto[1] |
auto[1] |
378999 |
1 |
|
|
T21 |
3 |
|
T29 |
44 |
|
T31 |
1284 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8064351 |
1 |
|
|
T21 |
114 |
|
T22 |
204 |
|
T23 |
128 |
| auto[1] |
5965880 |
1 |
|
|
T21 |
93 |
|
T29 |
778 |
|
T31 |
16192 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13269691 |
1 |
|
|
T21 |
203 |
|
T22 |
204 |
|
T23 |
128 |
| auto[1] |
760540 |
1 |
|
|
T21 |
4 |
|
T29 |
156 |
|
T31 |
2607 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8085560 |
1 |
|
|
T21 |
136 |
|
T22 |
204 |
|
T23 |
128 |
| auto[1] |
5944671 |
1 |
|
|
T21 |
71 |
|
T29 |
777 |
|
T31 |
16875 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2589801 |
1 |
|
|
T21 |
47 |
|
T29 |
256 |
|
T31 |
7051 |
| auto[1] |
auto[0] |
auto[1] |
380029 |
1 |
|
|
T21 |
2 |
|
T29 |
70 |
|
T31 |
1231 |
| auto[1] |
auto[1] |
auto[0] |
2594330 |
1 |
|
|
T21 |
20 |
|
T29 |
365 |
|
T31 |
7217 |
| auto[1] |
auto[1] |
auto[1] |
380511 |
1 |
|
|
T21 |
2 |
|
T29 |
86 |
|
T31 |
1376 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8109024 |
1 |
|
|
T21 |
104 |
|
T22 |
204 |
|
T23 |
128 |
| auto[1] |
5921207 |
1 |
|
|
T21 |
103 |
|
T29 |
602 |
|
T31 |
15202 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13264817 |
1 |
|
|
T21 |
203 |
|
T22 |
204 |
|
T23 |
128 |
| auto[1] |
765414 |
1 |
|
|
T21 |
4 |
|
T29 |
173 |
|
T31 |
2316 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8064006 |
1 |
|
|
T21 |
141 |
|
T22 |
204 |
|
T23 |
128 |
| auto[1] |
5966225 |
1 |
|
|
T21 |
66 |
|
T29 |
872 |
|
T31 |
15060 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2612392 |
1 |
|
|
T21 |
37 |
|
T29 |
360 |
|
T31 |
6824 |
| auto[1] |
auto[0] |
auto[1] |
385966 |
1 |
|
|
T21 |
3 |
|
T29 |
88 |
|
T31 |
1216 |
| auto[1] |
auto[1] |
auto[0] |
2588419 |
1 |
|
|
T21 |
25 |
|
T29 |
339 |
|
T31 |
5920 |
| auto[1] |
auto[1] |
auto[1] |
379448 |
1 |
|
|
T21 |
1 |
|
T29 |
85 |
|
T31 |
1100 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8095605 |
1 |
|
|
T21 |
134 |
|
T22 |
204 |
|
T23 |
128 |
| auto[1] |
5934626 |
1 |
|
|
T21 |
73 |
|
T29 |
765 |
|
T31 |
15719 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13271224 |
1 |
|
|
T21 |
200 |
|
T22 |
204 |
|
T23 |
128 |
| auto[1] |
759007 |
1 |
|
|
T21 |
7 |
|
T29 |
123 |
|
T31 |
2583 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8097490 |
1 |
|
|
T21 |
85 |
|
T22 |
204 |
|
T23 |
128 |
| auto[1] |
5932741 |
1 |
|
|
T21 |
122 |
|
T29 |
636 |
|
T31 |
16752 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2591245 |
1 |
|
|
T21 |
58 |
|
T29 |
209 |
|
T31 |
6969 |
| auto[1] |
auto[0] |
auto[1] |
379936 |
1 |
|
|
T21 |
4 |
|
T29 |
47 |
|
T31 |
1311 |
| auto[1] |
auto[1] |
auto[0] |
2582489 |
1 |
|
|
T21 |
57 |
|
T29 |
304 |
|
T31 |
7200 |
| auto[1] |
auto[1] |
auto[1] |
379071 |
1 |
|
|
T21 |
3 |
|
T29 |
76 |
|
T31 |
1272 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8061094 |
1 |
|
|
T21 |
118 |
|
T22 |
204 |
|
T23 |
128 |
| auto[1] |
5969137 |
1 |
|
|
T21 |
89 |
|
T29 |
612 |
|
T31 |
16758 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13261805 |
1 |
|
|
T21 |
201 |
|
T22 |
204 |
|
T23 |
128 |
| auto[1] |
768426 |
1 |
|
|
T21 |
6 |
|
T29 |
111 |
|
T31 |
2383 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8045723 |
1 |
|
|
T21 |
95 |
|
T22 |
204 |
|
T23 |
128 |
| auto[1] |
5984508 |
1 |
|
|
T21 |
112 |
|
T29 |
628 |
|
T31 |
15683 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2600586 |
1 |
|
|
T21 |
66 |
|
T29 |
265 |
|
T31 |
6716 |
| auto[1] |
auto[0] |
auto[1] |
383674 |
1 |
|
|
T21 |
5 |
|
T29 |
59 |
|
T31 |
1221 |
| auto[1] |
auto[1] |
auto[0] |
2615496 |
1 |
|
|
T21 |
40 |
|
T29 |
252 |
|
T31 |
6584 |
| auto[1] |
auto[1] |
auto[1] |
384752 |
1 |
|
|
T21 |
1 |
|
T29 |
52 |
|
T31 |
1162 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8061820 |
1 |
|
|
T21 |
101 |
|
T22 |
204 |
|
T23 |
128 |
| auto[1] |
5968411 |
1 |
|
|
T21 |
106 |
|
T29 |
752 |
|
T31 |
15903 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13267942 |
1 |
|
|
T21 |
195 |
|
T22 |
204 |
|
T23 |
128 |
| auto[1] |
762289 |
1 |
|
|
T21 |
12 |
|
T29 |
107 |
|
T31 |
2510 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8088185 |
1 |
|
|
T21 |
65 |
|
T22 |
204 |
|
T23 |
128 |
| auto[1] |
5942046 |
1 |
|
|
T21 |
142 |
|
T29 |
560 |
|
T31 |
15767 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2591646 |
1 |
|
|
T21 |
53 |
|
T29 |
192 |
|
T31 |
6303 |
| auto[1] |
auto[0] |
auto[1] |
381690 |
1 |
|
|
T21 |
2 |
|
T29 |
48 |
|
T31 |
1172 |
| auto[1] |
auto[1] |
auto[0] |
2588111 |
1 |
|
|
T21 |
77 |
|
T29 |
261 |
|
T31 |
6954 |
| auto[1] |
auto[1] |
auto[1] |
380599 |
1 |
|
|
T21 |
10 |
|
T29 |
59 |
|
T31 |
1338 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8106363 |
1 |
|
|
T21 |
55 |
|
T22 |
204 |
|
T23 |
128 |
| auto[1] |
5923868 |
1 |
|
|
T21 |
152 |
|
T29 |
509 |
|
T31 |
14975 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13265526 |
1 |
|
|
T21 |
204 |
|
T22 |
204 |
|
T23 |
128 |
| auto[1] |
764705 |
1 |
|
|
T21 |
3 |
|
T29 |
120 |
|
T31 |
2504 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8066811 |
1 |
|
|
T21 |
150 |
|
T22 |
204 |
|
T23 |
128 |
| auto[1] |
5963420 |
1 |
|
|
T21 |
57 |
|
T29 |
596 |
|
T31 |
16046 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2613915 |
1 |
|
|
T21 |
9 |
|
T29 |
303 |
|
T31 |
7084 |
| auto[1] |
auto[0] |
auto[1] |
385655 |
1 |
|
|
T29 |
73 |
|
T31 |
1324 |
|
T32 |
3125 |
| auto[1] |
auto[1] |
auto[0] |
2584800 |
1 |
|
|
T21 |
45 |
|
T29 |
173 |
|
T31 |
6458 |
| auto[1] |
auto[1] |
auto[1] |
379050 |
1 |
|
|
T21 |
3 |
|
T29 |
47 |
|
T31 |
1180 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8107385 |
1 |
|
|
T21 |
99 |
|
T22 |
204 |
|
T23 |
128 |
| auto[1] |
5922846 |
1 |
|
|
T21 |
108 |
|
T29 |
673 |
|
T31 |
15165 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13268105 |
1 |
|
|
T21 |
200 |
|
T22 |
204 |
|
T23 |
128 |
| auto[1] |
762126 |
1 |
|
|
T21 |
7 |
|
T29 |
162 |
|
T31 |
2284 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8086739 |
1 |
|
|
T21 |
108 |
|
T22 |
204 |
|
T23 |
128 |
| auto[1] |
5943492 |
1 |
|
|
T21 |
99 |
|
T29 |
843 |
|
T31 |
15001 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2615829 |
1 |
|
|
T21 |
30 |
|
T29 |
337 |
|
T31 |
6601 |
| auto[1] |
auto[0] |
auto[1] |
386316 |
1 |
|
|
T21 |
3 |
|
T29 |
76 |
|
T31 |
1239 |
| auto[1] |
auto[1] |
auto[0] |
2565537 |
1 |
|
|
T21 |
62 |
|
T29 |
344 |
|
T31 |
6116 |
| auto[1] |
auto[1] |
auto[1] |
375810 |
1 |
|
|
T21 |
4 |
|
T29 |
86 |
|
T31 |
1045 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8054941 |
1 |
|
|
T21 |
78 |
|
T22 |
204 |
|
T23 |
128 |
| auto[1] |
5975290 |
1 |
|
|
T21 |
129 |
|
T29 |
621 |
|
T31 |
15568 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13266800 |
1 |
|
|
T21 |
205 |
|
T22 |
204 |
|
T23 |
128 |
| auto[1] |
763431 |
1 |
|
|
T21 |
2 |
|
T29 |
114 |
|
T31 |
2557 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8082962 |
1 |
|
|
T21 |
143 |
|
T22 |
204 |
|
T23 |
128 |
| auto[1] |
5947269 |
1 |
|
|
T21 |
64 |
|
T29 |
631 |
|
T31 |
16347 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2590406 |
1 |
|
|
T21 |
30 |
|
T29 |
236 |
|
T31 |
7217 |
| auto[1] |
auto[0] |
auto[1] |
382180 |
1 |
|
|
T21 |
2 |
|
T29 |
50 |
|
T31 |
1329 |
| auto[1] |
auto[1] |
auto[0] |
2593432 |
1 |
|
|
T21 |
32 |
|
T29 |
281 |
|
T31 |
6573 |
| auto[1] |
auto[1] |
auto[1] |
381251 |
1 |
|
|
T29 |
64 |
|
T31 |
1228 |
|
T54 |
2 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8087076 |
1 |
|
|
T21 |
87 |
|
T22 |
204 |
|
T23 |
128 |
| auto[1] |
5943155 |
1 |
|
|
T21 |
120 |
|
T29 |
453 |
|
T31 |
16374 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13261458 |
1 |
|
|
T21 |
199 |
|
T22 |
204 |
|
T23 |
128 |
| auto[1] |
768773 |
1 |
|
|
T21 |
8 |
|
T29 |
161 |
|
T31 |
2454 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8046418 |
1 |
|
|
T21 |
108 |
|
T22 |
204 |
|
T23 |
128 |
| auto[1] |
5983813 |
1 |
|
|
T21 |
99 |
|
T29 |
799 |
|
T31 |
15842 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2618810 |
1 |
|
|
T21 |
44 |
|
T29 |
475 |
|
T31 |
6249 |
| auto[1] |
auto[0] |
auto[1] |
387133 |
1 |
|
|
T21 |
5 |
|
T29 |
121 |
|
T31 |
1176 |
| auto[1] |
auto[1] |
auto[0] |
2596230 |
1 |
|
|
T21 |
47 |
|
T29 |
163 |
|
T31 |
7139 |
| auto[1] |
auto[1] |
auto[1] |
381640 |
1 |
|
|
T21 |
3 |
|
T29 |
40 |
|
T31 |
1278 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8063104 |
1 |
|
|
T21 |
58 |
|
T22 |
204 |
|
T23 |
128 |
| auto[1] |
5967127 |
1 |
|
|
T21 |
149 |
|
T29 |
369 |
|
T31 |
16929 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13269533 |
1 |
|
|
T21 |
201 |
|
T22 |
204 |
|
T23 |
128 |
| auto[1] |
760698 |
1 |
|
|
T21 |
6 |
|
T29 |
142 |
|
T31 |
2323 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8092584 |
1 |
|
|
T21 |
127 |
|
T22 |
204 |
|
T23 |
128 |
| auto[1] |
5937647 |
1 |
|
|
T21 |
80 |
|
T29 |
711 |
|
T31 |
15378 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2589666 |
1 |
|
|
T21 |
21 |
|
T29 |
388 |
|
T31 |
6031 |
| auto[1] |
auto[0] |
auto[1] |
381219 |
1 |
|
|
T21 |
2 |
|
T29 |
94 |
|
T31 |
1053 |
| auto[1] |
auto[1] |
auto[0] |
2587283 |
1 |
|
|
T21 |
53 |
|
T29 |
181 |
|
T31 |
7024 |
| auto[1] |
auto[1] |
auto[1] |
379479 |
1 |
|
|
T21 |
4 |
|
T29 |
48 |
|
T31 |
1270 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8058676 |
1 |
|
|
T21 |
94 |
|
T22 |
204 |
|
T23 |
128 |
| auto[1] |
5971555 |
1 |
|
|
T21 |
113 |
|
T29 |
752 |
|
T31 |
15077 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13266653 |
1 |
|
|
T21 |
203 |
|
T22 |
204 |
|
T23 |
128 |
| auto[1] |
763578 |
1 |
|
|
T21 |
4 |
|
T29 |
122 |
|
T31 |
2334 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8084410 |
1 |
|
|
T21 |
147 |
|
T22 |
204 |
|
T23 |
128 |
| auto[1] |
5945821 |
1 |
|
|
T21 |
60 |
|
T29 |
589 |
|
T31 |
15103 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2588279 |
1 |
|
|
T21 |
20 |
|
T29 |
280 |
|
T31 |
6141 |
| auto[1] |
auto[0] |
auto[1] |
381523 |
1 |
|
|
T21 |
1 |
|
T29 |
75 |
|
T31 |
1135 |
| auto[1] |
auto[1] |
auto[0] |
2593964 |
1 |
|
|
T21 |
36 |
|
T29 |
187 |
|
T31 |
6628 |
| auto[1] |
auto[1] |
auto[1] |
382055 |
1 |
|
|
T21 |
3 |
|
T29 |
47 |
|
T31 |
1199 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8092037 |
1 |
|
|
T21 |
96 |
|
T22 |
204 |
|
T23 |
128 |
| auto[1] |
5938194 |
1 |
|
|
T21 |
111 |
|
T29 |
490 |
|
T31 |
15958 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13271261 |
1 |
|
|
T21 |
203 |
|
T22 |
204 |
|
T23 |
128 |
| auto[1] |
758970 |
1 |
|
|
T21 |
4 |
|
T29 |
126 |
|
T31 |
2175 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8105898 |
1 |
|
|
T21 |
142 |
|
T22 |
204 |
|
T23 |
128 |
| auto[1] |
5924333 |
1 |
|
|
T21 |
65 |
|
T29 |
644 |
|
T31 |
14221 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2596518 |
1 |
|
|
T21 |
11 |
|
T29 |
364 |
|
T31 |
6032 |
| auto[1] |
auto[0] |
auto[1] |
381525 |
1 |
|
|
T29 |
91 |
|
T31 |
1110 |
|
T32 |
2873 |
| auto[1] |
auto[1] |
auto[0] |
2568845 |
1 |
|
|
T21 |
50 |
|
T29 |
154 |
|
T31 |
6014 |
| auto[1] |
auto[1] |
auto[1] |
377445 |
1 |
|
|
T21 |
4 |
|
T29 |
35 |
|
T31 |
1065 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8070482 |
1 |
|
|
T21 |
104 |
|
T22 |
204 |
|
T23 |
128 |
| auto[1] |
5959749 |
1 |
|
|
T21 |
103 |
|
T29 |
880 |
|
T31 |
17753 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13264870 |
1 |
|
|
T21 |
196 |
|
T22 |
204 |
|
T23 |
128 |
| auto[1] |
765361 |
1 |
|
|
T21 |
11 |
|
T29 |
108 |
|
T31 |
2379 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8068775 |
1 |
|
|
T21 |
84 |
|
T22 |
204 |
|
T23 |
128 |
| auto[1] |
5961456 |
1 |
|
|
T21 |
123 |
|
T29 |
548 |
|
T31 |
15257 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2598414 |
1 |
|
|
T21 |
70 |
|
T29 |
129 |
|
T31 |
5831 |
| auto[1] |
auto[0] |
auto[1] |
383130 |
1 |
|
|
T21 |
6 |
|
T29 |
34 |
|
T31 |
1045 |
| auto[1] |
auto[1] |
auto[0] |
2597681 |
1 |
|
|
T21 |
42 |
|
T29 |
311 |
|
T31 |
7047 |
| auto[1] |
auto[1] |
auto[1] |
382231 |
1 |
|
|
T21 |
5 |
|
T29 |
74 |
|
T31 |
1334 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8072222 |
1 |
|
|
T21 |
107 |
|
T22 |
204 |
|
T23 |
128 |
| auto[1] |
5958009 |
1 |
|
|
T21 |
100 |
|
T29 |
469 |
|
T31 |
16193 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13272076 |
1 |
|
|
T21 |
200 |
|
T22 |
204 |
|
T23 |
128 |
| auto[1] |
758155 |
1 |
|
|
T21 |
7 |
|
T29 |
126 |
|
T31 |
2421 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8105745 |
1 |
|
|
T21 |
123 |
|
T22 |
204 |
|
T23 |
128 |
| auto[1] |
5924486 |
1 |
|
|
T21 |
84 |
|
T29 |
620 |
|
T31 |
15790 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2573168 |
1 |
|
|
T21 |
53 |
|
T29 |
377 |
|
T31 |
6427 |
| auto[1] |
auto[0] |
auto[1] |
376857 |
1 |
|
|
T21 |
6 |
|
T29 |
94 |
|
T31 |
1123 |
| auto[1] |
auto[1] |
auto[0] |
2593163 |
1 |
|
|
T21 |
24 |
|
T29 |
117 |
|
T31 |
6942 |
| auto[1] |
auto[1] |
auto[1] |
381298 |
1 |
|
|
T21 |
1 |
|
T29 |
32 |
|
T31 |
1298 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8065487 |
1 |
|
|
T21 |
99 |
|
T22 |
204 |
|
T23 |
128 |
| auto[1] |
5964744 |
1 |
|
|
T21 |
108 |
|
T29 |
569 |
|
T31 |
16409 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13274454 |
1 |
|
|
T21 |
197 |
|
T22 |
204 |
|
T23 |
128 |
| auto[1] |
755777 |
1 |
|
|
T21 |
10 |
|
T29 |
100 |
|
T31 |
2676 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8126277 |
1 |
|
|
T21 |
107 |
|
T22 |
204 |
|
T23 |
128 |
| auto[1] |
5903954 |
1 |
|
|
T21 |
100 |
|
T29 |
529 |
|
T31 |
17313 |