Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8069226 |
1 |
|
|
T21 |
113 |
|
T22 |
204 |
|
T23 |
128 |
| auto[1] |
5961005 |
1 |
|
|
T21 |
94 |
|
T29 |
670 |
|
T31 |
16619 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13267037 |
1 |
|
|
T21 |
202 |
|
T22 |
204 |
|
T23 |
128 |
| auto[1] |
763194 |
1 |
|
|
T21 |
5 |
|
T29 |
144 |
|
T31 |
2411 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8081397 |
1 |
|
|
T21 |
110 |
|
T22 |
204 |
|
T23 |
128 |
| auto[1] |
5948834 |
1 |
|
|
T21 |
97 |
|
T29 |
770 |
|
T31 |
15842 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2595543 |
1 |
|
|
T21 |
46 |
|
T29 |
233 |
|
T31 |
6772 |
| auto[1] |
auto[0] |
auto[1] |
382800 |
1 |
|
|
T21 |
2 |
|
T29 |
54 |
|
T31 |
1193 |
| auto[1] |
auto[1] |
auto[0] |
2590097 |
1 |
|
|
T21 |
46 |
|
T29 |
393 |
|
T31 |
6659 |
| auto[1] |
auto[1] |
auto[1] |
380394 |
1 |
|
|
T21 |
3 |
|
T29 |
90 |
|
T31 |
1218 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |