Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8086460 |
1 |
|
|
T21 |
122 |
|
T22 |
204 |
|
T23 |
128 |
| auto[1] |
5943771 |
1 |
|
|
T21 |
85 |
|
T29 |
428 |
|
T31 |
17216 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13264345 |
1 |
|
|
T21 |
198 |
|
T22 |
204 |
|
T23 |
128 |
| auto[1] |
765886 |
1 |
|
|
T21 |
9 |
|
T29 |
101 |
|
T31 |
2514 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8062329 |
1 |
|
|
T21 |
95 |
|
T22 |
204 |
|
T23 |
128 |
| auto[1] |
5967902 |
1 |
|
|
T21 |
112 |
|
T29 |
526 |
|
T31 |
15981 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2611801 |
1 |
|
|
T21 |
73 |
|
T29 |
314 |
|
T31 |
5778 |
| auto[1] |
auto[0] |
auto[1] |
384863 |
1 |
|
|
T21 |
8 |
|
T29 |
73 |
|
T31 |
1115 |
| auto[1] |
auto[1] |
auto[0] |
2590215 |
1 |
|
|
T21 |
30 |
|
T29 |
111 |
|
T31 |
7689 |
| auto[1] |
auto[1] |
auto[1] |
381023 |
1 |
|
|
T21 |
1 |
|
T29 |
28 |
|
T31 |
1399 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |