Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8068854 |
1 |
|
|
T21 |
84 |
|
T22 |
204 |
|
T23 |
128 |
| auto[1] |
5961377 |
1 |
|
|
T21 |
123 |
|
T29 |
759 |
|
T31 |
16008 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11599939 |
1 |
|
|
T21 |
153 |
|
T22 |
204 |
|
T23 |
128 |
| auto[1] |
2430292 |
1 |
|
|
T21 |
54 |
|
T29 |
280 |
|
T31 |
8681 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8074513 |
1 |
|
|
T21 |
95 |
|
T22 |
204 |
|
T23 |
128 |
| auto[1] |
5955718 |
1 |
|
|
T21 |
112 |
|
T29 |
532 |
|
T31 |
15719 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1766593 |
1 |
|
|
T21 |
30 |
|
T29 |
119 |
|
T31 |
3402 |
| auto[1] |
auto[0] |
auto[1] |
1220121 |
1 |
|
|
T21 |
22 |
|
T29 |
110 |
|
T31 |
4435 |
| auto[1] |
auto[1] |
auto[0] |
1758833 |
1 |
|
|
T21 |
28 |
|
T29 |
133 |
|
T31 |
3636 |
| auto[1] |
auto[1] |
auto[1] |
1210171 |
1 |
|
|
T21 |
32 |
|
T29 |
170 |
|
T31 |
4246 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |