Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8095605 |
1 |
|
|
T21 |
134 |
|
T22 |
204 |
|
T23 |
128 |
| auto[1] |
5934626 |
1 |
|
|
T21 |
73 |
|
T29 |
765 |
|
T31 |
15719 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11598710 |
1 |
|
|
T21 |
132 |
|
T22 |
204 |
|
T23 |
128 |
| auto[1] |
2431521 |
1 |
|
|
T21 |
75 |
|
T29 |
317 |
|
T31 |
8389 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8077177 |
1 |
|
|
T21 |
76 |
|
T22 |
204 |
|
T23 |
128 |
| auto[1] |
5953054 |
1 |
|
|
T21 |
131 |
|
T29 |
617 |
|
T31 |
15061 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1765420 |
1 |
|
|
T21 |
41 |
|
T29 |
180 |
|
T31 |
3513 |
| auto[1] |
auto[0] |
auto[1] |
1221719 |
1 |
|
|
T21 |
44 |
|
T29 |
155 |
|
T31 |
4483 |
| auto[1] |
auto[1] |
auto[0] |
1756113 |
1 |
|
|
T21 |
15 |
|
T29 |
120 |
|
T31 |
3159 |
| auto[1] |
auto[1] |
auto[1] |
1209802 |
1 |
|
|
T21 |
31 |
|
T29 |
162 |
|
T31 |
3906 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |