Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8063104 |
1 |
|
|
T21 |
58 |
|
T22 |
204 |
|
T23 |
128 |
| auto[1] |
5967127 |
1 |
|
|
T21 |
149 |
|
T29 |
369 |
|
T31 |
16929 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11598100 |
1 |
|
|
T21 |
166 |
|
T22 |
204 |
|
T23 |
128 |
| auto[1] |
2432131 |
1 |
|
|
T21 |
41 |
|
T29 |
389 |
|
T31 |
8698 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8092152 |
1 |
|
|
T21 |
86 |
|
T22 |
204 |
|
T23 |
128 |
| auto[1] |
5938079 |
1 |
|
|
T21 |
121 |
|
T29 |
777 |
|
T31 |
16051 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1749291 |
1 |
|
|
T21 |
18 |
|
T29 |
329 |
|
T31 |
3612 |
| auto[1] |
auto[0] |
auto[1] |
1217849 |
1 |
|
|
T21 |
14 |
|
T29 |
310 |
|
T31 |
4412 |
| auto[1] |
auto[1] |
auto[0] |
1756657 |
1 |
|
|
T21 |
62 |
|
T29 |
59 |
|
T31 |
3741 |
| auto[1] |
auto[1] |
auto[1] |
1214282 |
1 |
|
|
T21 |
27 |
|
T29 |
79 |
|
T31 |
4286 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |