Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8092037 |
1 |
|
|
T21 |
96 |
|
T22 |
204 |
|
T23 |
128 |
| auto[1] |
5938194 |
1 |
|
|
T21 |
111 |
|
T29 |
490 |
|
T31 |
15958 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11589532 |
1 |
|
|
T21 |
159 |
|
T22 |
204 |
|
T23 |
128 |
| auto[1] |
2440699 |
1 |
|
|
T21 |
48 |
|
T29 |
397 |
|
T31 |
8981 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8064802 |
1 |
|
|
T21 |
130 |
|
T22 |
204 |
|
T23 |
128 |
| auto[1] |
5965429 |
1 |
|
|
T21 |
77 |
|
T29 |
786 |
|
T31 |
16255 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1773672 |
1 |
|
|
T21 |
20 |
|
T29 |
259 |
|
T31 |
3819 |
| auto[1] |
auto[0] |
auto[1] |
1226960 |
1 |
|
|
T21 |
22 |
|
T29 |
271 |
|
T31 |
4430 |
| auto[1] |
auto[1] |
auto[0] |
1751058 |
1 |
|
|
T21 |
9 |
|
T29 |
130 |
|
T31 |
3455 |
| auto[1] |
auto[1] |
auto[1] |
1213739 |
1 |
|
|
T21 |
26 |
|
T29 |
126 |
|
T31 |
4551 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |