Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8070482 |
1 |
|
|
T21 |
104 |
|
T22 |
204 |
|
T23 |
128 |
| auto[1] |
5959749 |
1 |
|
|
T21 |
103 |
|
T29 |
880 |
|
T31 |
17753 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11607772 |
1 |
|
|
T21 |
155 |
|
T22 |
204 |
|
T23 |
128 |
| auto[1] |
2422459 |
1 |
|
|
T21 |
52 |
|
T29 |
304 |
|
T31 |
8988 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8098841 |
1 |
|
|
T21 |
101 |
|
T22 |
204 |
|
T23 |
128 |
| auto[1] |
5931390 |
1 |
|
|
T21 |
106 |
|
T29 |
651 |
|
T31 |
16193 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1763227 |
1 |
|
|
T21 |
34 |
|
T29 |
132 |
|
T31 |
3207 |
| auto[1] |
auto[0] |
auto[1] |
1215696 |
1 |
|
|
T21 |
14 |
|
T29 |
113 |
|
T31 |
3888 |
| auto[1] |
auto[1] |
auto[0] |
1745704 |
1 |
|
|
T21 |
20 |
|
T29 |
215 |
|
T31 |
3998 |
| auto[1] |
auto[1] |
auto[1] |
1206763 |
1 |
|
|
T21 |
38 |
|
T29 |
191 |
|
T31 |
5100 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |