Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8047204 |
1 |
|
|
T21 |
122 |
|
T22 |
204 |
|
T23 |
128 |
| auto[1] |
5983027 |
1 |
|
|
T21 |
85 |
|
T29 |
868 |
|
T31 |
16645 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13265068 |
1 |
|
|
T21 |
201 |
|
T22 |
204 |
|
T23 |
128 |
| auto[1] |
765163 |
1 |
|
|
T21 |
6 |
|
T29 |
133 |
|
T31 |
2437 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8066411 |
1 |
|
|
T21 |
107 |
|
T22 |
204 |
|
T23 |
128 |
| auto[1] |
5963820 |
1 |
|
|
T21 |
100 |
|
T29 |
669 |
|
T31 |
15750 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2588560 |
1 |
|
|
T21 |
71 |
|
T29 |
204 |
|
T31 |
6526 |
| auto[1] |
auto[0] |
auto[1] |
380301 |
1 |
|
|
T21 |
5 |
|
T29 |
56 |
|
T31 |
1204 |
| auto[1] |
auto[1] |
auto[0] |
2610097 |
1 |
|
|
T21 |
23 |
|
T29 |
332 |
|
T31 |
6787 |
| auto[1] |
auto[1] |
auto[1] |
384862 |
1 |
|
|
T21 |
1 |
|
T29 |
77 |
|
T31 |
1233 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |