Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8086046 |
1 |
|
|
T21 |
94 |
|
T22 |
204 |
|
T23 |
128 |
| auto[1] |
5944185 |
1 |
|
|
T21 |
113 |
|
T29 |
667 |
|
T31 |
16135 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13265776 |
1 |
|
|
T21 |
204 |
|
T22 |
204 |
|
T23 |
128 |
| auto[1] |
764455 |
1 |
|
|
T21 |
3 |
|
T29 |
154 |
|
T31 |
2483 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8073282 |
1 |
|
|
T21 |
166 |
|
T22 |
204 |
|
T23 |
128 |
| auto[1] |
5956949 |
1 |
|
|
T21 |
41 |
|
T29 |
798 |
|
T31 |
15772 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2620241 |
1 |
|
|
T21 |
12 |
|
T29 |
274 |
|
T31 |
6608 |
| auto[1] |
auto[0] |
auto[1] |
385920 |
1 |
|
|
T21 |
1 |
|
T29 |
68 |
|
T31 |
1259 |
| auto[1] |
auto[1] |
auto[0] |
2572253 |
1 |
|
|
T21 |
26 |
|
T29 |
370 |
|
T31 |
6681 |
| auto[1] |
auto[1] |
auto[1] |
378535 |
1 |
|
|
T21 |
2 |
|
T29 |
86 |
|
T31 |
1224 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |