Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8087100 |
1 |
|
|
T21 |
139 |
|
T22 |
204 |
|
T23 |
128 |
| auto[1] |
5943131 |
1 |
|
|
T21 |
68 |
|
T29 |
504 |
|
T31 |
14225 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13269972 |
1 |
|
|
T21 |
198 |
|
T22 |
204 |
|
T23 |
128 |
| auto[1] |
760259 |
1 |
|
|
T21 |
9 |
|
T29 |
107 |
|
T31 |
2239 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8091704 |
1 |
|
|
T21 |
61 |
|
T22 |
204 |
|
T23 |
128 |
| auto[1] |
5938527 |
1 |
|
|
T21 |
146 |
|
T29 |
550 |
|
T31 |
14901 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2602512 |
1 |
|
|
T21 |
75 |
|
T29 |
251 |
|
T31 |
6583 |
| auto[1] |
auto[0] |
auto[1] |
383062 |
1 |
|
|
T21 |
3 |
|
T29 |
59 |
|
T31 |
1145 |
| auto[1] |
auto[1] |
auto[0] |
2575756 |
1 |
|
|
T21 |
62 |
|
T29 |
192 |
|
T31 |
6079 |
| auto[1] |
auto[1] |
auto[1] |
377197 |
1 |
|
|
T21 |
6 |
|
T29 |
48 |
|
T31 |
1094 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |