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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.63 99.06 99.24 100.00 99.80 99.68 99.99


Total test records in report: 938
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T766 /workspace/coverage/cover_reg_top/2.gpio_csr_bit_bash.3416029273 Apr 18 12:29:57 PM PDT 24 Apr 18 12:30:00 PM PDT 24 114501628 ps
T767 /workspace/coverage/cover_reg_top/10.gpio_csr_mem_rw_with_rand_reset.3886737572 Apr 18 12:30:12 PM PDT 24 Apr 18 12:30:15 PM PDT 24 27186726 ps
T768 /workspace/coverage/cover_reg_top/17.gpio_same_csr_outstanding.2480364048 Apr 18 12:30:11 PM PDT 24 Apr 18 12:30:14 PM PDT 24 52628052 ps
T44 /workspace/coverage/cover_reg_top/14.gpio_tl_intg_err.1623201590 Apr 18 12:30:08 PM PDT 24 Apr 18 12:30:11 PM PDT 24 113670196 ps
T769 /workspace/coverage/cover_reg_top/1.gpio_tl_intg_err.1397454584 Apr 18 12:29:50 PM PDT 24 Apr 18 12:29:52 PM PDT 24 141718655 ps
T770 /workspace/coverage/cover_reg_top/33.gpio_intr_test.1314506523 Apr 18 12:31:46 PM PDT 24 Apr 18 12:31:48 PM PDT 24 53422903 ps
T81 /workspace/coverage/cover_reg_top/2.gpio_csr_aliasing.2291800104 Apr 18 12:30:03 PM PDT 24 Apr 18 12:30:10 PM PDT 24 120706749 ps
T771 /workspace/coverage/cover_reg_top/0.gpio_csr_hw_reset.880517720 Apr 18 12:29:44 PM PDT 24 Apr 18 12:29:45 PM PDT 24 30250853 ps
T45 /workspace/coverage/cover_reg_top/12.gpio_tl_intg_err.212247882 Apr 18 12:30:01 PM PDT 24 Apr 18 12:30:02 PM PDT 24 124404669 ps
T772 /workspace/coverage/cover_reg_top/0.gpio_tl_intg_err.2179954933 Apr 18 12:29:50 PM PDT 24 Apr 18 12:29:52 PM PDT 24 272425201 ps
T773 /workspace/coverage/cover_reg_top/41.gpio_intr_test.1453276396 Apr 18 12:30:14 PM PDT 24 Apr 18 12:30:17 PM PDT 24 17788368 ps
T774 /workspace/coverage/cover_reg_top/23.gpio_intr_test.543689132 Apr 18 12:30:06 PM PDT 24 Apr 18 12:30:08 PM PDT 24 13589475 ps
T775 /workspace/coverage/cover_reg_top/7.gpio_csr_rw.209766164 Apr 18 12:30:33 PM PDT 24 Apr 18 12:30:34 PM PDT 24 42799404 ps
T82 /workspace/coverage/cover_reg_top/4.gpio_csr_aliasing.319657093 Apr 18 12:29:54 PM PDT 24 Apr 18 12:29:56 PM PDT 24 91225093 ps
T50 /workspace/coverage/cover_reg_top/16.gpio_tl_intg_err.3454497706 Apr 18 12:30:08 PM PDT 24 Apr 18 12:30:10 PM PDT 24 80338823 ps
T776 /workspace/coverage/cover_reg_top/1.gpio_same_csr_outstanding.237649388 Apr 18 12:29:53 PM PDT 24 Apr 18 12:29:54 PM PDT 24 60708414 ps
T83 /workspace/coverage/cover_reg_top/1.gpio_csr_aliasing.2880178328 Apr 18 12:29:44 PM PDT 24 Apr 18 12:29:45 PM PDT 24 320000259 ps
T777 /workspace/coverage/cover_reg_top/15.gpio_csr_mem_rw_with_rand_reset.448110483 Apr 18 12:30:14 PM PDT 24 Apr 18 12:30:17 PM PDT 24 223376574 ps
T84 /workspace/coverage/cover_reg_top/3.gpio_csr_hw_reset.4198187601 Apr 18 12:30:12 PM PDT 24 Apr 18 12:30:15 PM PDT 24 30392988 ps
T778 /workspace/coverage/cover_reg_top/24.gpio_intr_test.1270978908 Apr 18 12:31:11 PM PDT 24 Apr 18 12:31:18 PM PDT 24 73066919 ps
T779 /workspace/coverage/cover_reg_top/14.gpio_intr_test.1036781424 Apr 18 12:30:18 PM PDT 24 Apr 18 12:30:20 PM PDT 24 41428818 ps
T780 /workspace/coverage/cover_reg_top/6.gpio_intr_test.214264552 Apr 18 12:30:10 PM PDT 24 Apr 18 12:30:13 PM PDT 24 36421000 ps
T781 /workspace/coverage/cover_reg_top/8.gpio_tl_intg_err.609672589 Apr 18 12:30:12 PM PDT 24 Apr 18 12:30:16 PM PDT 24 90194093 ps
T782 /workspace/coverage/cover_reg_top/11.gpio_intr_test.2661255674 Apr 18 12:30:06 PM PDT 24 Apr 18 12:30:07 PM PDT 24 14930239 ps
T783 /workspace/coverage/cover_reg_top/14.gpio_tl_errors.2044062759 Apr 18 12:31:11 PM PDT 24 Apr 18 12:31:19 PM PDT 24 109385466 ps
T784 /workspace/coverage/cover_reg_top/0.gpio_csr_rw.3363279000 Apr 18 12:29:57 PM PDT 24 Apr 18 12:29:59 PM PDT 24 14646385 ps
T785 /workspace/coverage/cover_reg_top/19.gpio_same_csr_outstanding.2078755121 Apr 18 12:30:47 PM PDT 24 Apr 18 12:30:54 PM PDT 24 19987651 ps
T786 /workspace/coverage/cover_reg_top/19.gpio_tl_intg_err.2138735385 Apr 18 12:30:10 PM PDT 24 Apr 18 12:30:14 PM PDT 24 353392108 ps
T787 /workspace/coverage/cover_reg_top/9.gpio_tl_intg_err.2043890808 Apr 18 12:29:57 PM PDT 24 Apr 18 12:29:59 PM PDT 24 51336134 ps
T788 /workspace/coverage/cover_reg_top/2.gpio_intr_test.3735700704 Apr 18 12:30:09 PM PDT 24 Apr 18 12:30:11 PM PDT 24 16157106 ps
T789 /workspace/coverage/cover_reg_top/20.gpio_intr_test.4002897603 Apr 18 12:31:43 PM PDT 24 Apr 18 12:31:45 PM PDT 24 11369995 ps
T790 /workspace/coverage/cover_reg_top/35.gpio_intr_test.3448446258 Apr 18 12:30:11 PM PDT 24 Apr 18 12:30:13 PM PDT 24 12276356 ps
T791 /workspace/coverage/cover_reg_top/19.gpio_csr_mem_rw_with_rand_reset.2850049600 Apr 18 12:30:17 PM PDT 24 Apr 18 12:30:19 PM PDT 24 26959112 ps
T792 /workspace/coverage/cover_reg_top/13.gpio_intr_test.2633156862 Apr 18 12:30:08 PM PDT 24 Apr 18 12:30:10 PM PDT 24 72325824 ps
T793 /workspace/coverage/cover_reg_top/11.gpio_tl_errors.513688691 Apr 18 12:30:10 PM PDT 24 Apr 18 12:30:14 PM PDT 24 245709610 ps
T794 /workspace/coverage/cover_reg_top/39.gpio_intr_test.3088903294 Apr 18 12:30:18 PM PDT 24 Apr 18 12:30:19 PM PDT 24 15208403 ps
T85 /workspace/coverage/cover_reg_top/17.gpio_csr_rw.3895071448 Apr 18 12:30:06 PM PDT 24 Apr 18 12:30:08 PM PDT 24 14133539 ps
T795 /workspace/coverage/cover_reg_top/16.gpio_same_csr_outstanding.3249049976 Apr 18 12:30:07 PM PDT 24 Apr 18 12:30:09 PM PDT 24 19881634 ps
T796 /workspace/coverage/cover_reg_top/3.gpio_csr_mem_rw_with_rand_reset.4071767075 Apr 18 12:29:55 PM PDT 24 Apr 18 12:29:57 PM PDT 24 20101234 ps
T797 /workspace/coverage/cover_reg_top/5.gpio_intr_test.2376437351 Apr 18 12:30:24 PM PDT 24 Apr 18 12:30:27 PM PDT 24 20538070 ps
T86 /workspace/coverage/cover_reg_top/8.gpio_csr_rw.820909630 Apr 18 12:30:13 PM PDT 24 Apr 18 12:30:16 PM PDT 24 24303967 ps
T88 /workspace/coverage/cover_reg_top/2.gpio_csr_rw.2151537947 Apr 18 12:30:04 PM PDT 24 Apr 18 12:30:06 PM PDT 24 20005285 ps
T87 /workspace/coverage/cover_reg_top/14.gpio_csr_rw.2557379438 Apr 18 12:30:10 PM PDT 24 Apr 18 12:30:12 PM PDT 24 101347347 ps
T798 /workspace/coverage/cover_reg_top/17.gpio_tl_errors.16459668 Apr 18 12:30:08 PM PDT 24 Apr 18 12:30:11 PM PDT 24 40761938 ps
T799 /workspace/coverage/cover_reg_top/40.gpio_intr_test.1907348010 Apr 18 12:30:11 PM PDT 24 Apr 18 12:30:14 PM PDT 24 17775893 ps
T800 /workspace/coverage/cover_reg_top/2.gpio_tl_intg_err.657189973 Apr 18 12:29:52 PM PDT 24 Apr 18 12:29:55 PM PDT 24 378076420 ps
T801 /workspace/coverage/cover_reg_top/4.gpio_intr_test.629336479 Apr 18 12:30:04 PM PDT 24 Apr 18 12:30:06 PM PDT 24 28354724 ps
T802 /workspace/coverage/cover_reg_top/10.gpio_tl_errors.4082161477 Apr 18 12:30:11 PM PDT 24 Apr 18 12:30:16 PM PDT 24 164074395 ps
T803 /workspace/coverage/cover_reg_top/0.gpio_tl_errors.3885554576 Apr 18 12:30:07 PM PDT 24 Apr 18 12:30:10 PM PDT 24 38354382 ps
T804 /workspace/coverage/cover_reg_top/3.gpio_same_csr_outstanding.1615570879 Apr 18 12:30:03 PM PDT 24 Apr 18 12:30:05 PM PDT 24 74767397 ps
T805 /workspace/coverage/cover_reg_top/5.gpio_same_csr_outstanding.2535356163 Apr 18 12:30:00 PM PDT 24 Apr 18 12:30:01 PM PDT 24 28080004 ps
T806 /workspace/coverage/cover_reg_top/47.gpio_intr_test.955944583 Apr 18 12:30:52 PM PDT 24 Apr 18 12:30:54 PM PDT 24 42456096 ps
T807 /workspace/coverage/cover_reg_top/31.gpio_intr_test.3373130099 Apr 18 12:30:10 PM PDT 24 Apr 18 12:30:12 PM PDT 24 42597981 ps
T808 /workspace/coverage/cover_reg_top/9.gpio_intr_test.2479930060 Apr 18 12:29:59 PM PDT 24 Apr 18 12:30:00 PM PDT 24 26273721 ps
T809 /workspace/coverage/cover_reg_top/9.gpio_tl_errors.3936029855 Apr 18 12:29:57 PM PDT 24 Apr 18 12:30:00 PM PDT 24 70401305 ps
T92 /workspace/coverage/cover_reg_top/11.gpio_csr_rw.603975538 Apr 18 12:30:03 PM PDT 24 Apr 18 12:30:05 PM PDT 24 46995241 ps
T810 /workspace/coverage/cover_reg_top/36.gpio_intr_test.4043206206 Apr 18 12:30:09 PM PDT 24 Apr 18 12:30:12 PM PDT 24 23143039 ps
T811 /workspace/coverage/cover_reg_top/3.gpio_tl_errors.966574054 Apr 18 12:30:28 PM PDT 24 Apr 18 12:30:31 PM PDT 24 58971177 ps
T812 /workspace/coverage/cover_reg_top/30.gpio_intr_test.2666991847 Apr 18 12:31:43 PM PDT 24 Apr 18 12:31:44 PM PDT 24 17088035 ps
T813 /workspace/coverage/cover_reg_top/7.gpio_same_csr_outstanding.995633210 Apr 18 12:30:07 PM PDT 24 Apr 18 12:30:09 PM PDT 24 24317871 ps
T814 /workspace/coverage/cover_reg_top/1.gpio_csr_rw.3888328046 Apr 18 12:29:54 PM PDT 24 Apr 18 12:29:56 PM PDT 24 76816136 ps
T815 /workspace/coverage/cover_reg_top/17.gpio_csr_mem_rw_with_rand_reset.1991548805 Apr 18 12:30:18 PM PDT 24 Apr 18 12:30:20 PM PDT 24 29074174 ps
T816 /workspace/coverage/cover_reg_top/45.gpio_intr_test.1601301567 Apr 18 12:30:19 PM PDT 24 Apr 18 12:30:20 PM PDT 24 12579273 ps
T817 /workspace/coverage/cover_reg_top/48.gpio_intr_test.3350683264 Apr 18 12:30:26 PM PDT 24 Apr 18 12:30:28 PM PDT 24 84725553 ps
T818 /workspace/coverage/cover_reg_top/0.gpio_csr_bit_bash.2603085681 Apr 18 12:29:51 PM PDT 24 Apr 18 12:29:53 PM PDT 24 264446654 ps
T819 /workspace/coverage/cover_reg_top/6.gpio_tl_errors.1198858722 Apr 18 12:30:00 PM PDT 24 Apr 18 12:30:04 PM PDT 24 46955483 ps
T820 /workspace/coverage/cover_reg_top/12.gpio_tl_errors.459186662 Apr 18 12:29:58 PM PDT 24 Apr 18 12:30:00 PM PDT 24 44591824 ps
T821 /workspace/coverage/cover_reg_top/44.gpio_intr_test.308304059 Apr 18 12:30:20 PM PDT 24 Apr 18 12:30:22 PM PDT 24 12629617 ps
T822 /workspace/coverage/cover_reg_top/19.gpio_tl_errors.988200115 Apr 18 12:30:11 PM PDT 24 Apr 18 12:30:14 PM PDT 24 83884132 ps
T823 /workspace/coverage/cover_reg_top/49.gpio_intr_test.1365733921 Apr 18 12:30:09 PM PDT 24 Apr 18 12:30:11 PM PDT 24 48169285 ps
T89 /workspace/coverage/cover_reg_top/2.gpio_csr_hw_reset.72826783 Apr 18 12:30:01 PM PDT 24 Apr 18 12:30:02 PM PDT 24 27531557 ps
T824 /workspace/coverage/cover_reg_top/4.gpio_tl_intg_err.2549059286 Apr 18 12:29:59 PM PDT 24 Apr 18 12:30:01 PM PDT 24 1026312949 ps
T825 /workspace/coverage/cover_reg_top/17.gpio_intr_test.3329672364 Apr 18 12:30:22 PM PDT 24 Apr 18 12:30:24 PM PDT 24 19138282 ps
T826 /workspace/coverage/cover_reg_top/16.gpio_intr_test.2262886740 Apr 18 12:30:12 PM PDT 24 Apr 18 12:30:15 PM PDT 24 42083912 ps
T827 /workspace/coverage/cover_reg_top/5.gpio_csr_mem_rw_with_rand_reset.1070922492 Apr 18 12:30:09 PM PDT 24 Apr 18 12:30:11 PM PDT 24 64408935 ps
T828 /workspace/coverage/cover_reg_top/9.gpio_csr_rw.1651603225 Apr 18 12:30:08 PM PDT 24 Apr 18 12:30:10 PM PDT 24 24371485 ps
T829 /workspace/coverage/cover_reg_top/0.gpio_same_csr_outstanding.3306143776 Apr 18 12:29:37 PM PDT 24 Apr 18 12:29:38 PM PDT 24 113517154 ps
T90 /workspace/coverage/cover_reg_top/5.gpio_csr_rw.447273475 Apr 18 12:29:55 PM PDT 24 Apr 18 12:29:56 PM PDT 24 44336054 ps
T830 /workspace/coverage/cover_reg_top/1.gpio_csr_mem_rw_with_rand_reset.3091915295 Apr 18 12:29:50 PM PDT 24 Apr 18 12:29:51 PM PDT 24 16157710 ps
T831 /workspace/coverage/cover_reg_top/16.gpio_csr_mem_rw_with_rand_reset.2219798046 Apr 18 12:30:10 PM PDT 24 Apr 18 12:30:13 PM PDT 24 17022262 ps
T832 /workspace/coverage/cover_reg_top/0.gpio_csr_mem_rw_with_rand_reset.2656129873 Apr 18 12:30:12 PM PDT 24 Apr 18 12:30:15 PM PDT 24 20983346 ps
T833 /workspace/coverage/cover_reg_top/7.gpio_tl_intg_err.3653955984 Apr 18 12:30:08 PM PDT 24 Apr 18 12:30:11 PM PDT 24 206244720 ps
T834 /workspace/coverage/cover_reg_top/42.gpio_intr_test.604497655 Apr 18 12:30:16 PM PDT 24 Apr 18 12:30:18 PM PDT 24 19294306 ps
T835 /workspace/coverage/cover_reg_top/18.gpio_csr_mem_rw_with_rand_reset.695781791 Apr 18 12:30:09 PM PDT 24 Apr 18 12:30:12 PM PDT 24 34540943 ps
T91 /workspace/coverage/cover_reg_top/4.gpio_csr_bit_bash.2513943845 Apr 18 12:30:04 PM PDT 24 Apr 18 12:30:08 PM PDT 24 303822204 ps
T836 /workspace/coverage/cover_reg_top/5.gpio_tl_errors.4132327274 Apr 18 12:30:17 PM PDT 24 Apr 18 12:30:20 PM PDT 24 71287188 ps
T837 /workspace/coverage/cover_reg_top/4.gpio_tl_errors.84851348 Apr 18 12:30:10 PM PDT 24 Apr 18 12:30:15 PM PDT 24 564902648 ps
T838 /workspace/coverage/cover_reg_top/6.gpio_csr_rw.997280004 Apr 18 12:30:40 PM PDT 24 Apr 18 12:30:42 PM PDT 24 12861287 ps
T839 /workspace/coverage/en_cdc_prims/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim.636090163 Apr 18 12:30:10 PM PDT 24 Apr 18 12:30:18 PM PDT 24 41517001 ps
T840 /workspace/coverage/en_cdc_prims/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1054880155 Apr 18 12:30:11 PM PDT 24 Apr 18 12:30:15 PM PDT 24 38293542 ps
T841 /workspace/coverage/en_cdc_prims/41.gpio_smoke_en_cdc_prim.3038909340 Apr 18 12:30:25 PM PDT 24 Apr 18 12:30:32 PM PDT 24 70780309 ps
T842 /workspace/coverage/en_cdc_prims/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim.699130003 Apr 18 12:30:19 PM PDT 24 Apr 18 12:30:21 PM PDT 24 633515272 ps
T843 /workspace/coverage/en_cdc_prims/15.gpio_smoke_en_cdc_prim.3279638011 Apr 18 12:30:25 PM PDT 24 Apr 18 12:30:28 PM PDT 24 103449418 ps
T844 /workspace/coverage/en_cdc_prims/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2778085425 Apr 18 12:31:02 PM PDT 24 Apr 18 12:31:07 PM PDT 24 69778974 ps
T845 /workspace/coverage/en_cdc_prims/30.gpio_smoke_en_cdc_prim.3221767945 Apr 18 12:30:27 PM PDT 24 Apr 18 12:30:30 PM PDT 24 155225203 ps
T846 /workspace/coverage/en_cdc_prims/36.gpio_smoke_en_cdc_prim.1680299198 Apr 18 12:30:23 PM PDT 24 Apr 18 12:30:25 PM PDT 24 76810702 ps
T847 /workspace/coverage/en_cdc_prims/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2967652266 Apr 18 12:30:17 PM PDT 24 Apr 18 12:30:19 PM PDT 24 173229531 ps
T848 /workspace/coverage/en_cdc_prims/40.gpio_smoke_en_cdc_prim.106146625 Apr 18 12:30:25 PM PDT 24 Apr 18 12:30:28 PM PDT 24 100882848 ps
T849 /workspace/coverage/en_cdc_prims/47.gpio_smoke_en_cdc_prim.1928667627 Apr 18 12:30:36 PM PDT 24 Apr 18 12:30:38 PM PDT 24 126187420 ps
T850 /workspace/coverage/en_cdc_prims/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1172662718 Apr 18 12:30:20 PM PDT 24 Apr 18 12:30:22 PM PDT 24 161636236 ps
T851 /workspace/coverage/en_cdc_prims/43.gpio_smoke_en_cdc_prim.1698700511 Apr 18 12:30:25 PM PDT 24 Apr 18 12:30:28 PM PDT 24 309526191 ps
T852 /workspace/coverage/en_cdc_prims/34.gpio_smoke_en_cdc_prim.2348831931 Apr 18 12:30:10 PM PDT 24 Apr 18 12:30:13 PM PDT 24 30366150 ps
T853 /workspace/coverage/en_cdc_prims/3.gpio_smoke_en_cdc_prim.1322037016 Apr 18 12:30:12 PM PDT 24 Apr 18 12:30:15 PM PDT 24 55190055 ps
T854 /workspace/coverage/en_cdc_prims/24.gpio_smoke_en_cdc_prim.1706937672 Apr 18 12:30:16 PM PDT 24 Apr 18 12:30:19 PM PDT 24 209366332 ps
T855 /workspace/coverage/en_cdc_prims/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim.630444271 Apr 18 12:30:13 PM PDT 24 Apr 18 12:30:21 PM PDT 24 306193823 ps
T856 /workspace/coverage/en_cdc_prims/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim.422210416 Apr 18 12:30:33 PM PDT 24 Apr 18 12:30:35 PM PDT 24 144704603 ps
T857 /workspace/coverage/en_cdc_prims/18.gpio_smoke_en_cdc_prim.1840558268 Apr 18 12:30:10 PM PDT 24 Apr 18 12:30:13 PM PDT 24 94641217 ps
T858 /workspace/coverage/en_cdc_prims/5.gpio_smoke_en_cdc_prim.3543162988 Apr 18 12:30:26 PM PDT 24 Apr 18 12:30:29 PM PDT 24 358890845 ps
T859 /workspace/coverage/en_cdc_prims/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim.491969862 Apr 18 12:30:08 PM PDT 24 Apr 18 12:30:11 PM PDT 24 301160749 ps
T860 /workspace/coverage/en_cdc_prims/11.gpio_smoke_en_cdc_prim.4213491718 Apr 18 12:30:25 PM PDT 24 Apr 18 12:30:28 PM PDT 24 40813655 ps
T861 /workspace/coverage/en_cdc_prims/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2306634434 Apr 18 12:30:30 PM PDT 24 Apr 18 12:30:32 PM PDT 24 166924700 ps
T862 /workspace/coverage/en_cdc_prims/1.gpio_smoke_en_cdc_prim.3383186147 Apr 18 12:30:18 PM PDT 24 Apr 18 12:30:20 PM PDT 24 38607136 ps
T863 /workspace/coverage/en_cdc_prims/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4189824398 Apr 18 12:30:04 PM PDT 24 Apr 18 12:30:06 PM PDT 24 98707917 ps
T864 /workspace/coverage/en_cdc_prims/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1853855349 Apr 18 12:30:26 PM PDT 24 Apr 18 12:30:29 PM PDT 24 688785480 ps
T865 /workspace/coverage/en_cdc_prims/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2294534095 Apr 18 12:31:34 PM PDT 24 Apr 18 12:31:36 PM PDT 24 531832762 ps
T866 /workspace/coverage/en_cdc_prims/22.gpio_smoke_en_cdc_prim.713894979 Apr 18 12:30:23 PM PDT 24 Apr 18 12:30:25 PM PDT 24 35309745 ps
T867 /workspace/coverage/en_cdc_prims/14.gpio_smoke_en_cdc_prim.1954001234 Apr 18 12:30:13 PM PDT 24 Apr 18 12:30:16 PM PDT 24 43320910 ps
T868 /workspace/coverage/en_cdc_prims/45.gpio_smoke_en_cdc_prim.3842034506 Apr 18 12:30:47 PM PDT 24 Apr 18 12:30:49 PM PDT 24 54462627 ps
T869 /workspace/coverage/en_cdc_prims/38.gpio_smoke_en_cdc_prim.3820508363 Apr 18 12:30:10 PM PDT 24 Apr 18 12:30:14 PM PDT 24 50295898 ps
T870 /workspace/coverage/en_cdc_prims/27.gpio_smoke_en_cdc_prim.4281358331 Apr 18 12:30:13 PM PDT 24 Apr 18 12:30:16 PM PDT 24 81925250 ps
T871 /workspace/coverage/en_cdc_prims/31.gpio_smoke_en_cdc_prim.3004671360 Apr 18 12:30:24 PM PDT 24 Apr 18 12:30:26 PM PDT 24 31062927 ps
T872 /workspace/coverage/en_cdc_prims/7.gpio_smoke_en_cdc_prim.2723098279 Apr 18 12:30:05 PM PDT 24 Apr 18 12:30:08 PM PDT 24 282880094 ps
T873 /workspace/coverage/en_cdc_prims/26.gpio_smoke_en_cdc_prim.1711520410 Apr 18 12:30:19 PM PDT 24 Apr 18 12:30:21 PM PDT 24 170212153 ps
T874 /workspace/coverage/en_cdc_prims/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim.939746851 Apr 18 12:30:15 PM PDT 24 Apr 18 12:30:20 PM PDT 24 63113271 ps
T875 /workspace/coverage/en_cdc_prims/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2211324059 Apr 18 12:30:13 PM PDT 24 Apr 18 12:30:17 PM PDT 24 63823953 ps
T876 /workspace/coverage/en_cdc_prims/46.gpio_smoke_en_cdc_prim.2784326516 Apr 18 12:30:44 PM PDT 24 Apr 18 12:30:46 PM PDT 24 113646805 ps
T877 /workspace/coverage/en_cdc_prims/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2864249748 Apr 18 12:30:43 PM PDT 24 Apr 18 12:30:45 PM PDT 24 33075974 ps
T878 /workspace/coverage/en_cdc_prims/8.gpio_smoke_en_cdc_prim.1743222518 Apr 18 12:30:24 PM PDT 24 Apr 18 12:30:32 PM PDT 24 125734334 ps
T879 /workspace/coverage/en_cdc_prims/23.gpio_smoke_en_cdc_prim.2821848985 Apr 18 12:30:21 PM PDT 24 Apr 18 12:30:24 PM PDT 24 79213205 ps
T880 /workspace/coverage/en_cdc_prims/6.gpio_smoke_en_cdc_prim.2847215121 Apr 18 12:30:21 PM PDT 24 Apr 18 12:30:24 PM PDT 24 102859534 ps
T881 /workspace/coverage/en_cdc_prims/4.gpio_smoke_en_cdc_prim.1470396545 Apr 18 12:30:07 PM PDT 24 Apr 18 12:30:09 PM PDT 24 25994115 ps
T882 /workspace/coverage/en_cdc_prims/29.gpio_smoke_en_cdc_prim.308536094 Apr 18 12:30:14 PM PDT 24 Apr 18 12:30:18 PM PDT 24 72317282 ps
T883 /workspace/coverage/en_cdc_prims/49.gpio_smoke_en_cdc_prim.825263098 Apr 18 12:30:20 PM PDT 24 Apr 18 12:30:22 PM PDT 24 38297178 ps
T884 /workspace/coverage/en_cdc_prims/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3565375082 Apr 18 12:31:05 PM PDT 24 Apr 18 12:31:14 PM PDT 24 489004931 ps
T885 /workspace/coverage/en_cdc_prims/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1290157220 Apr 18 12:30:25 PM PDT 24 Apr 18 12:30:27 PM PDT 24 70068697 ps
T886 /workspace/coverage/en_cdc_prims/35.gpio_smoke_en_cdc_prim.2600520901 Apr 18 12:30:25 PM PDT 24 Apr 18 12:30:28 PM PDT 24 352075213 ps
T887 /workspace/coverage/en_cdc_prims/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2894140707 Apr 18 12:30:23 PM PDT 24 Apr 18 12:30:26 PM PDT 24 194920592 ps
T888 /workspace/coverage/en_cdc_prims/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2239609356 Apr 18 12:30:10 PM PDT 24 Apr 18 12:30:13 PM PDT 24 257105905 ps
T889 /workspace/coverage/en_cdc_prims/25.gpio_smoke_en_cdc_prim.2956537469 Apr 18 12:30:13 PM PDT 24 Apr 18 12:30:17 PM PDT 24 376570335 ps
T890 /workspace/coverage/en_cdc_prims/37.gpio_smoke_en_cdc_prim.19767245 Apr 18 12:30:25 PM PDT 24 Apr 18 12:30:28 PM PDT 24 57324077 ps
T891 /workspace/coverage/en_cdc_prims/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1076154230 Apr 18 12:30:18 PM PDT 24 Apr 18 12:30:20 PM PDT 24 131074563 ps
T892 /workspace/coverage/en_cdc_prims/28.gpio_smoke_en_cdc_prim.1571492841 Apr 18 12:30:44 PM PDT 24 Apr 18 12:30:46 PM PDT 24 85336699 ps
T893 /workspace/coverage/en_cdc_prims/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2298462063 Apr 18 12:30:18 PM PDT 24 Apr 18 12:30:20 PM PDT 24 117166517 ps
T894 /workspace/coverage/en_cdc_prims/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2722762736 Apr 18 12:30:13 PM PDT 24 Apr 18 12:30:16 PM PDT 24 71961226 ps
T895 /workspace/coverage/en_cdc_prims/39.gpio_smoke_en_cdc_prim.3562910905 Apr 18 12:30:22 PM PDT 24 Apr 18 12:30:25 PM PDT 24 226668338 ps
T896 /workspace/coverage/en_cdc_prims/48.gpio_smoke_en_cdc_prim.3343502985 Apr 18 12:30:25 PM PDT 24 Apr 18 12:30:27 PM PDT 24 48642654 ps
T897 /workspace/coverage/en_cdc_prims/10.gpio_smoke_en_cdc_prim.2990416048 Apr 18 12:30:20 PM PDT 24 Apr 18 12:30:22 PM PDT 24 53090956 ps
T898 /workspace/coverage/en_cdc_prims/2.gpio_smoke_en_cdc_prim.1867878855 Apr 18 12:30:14 PM PDT 24 Apr 18 12:30:17 PM PDT 24 121039158 ps
T899 /workspace/coverage/en_cdc_prims/16.gpio_smoke_en_cdc_prim.2594369928 Apr 18 12:30:20 PM PDT 24 Apr 18 12:30:22 PM PDT 24 44822149 ps
T900 /workspace/coverage/en_cdc_prims/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1701927995 Apr 18 12:30:13 PM PDT 24 Apr 18 12:30:16 PM PDT 24 170549260 ps
T901 /workspace/coverage/en_cdc_prims/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2508556830 Apr 18 12:31:05 PM PDT 24 Apr 18 12:31:14 PM PDT 24 206690076 ps
T902 /workspace/coverage/en_cdc_prims/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3421467255 Apr 18 12:30:13 PM PDT 24 Apr 18 12:30:16 PM PDT 24 44288412 ps
T903 /workspace/coverage/en_cdc_prims/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3037487515 Apr 18 12:30:27 PM PDT 24 Apr 18 12:30:30 PM PDT 24 71348035 ps
T904 /workspace/coverage/en_cdc_prims/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1243397570 Apr 18 12:30:12 PM PDT 24 Apr 18 12:30:16 PM PDT 24 28696714 ps
T905 /workspace/coverage/en_cdc_prims/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim.348606136 Apr 18 12:30:06 PM PDT 24 Apr 18 12:30:08 PM PDT 24 321291185 ps
T906 /workspace/coverage/en_cdc_prims/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim.434623760 Apr 18 12:30:24 PM PDT 24 Apr 18 12:30:26 PM PDT 24 63396105 ps
T907 /workspace/coverage/en_cdc_prims/42.gpio_smoke_en_cdc_prim.1276317243 Apr 18 12:30:33 PM PDT 24 Apr 18 12:30:35 PM PDT 24 172064517 ps
T908 /workspace/coverage/en_cdc_prims/44.gpio_smoke_en_cdc_prim.3806136335 Apr 18 12:30:30 PM PDT 24 Apr 18 12:30:31 PM PDT 24 24080071 ps
T909 /workspace/coverage/en_cdc_prims/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4262736347 Apr 18 12:30:31 PM PDT 24 Apr 18 12:30:33 PM PDT 24 99918112 ps
T910 /workspace/coverage/en_cdc_prims/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4239023035 Apr 18 12:30:28 PM PDT 24 Apr 18 12:30:30 PM PDT 24 239401994 ps
T911 /workspace/coverage/en_cdc_prims/0.gpio_smoke_en_cdc_prim.908812197 Apr 18 12:30:09 PM PDT 24 Apr 18 12:30:12 PM PDT 24 57915383 ps
T912 /workspace/coverage/en_cdc_prims/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1443535236 Apr 18 12:30:26 PM PDT 24 Apr 18 12:30:29 PM PDT 24 110743149 ps
T913 /workspace/coverage/en_cdc_prims/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1217004313 Apr 18 12:30:27 PM PDT 24 Apr 18 12:30:30 PM PDT 24 150114263 ps
T914 /workspace/coverage/en_cdc_prims/32.gpio_smoke_en_cdc_prim.1742431058 Apr 18 12:30:26 PM PDT 24 Apr 18 12:30:29 PM PDT 24 73173413 ps
T915 /workspace/coverage/en_cdc_prims/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4224537133 Apr 18 12:30:08 PM PDT 24 Apr 18 12:30:11 PM PDT 24 67225918 ps
T916 /workspace/coverage/en_cdc_prims/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim.985641074 Apr 18 12:30:15 PM PDT 24 Apr 18 12:30:21 PM PDT 24 86954973 ps
T917 /workspace/coverage/en_cdc_prims/20.gpio_smoke_en_cdc_prim.2327123202 Apr 18 12:30:23 PM PDT 24 Apr 18 12:30:26 PM PDT 24 365167218 ps
T918 /workspace/coverage/en_cdc_prims/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2406121129 Apr 18 12:30:15 PM PDT 24 Apr 18 12:30:19 PM PDT 24 63194175 ps
T919 /workspace/coverage/en_cdc_prims/19.gpio_smoke_en_cdc_prim.4191095531 Apr 18 12:30:29 PM PDT 24 Apr 18 12:30:31 PM PDT 24 195327935 ps
T920 /workspace/coverage/en_cdc_prims/33.gpio_smoke_en_cdc_prim.1436414229 Apr 18 12:30:23 PM PDT 24 Apr 18 12:30:30 PM PDT 24 109002392 ps
T921 /workspace/coverage/en_cdc_prims/12.gpio_smoke_en_cdc_prim.1371026042 Apr 18 12:30:07 PM PDT 24 Apr 18 12:30:09 PM PDT 24 214433865 ps
T922 /workspace/coverage/en_cdc_prims/9.gpio_smoke_en_cdc_prim.1793489795 Apr 18 12:30:02 PM PDT 24 Apr 18 12:30:04 PM PDT 24 55715364 ps
T923 /workspace/coverage/en_cdc_prims/17.gpio_smoke_en_cdc_prim.2614434368 Apr 18 12:30:22 PM PDT 24 Apr 18 12:30:25 PM PDT 24 1054822297 ps
T924 /workspace/coverage/en_cdc_prims/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3942277310 Apr 18 12:30:13 PM PDT 24 Apr 18 12:30:16 PM PDT 24 42600252 ps
T925 /workspace/coverage/en_cdc_prims/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim.119509886 Apr 18 12:30:23 PM PDT 24 Apr 18 12:30:25 PM PDT 24 191587922 ps
T926 /workspace/coverage/en_cdc_prims/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3476085069 Apr 18 12:30:20 PM PDT 24 Apr 18 12:30:23 PM PDT 24 103043376 ps
T927 /workspace/coverage/en_cdc_prims/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1806528289 Apr 18 12:30:22 PM PDT 24 Apr 18 12:30:25 PM PDT 24 50560256 ps
T928 /workspace/coverage/en_cdc_prims/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1322567528 Apr 18 12:30:25 PM PDT 24 Apr 18 12:30:28 PM PDT 24 136878813 ps
T929 /workspace/coverage/en_cdc_prims/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim.714053536 Apr 18 12:30:27 PM PDT 24 Apr 18 12:30:30 PM PDT 24 337536826 ps
T930 /workspace/coverage/en_cdc_prims/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3668210910 Apr 18 12:30:29 PM PDT 24 Apr 18 12:30:31 PM PDT 24 354355786 ps
T931 /workspace/coverage/en_cdc_prims/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim.144556110 Apr 18 12:30:19 PM PDT 24 Apr 18 12:30:21 PM PDT 24 95567315 ps
T932 /workspace/coverage/en_cdc_prims/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim.561588242 Apr 18 12:30:27 PM PDT 24 Apr 18 12:30:30 PM PDT 24 171488750 ps
T933 /workspace/coverage/en_cdc_prims/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3055374267 Apr 18 12:30:20 PM PDT 24 Apr 18 12:30:23 PM PDT 24 209246373 ps
T934 /workspace/coverage/en_cdc_prims/21.gpio_smoke_en_cdc_prim.4108011709 Apr 18 12:30:20 PM PDT 24 Apr 18 12:30:23 PM PDT 24 790590241 ps
T935 /workspace/coverage/en_cdc_prims/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1886097542 Apr 18 12:30:24 PM PDT 24 Apr 18 12:30:31 PM PDT 24 151702120 ps
T936 /workspace/coverage/en_cdc_prims/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim.866046643 Apr 18 12:30:16 PM PDT 24 Apr 18 12:30:18 PM PDT 24 623043011 ps
T937 /workspace/coverage/en_cdc_prims/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2442349669 Apr 18 12:31:22 PM PDT 24 Apr 18 12:31:25 PM PDT 24 122611051 ps
T938 /workspace/coverage/en_cdc_prims/13.gpio_smoke_en_cdc_prim.661232612 Apr 18 12:31:05 PM PDT 24 Apr 18 12:31:14 PM PDT 24 143863406 ps

Test location /workspace/coverage/default/1.gpio_intr_with_filter_rand_intr_event.1723356853
Short name T28
Test name
Test status
Simulation time 107001715 ps
CPU time 3.36 seconds
Started Apr 18 12:30:54 PM PDT 24
Finished Apr 18 12:30:59 PM PDT 24
Peak memory 197980 kb
Host smart-3be7ba50-fa5a-4939-b111-b39dece15e66
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1723356853 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 1.gpio_intr_with_filter_rand_intr_event.1723356853
Directory /workspace/1.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/36.gpio_stress_all_with_rand_reset.2412849238
Short name T35
Test name
Test status
Simulation time 20212706056 ps
CPU time 497.64 seconds
Started Apr 18 12:31:47 PM PDT 24
Finished Apr 18 12:40:06 PM PDT 24
Peak memory 198104 kb
Host smart-53de1806-4a34-472f-9f19-c2714cdd525a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2412849238 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_stress_all_with_rand_reset.2412849238
Directory /workspace/36.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.gpio_sec_cm.1061316547
Short name T24
Test name
Test status
Simulation time 88354491 ps
CPU time 0.96 seconds
Started Apr 18 12:30:43 PM PDT 24
Finished Apr 18 12:30:45 PM PDT 24
Peak memory 214676 kb
Host smart-2486b88f-12a3-4670-9a62-04261530d475
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1061316547 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_sec_cm.1061316547
Directory /workspace/3.gpio_sec_cm/latest

Test location /workspace/coverage/default/31.gpio_random_long_reg_writes_reg_reads.151049378
Short name T3
Test name
Test status
Simulation time 339466382 ps
CPU time 1.31 seconds
Started Apr 18 12:31:25 PM PDT 24
Finished Apr 18 12:31:28 PM PDT 24
Peak memory 198120 kb
Host smart-a05c12ee-f773-4d89-85d9-dbd5fc140d99
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=151049378 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_ran
dom_long_reg_writes_reg_reads.151049378
Directory /workspace/31.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_csr_rw.3873242440
Short name T76
Test name
Test status
Simulation time 48406063 ps
CPU time 0.63 seconds
Started Apr 18 12:30:17 PM PDT 24
Finished Apr 18 12:30:19 PM PDT 24
Peak memory 195096 kb
Host smart-19cb509d-4674-4055-82e0-f6e0864d8dbc
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3873242440 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpi
o_csr_rw.3873242440
Directory /workspace/19.gpio_csr_rw/latest

Test location /workspace/coverage/default/10.gpio_dout_din_regs_random_rw.3254176049
Short name T23
Test name
Test status
Simulation time 83541095 ps
CPU time 0.88 seconds
Started Apr 18 12:30:50 PM PDT 24
Finished Apr 18 12:30:52 PM PDT 24
Peak memory 197172 kb
Host smart-815fe13c-82f1-441c-88d4-62da6166f6f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3254176049 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_dout_din_regs_random_rw.3254176049
Directory /workspace/10.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_tl_intg_err.1623201590
Short name T44
Test name
Test status
Simulation time 113670196 ps
CPU time 1.48 seconds
Started Apr 18 12:30:08 PM PDT 24
Finished Apr 18 12:30:11 PM PDT 24
Peak memory 198008 kb
Host smart-a6eb73cb-526f-4509-9df9-3cf959043c6d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1623201590 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 14.gpio_tl_intg_err.1623201590
Directory /workspace/14.gpio_tl_intg_err/latest

Test location /workspace/coverage/default/14.gpio_alert_test.1752668715
Short name T152
Test name
Test status
Simulation time 13089662 ps
CPU time 0.58 seconds
Started Apr 18 12:31:19 PM PDT 24
Finished Apr 18 12:31:22 PM PDT 24
Peak memory 195540 kb
Host smart-de2f107c-4e40-4b98-958c-93c340c9421f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1752668715 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_alert_test.1752668715
Directory /workspace/14.gpio_alert_test/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_same_csr_outstanding.3709065921
Short name T94
Test name
Test status
Simulation time 28712738 ps
CPU time 0.64 seconds
Started Apr 18 12:30:06 PM PDT 24
Finished Apr 18 12:30:08 PM PDT 24
Peak memory 194740 kb
Host smart-c93acf49-c848-4fe1-864f-e08a9d81ae57
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3709065921 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 11.gpio_same_csr_outstanding.3709065921
Directory /workspace/11.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_aliasing.2880178328
Short name T83
Test name
Test status
Simulation time 320000259 ps
CPU time 0.75 seconds
Started Apr 18 12:29:44 PM PDT 24
Finished Apr 18 12:29:45 PM PDT 24
Peak memory 195772 kb
Host smart-9183c1d2-9d1f-4e2f-93f3-b33105e00621
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2880178328 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
1.gpio_csr_aliasing.2880178328
Directory /workspace/1.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_tl_intg_err.1397454584
Short name T769
Test name
Test status
Simulation time 141718655 ps
CPU time 1.1 seconds
Started Apr 18 12:29:50 PM PDT 24
Finished Apr 18 12:29:52 PM PDT 24
Peak memory 198096 kb
Host smart-0133850e-4fc6-4794-aac5-3cb3a8099854
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1397454584 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 1.gpio_tl_intg_err.1397454584
Directory /workspace/1.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_aliasing.2527614660
Short name T764
Test name
Test status
Simulation time 72468630 ps
CPU time 0.88 seconds
Started Apr 18 12:30:02 PM PDT 24
Finished Apr 18 12:30:03 PM PDT 24
Peak memory 195544 kb
Host smart-d06b278a-b973-4915-9c93-9bc5f3c44ad4
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2527614660 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
0.gpio_csr_aliasing.2527614660
Directory /workspace/0.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_bit_bash.2603085681
Short name T818
Test name
Test status
Simulation time 264446654 ps
CPU time 1.45 seconds
Started Apr 18 12:29:51 PM PDT 24
Finished Apr 18 12:29:53 PM PDT 24
Peak memory 196444 kb
Host smart-5a3c5739-0653-482f-996c-28552f529301
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2603085681 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_bit_bash.2603085681
Directory /workspace/0.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_hw_reset.880517720
Short name T771
Test name
Test status
Simulation time 30250853 ps
CPU time 0.6 seconds
Started Apr 18 12:29:44 PM PDT 24
Finished Apr 18 12:29:45 PM PDT 24
Peak memory 194380 kb
Host smart-e3fa203d-678e-4888-9728-1063f4f93641
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=880517720 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_hw_reset.880517720
Directory /workspace/0.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_mem_rw_with_rand_reset.2656129873
Short name T832
Test name
Test status
Simulation time 20983346 ps
CPU time 0.63 seconds
Started Apr 18 12:30:12 PM PDT 24
Finished Apr 18 12:30:15 PM PDT 24
Peak memory 196416 kb
Host smart-f9395ed0-fb91-4cd0-9542-26c2313f744d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2656129873 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_mem_rw_with_rand_reset.2656129873
Directory /workspace/0.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_rw.3363279000
Short name T784
Test name
Test status
Simulation time 14646385 ps
CPU time 0.61 seconds
Started Apr 18 12:29:57 PM PDT 24
Finished Apr 18 12:29:59 PM PDT 24
Peak memory 195020 kb
Host smart-25e4889d-fec1-4fcd-81b0-a8a35922570c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3363279000 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio
_csr_rw.3363279000
Directory /workspace/0.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_intr_test.213726314
Short name T755
Test name
Test status
Simulation time 30676586 ps
CPU time 0.59 seconds
Started Apr 18 12:30:06 PM PDT 24
Finished Apr 18 12:30:08 PM PDT 24
Peak memory 193756 kb
Host smart-67e1d449-de7a-49b6-96df-25b07908c409
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=213726314 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_intr_test.213726314
Directory /workspace/0.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_same_csr_outstanding.3306143776
Short name T829
Test name
Test status
Simulation time 113517154 ps
CPU time 0.65 seconds
Started Apr 18 12:29:37 PM PDT 24
Finished Apr 18 12:29:38 PM PDT 24
Peak memory 195676 kb
Host smart-b9d62c1e-8a72-4682-8e26-662e707a0a0a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3306143776 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 0.gpio_same_csr_outstanding.3306143776
Directory /workspace/0.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_tl_errors.3885554576
Short name T803
Test name
Test status
Simulation time 38354382 ps
CPU time 1.96 seconds
Started Apr 18 12:30:07 PM PDT 24
Finished Apr 18 12:30:10 PM PDT 24
Peak memory 198156 kb
Host smart-eb39e69b-dab9-4cc9-a4e2-8e2d9c183660
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3885554576 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_tl_errors.3885554576
Directory /workspace/0.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_tl_intg_err.2179954933
Short name T772
Test name
Test status
Simulation time 272425201 ps
CPU time 1.15 seconds
Started Apr 18 12:29:50 PM PDT 24
Finished Apr 18 12:29:52 PM PDT 24
Peak memory 197968 kb
Host smart-0b8aa931-efa5-4128-95d1-4f65bf783929
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2179954933 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 0.gpio_tl_intg_err.2179954933
Directory /workspace/0.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_bit_bash.1626374849
Short name T111
Test name
Test status
Simulation time 35374108 ps
CPU time 1.38 seconds
Started Apr 18 12:30:05 PM PDT 24
Finished Apr 18 12:30:08 PM PDT 24
Peak memory 196636 kb
Host smart-f43d3eb3-27c7-41e7-9140-e7f77cc2c8f8
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1626374849 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_bit_bash.1626374849
Directory /workspace/1.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_hw_reset.3290799519
Short name T739
Test name
Test status
Simulation time 19645100 ps
CPU time 0.63 seconds
Started Apr 18 12:29:55 PM PDT 24
Finished Apr 18 12:29:57 PM PDT 24
Peak memory 194532 kb
Host smart-82a86498-ffcf-40ad-af9a-f789e55f2e73
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3290799519 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_hw_reset.3290799519
Directory /workspace/1.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_mem_rw_with_rand_reset.3091915295
Short name T830
Test name
Test status
Simulation time 16157710 ps
CPU time 0.64 seconds
Started Apr 18 12:29:50 PM PDT 24
Finished Apr 18 12:29:51 PM PDT 24
Peak memory 196788 kb
Host smart-87ee734c-77f2-4c82-99c0-dd16f55ecbd8
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3091915295 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_mem_rw_with_rand_reset.3091915295
Directory /workspace/1.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_rw.3888328046
Short name T814
Test name
Test status
Simulation time 76816136 ps
CPU time 0.63 seconds
Started Apr 18 12:29:54 PM PDT 24
Finished Apr 18 12:29:56 PM PDT 24
Peak memory 195456 kb
Host smart-9625aee3-a48f-4520-9233-06a06405de87
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3888328046 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio
_csr_rw.3888328046
Directory /workspace/1.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_intr_test.118623875
Short name T761
Test name
Test status
Simulation time 13447900 ps
CPU time 0.57 seconds
Started Apr 18 12:29:55 PM PDT 24
Finished Apr 18 12:29:57 PM PDT 24
Peak memory 193656 kb
Host smart-2a026b31-2ecf-4c87-a968-147b0c979217
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=118623875 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_intr_test.118623875
Directory /workspace/1.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_same_csr_outstanding.237649388
Short name T776
Test name
Test status
Simulation time 60708414 ps
CPU time 0.8 seconds
Started Apr 18 12:29:53 PM PDT 24
Finished Apr 18 12:29:54 PM PDT 24
Peak memory 196328 kb
Host smart-eb8c7c02-9fda-4697-9905-eb078d0f15ac
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=237649388 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 1.gpio_same_csr_outstanding.237649388
Directory /workspace/1.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_tl_errors.2636253719
Short name T729
Test name
Test status
Simulation time 129196941 ps
CPU time 1.64 seconds
Started Apr 18 12:29:45 PM PDT 24
Finished Apr 18 12:29:47 PM PDT 24
Peak memory 197984 kb
Host smart-2760c130-5e6b-48e0-ad2c-714a12032025
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2636253719 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_tl_errors.2636253719
Directory /workspace/1.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_csr_mem_rw_with_rand_reset.3886737572
Short name T767
Test name
Test status
Simulation time 27186726 ps
CPU time 0.84 seconds
Started Apr 18 12:30:12 PM PDT 24
Finished Apr 18 12:30:15 PM PDT 24
Peak memory 197848 kb
Host smart-e449fd22-4508-42f0-83e4-501315ef0572
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3886737572 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_csr_mem_rw_with_rand_reset.3886737572
Directory /workspace/10.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_csr_rw.3308692889
Short name T75
Test name
Test status
Simulation time 14458666 ps
CPU time 0.63 seconds
Started Apr 18 12:30:04 PM PDT 24
Finished Apr 18 12:30:06 PM PDT 24
Peak memory 194824 kb
Host smart-fca99c19-a9a7-4ed5-82a8-b0109617d4b1
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3308692889 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpi
o_csr_rw.3308692889
Directory /workspace/10.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_intr_test.3794279110
Short name T745
Test name
Test status
Simulation time 38688046 ps
CPU time 0.56 seconds
Started Apr 18 12:30:07 PM PDT 24
Finished Apr 18 12:30:09 PM PDT 24
Peak memory 194292 kb
Host smart-e4a284ca-35ec-49ad-ac74-e762f8bb7276
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3794279110 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_intr_test.3794279110
Directory /workspace/10.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_same_csr_outstanding.2134207449
Short name T99
Test name
Test status
Simulation time 18962341 ps
CPU time 0.64 seconds
Started Apr 18 12:30:05 PM PDT 24
Finished Apr 18 12:30:07 PM PDT 24
Peak memory 195008 kb
Host smart-09a5e526-1002-4900-9a75-617d5a03de14
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2134207449 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 10.gpio_same_csr_outstanding.2134207449
Directory /workspace/10.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_tl_errors.4082161477
Short name T802
Test name
Test status
Simulation time 164074395 ps
CPU time 1.99 seconds
Started Apr 18 12:30:11 PM PDT 24
Finished Apr 18 12:30:16 PM PDT 24
Peak memory 198052 kb
Host smart-ad53d8e5-31d3-4032-80b6-e464f9511fe6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4082161477 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_tl_errors.4082161477
Directory /workspace/10.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_tl_intg_err.1839858576
Short name T49
Test name
Test status
Simulation time 88015784 ps
CPU time 1.06 seconds
Started Apr 18 12:30:12 PM PDT 24
Finished Apr 18 12:30:16 PM PDT 24
Peak memory 198008 kb
Host smart-37cbe3fe-edf1-4c0a-aac6-2e69e5777873
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1839858576 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 10.gpio_tl_intg_err.1839858576
Directory /workspace/10.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_csr_mem_rw_with_rand_reset.1628968376
Short name T732
Test name
Test status
Simulation time 54360382 ps
CPU time 0.8 seconds
Started Apr 18 12:30:10 PM PDT 24
Finished Apr 18 12:30:13 PM PDT 24
Peak memory 197936 kb
Host smart-e07acb47-4de3-44a1-930d-8709262d8777
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1628968376 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_csr_mem_rw_with_rand_reset.1628968376
Directory /workspace/11.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_csr_rw.603975538
Short name T92
Test name
Test status
Simulation time 46995241 ps
CPU time 0.59 seconds
Started Apr 18 12:30:03 PM PDT 24
Finished Apr 18 12:30:05 PM PDT 24
Peak memory 194732 kb
Host smart-2ffd7c45-77f3-4f6f-80e5-9b348321095c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=603975538 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio
_csr_rw.603975538
Directory /workspace/11.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_intr_test.2661255674
Short name T782
Test name
Test status
Simulation time 14930239 ps
CPU time 0.58 seconds
Started Apr 18 12:30:06 PM PDT 24
Finished Apr 18 12:30:07 PM PDT 24
Peak memory 193672 kb
Host smart-87c101e2-114d-4f5b-8205-fcda53ea88a5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2661255674 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_intr_test.2661255674
Directory /workspace/11.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_tl_errors.513688691
Short name T793
Test name
Test status
Simulation time 245709610 ps
CPU time 1.57 seconds
Started Apr 18 12:30:10 PM PDT 24
Finished Apr 18 12:30:14 PM PDT 24
Peak memory 198052 kb
Host smart-bbb2d871-0da7-436a-a2c7-db6b0f0f8d8f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=513688691 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_tl_errors.513688691
Directory /workspace/11.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_tl_intg_err.4094636392
Short name T113
Test name
Test status
Simulation time 899461531 ps
CPU time 0.9 seconds
Started Apr 18 12:30:02 PM PDT 24
Finished Apr 18 12:30:04 PM PDT 24
Peak memory 197056 kb
Host smart-3483b7b6-6cdd-404b-8d8c-c185fb3b8007
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4094636392 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 11.gpio_tl_intg_err.4094636392
Directory /workspace/11.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_csr_mem_rw_with_rand_reset.1674695088
Short name T726
Test name
Test status
Simulation time 103173421 ps
CPU time 0.77 seconds
Started Apr 18 12:30:10 PM PDT 24
Finished Apr 18 12:30:12 PM PDT 24
Peak memory 197816 kb
Host smart-eb80ae1c-3cde-41dd-8414-4d6df9b76398
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1674695088 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_csr_mem_rw_with_rand_reset.1674695088
Directory /workspace/12.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_csr_rw.789980750
Short name T724
Test name
Test status
Simulation time 11996277 ps
CPU time 0.59 seconds
Started Apr 18 12:30:01 PM PDT 24
Finished Apr 18 12:30:02 PM PDT 24
Peak memory 193240 kb
Host smart-99bdc986-39ac-4650-ba24-9d5729b25694
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=789980750 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio
_csr_rw.789980750
Directory /workspace/12.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_intr_test.1203846632
Short name T754
Test name
Test status
Simulation time 23133254 ps
CPU time 0.59 seconds
Started Apr 18 12:30:07 PM PDT 24
Finished Apr 18 12:30:09 PM PDT 24
Peak memory 194472 kb
Host smart-41f2aab5-200a-435b-a7c2-c6a96f4907a4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1203846632 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_intr_test.1203846632
Directory /workspace/12.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_same_csr_outstanding.1566777135
Short name T93
Test name
Test status
Simulation time 215504031 ps
CPU time 0.89 seconds
Started Apr 18 12:30:04 PM PDT 24
Finished Apr 18 12:30:07 PM PDT 24
Peak memory 196196 kb
Host smart-4ff97e93-b109-4a26-a4f8-355724dca720
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1566777135 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 12.gpio_same_csr_outstanding.1566777135
Directory /workspace/12.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_tl_errors.459186662
Short name T820
Test name
Test status
Simulation time 44591824 ps
CPU time 1.27 seconds
Started Apr 18 12:29:58 PM PDT 24
Finished Apr 18 12:30:00 PM PDT 24
Peak memory 198024 kb
Host smart-0e52f924-8aea-4a37-9f16-8e76cc4955a8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=459186662 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_tl_errors.459186662
Directory /workspace/12.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_tl_intg_err.212247882
Short name T45
Test name
Test status
Simulation time 124404669 ps
CPU time 0.87 seconds
Started Apr 18 12:30:01 PM PDT 24
Finished Apr 18 12:30:02 PM PDT 24
Peak memory 197900 kb
Host smart-dc2e8d68-5169-4d7f-b347-2eea60fd5c38
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=212247882 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 12.gpio_tl_intg_err.212247882
Directory /workspace/12.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_csr_mem_rw_with_rand_reset.86260504
Short name T749
Test name
Test status
Simulation time 92181929 ps
CPU time 0.73 seconds
Started Apr 18 12:30:08 PM PDT 24
Finished Apr 18 12:30:10 PM PDT 24
Peak memory 197720 kb
Host smart-e75cc562-82fc-4229-8f21-92a8eb5a556a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86260504 -assert
nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_csr_mem_rw_with_rand_reset.86260504
Directory /workspace/13.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_csr_rw.2415436468
Short name T79
Test name
Test status
Simulation time 46486098 ps
CPU time 0.62 seconds
Started Apr 18 12:30:04 PM PDT 24
Finished Apr 18 12:30:06 PM PDT 24
Peak memory 194548 kb
Host smart-4c7a4814-bfff-4ad8-8fcf-1f529f362651
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2415436468 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpi
o_csr_rw.2415436468
Directory /workspace/13.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_intr_test.2633156862
Short name T792
Test name
Test status
Simulation time 72325824 ps
CPU time 0.58 seconds
Started Apr 18 12:30:08 PM PDT 24
Finished Apr 18 12:30:10 PM PDT 24
Peak memory 193752 kb
Host smart-e9d44c68-b86d-478e-a220-260aba0f5538
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2633156862 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_intr_test.2633156862
Directory /workspace/13.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_same_csr_outstanding.823093237
Short name T101
Test name
Test status
Simulation time 156591940 ps
CPU time 0.84 seconds
Started Apr 18 12:30:06 PM PDT 24
Finished Apr 18 12:30:09 PM PDT 24
Peak memory 196484 kb
Host smart-51ec5b96-ee38-4742-91dc-a87d1efb4b7f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=823093237 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 13.gpio_same_csr_outstanding.823093237
Directory /workspace/13.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_tl_errors.2367209053
Short name T756
Test name
Test status
Simulation time 250819777 ps
CPU time 2.34 seconds
Started Apr 18 12:30:10 PM PDT 24
Finished Apr 18 12:30:15 PM PDT 24
Peak memory 198016 kb
Host smart-1bbb8871-d937-47ae-9390-5fabf841ebe8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2367209053 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_tl_errors.2367209053
Directory /workspace/13.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_tl_intg_err.85151601
Short name T47
Test name
Test status
Simulation time 48470501 ps
CPU time 0.88 seconds
Started Apr 18 12:30:03 PM PDT 24
Finished Apr 18 12:30:05 PM PDT 24
Peak memory 197816 kb
Host smart-9c87a5a9-5b74-4097-b4b6-6e569828cb4f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85151601 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UV
M_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
13.gpio_tl_intg_err.85151601
Directory /workspace/13.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_csr_mem_rw_with_rand_reset.199481295
Short name T760
Test name
Test status
Simulation time 35922738 ps
CPU time 0.9 seconds
Started Apr 18 12:30:14 PM PDT 24
Finished Apr 18 12:30:17 PM PDT 24
Peak memory 197920 kb
Host smart-9c53b645-0951-4956-9f41-57bd308bed6e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=199481295 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_csr_mem_rw_with_rand_reset.199481295
Directory /workspace/14.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_csr_rw.2557379438
Short name T87
Test name
Test status
Simulation time 101347347 ps
CPU time 0.63 seconds
Started Apr 18 12:30:10 PM PDT 24
Finished Apr 18 12:30:12 PM PDT 24
Peak memory 194836 kb
Host smart-ad2c4ad0-b160-42c3-b0ea-0584b1666809
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2557379438 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpi
o_csr_rw.2557379438
Directory /workspace/14.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_intr_test.1036781424
Short name T779
Test name
Test status
Simulation time 41428818 ps
CPU time 0.62 seconds
Started Apr 18 12:30:18 PM PDT 24
Finished Apr 18 12:30:20 PM PDT 24
Peak memory 193928 kb
Host smart-ead98986-142a-46a9-bbf3-3db516ae7be3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1036781424 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_intr_test.1036781424
Directory /workspace/14.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_same_csr_outstanding.1938819767
Short name T96
Test name
Test status
Simulation time 24932875 ps
CPU time 0.71 seconds
Started Apr 18 12:30:40 PM PDT 24
Finished Apr 18 12:30:42 PM PDT 24
Peak memory 194832 kb
Host smart-5836fadb-108e-45cd-a36c-6dbf4d7eac82
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1938819767 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 14.gpio_same_csr_outstanding.1938819767
Directory /workspace/14.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_tl_errors.2044062759
Short name T783
Test name
Test status
Simulation time 109385466 ps
CPU time 2.15 seconds
Started Apr 18 12:31:11 PM PDT 24
Finished Apr 18 12:31:19 PM PDT 24
Peak memory 196448 kb
Host smart-4c13c1f9-5f17-494b-adea-2d3492afe060
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2044062759 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_tl_errors.2044062759
Directory /workspace/14.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_csr_mem_rw_with_rand_reset.448110483
Short name T777
Test name
Test status
Simulation time 223376574 ps
CPU time 0.85 seconds
Started Apr 18 12:30:14 PM PDT 24
Finished Apr 18 12:30:17 PM PDT 24
Peak memory 197900 kb
Host smart-e652d499-fb7c-4595-8c11-b185ac6b42b5
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=448110483 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_csr_mem_rw_with_rand_reset.448110483
Directory /workspace/15.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_csr_rw.3987008960
Short name T735
Test name
Test status
Simulation time 110493280 ps
CPU time 0.61 seconds
Started Apr 18 12:30:11 PM PDT 24
Finished Apr 18 12:30:14 PM PDT 24
Peak memory 194624 kb
Host smart-526b1908-8e35-4587-b18e-2fcadf74848f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3987008960 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpi
o_csr_rw.3987008960
Directory /workspace/15.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_intr_test.309958458
Short name T744
Test name
Test status
Simulation time 35197014 ps
CPU time 0.58 seconds
Started Apr 18 12:30:09 PM PDT 24
Finished Apr 18 12:30:11 PM PDT 24
Peak memory 193740 kb
Host smart-87d72421-0aaa-4df1-ac06-b8aa82e0bc42
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=309958458 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_intr_test.309958458
Directory /workspace/15.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_same_csr_outstanding.236310343
Short name T80
Test name
Test status
Simulation time 63168199 ps
CPU time 0.66 seconds
Started Apr 18 12:31:36 PM PDT 24
Finished Apr 18 12:31:38 PM PDT 24
Peak memory 194400 kb
Host smart-69df8dc9-370b-498a-8de5-563fcccd40c7
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=236310343 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 15.gpio_same_csr_outstanding.236310343
Directory /workspace/15.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_tl_errors.223338156
Short name T731
Test name
Test status
Simulation time 25029927 ps
CPU time 1.2 seconds
Started Apr 18 12:30:04 PM PDT 24
Finished Apr 18 12:30:06 PM PDT 24
Peak memory 198000 kb
Host smart-35b7df02-b229-42a1-9114-572e81eb3655
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=223338156 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_tl_errors.223338156
Directory /workspace/15.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_tl_intg_err.631474733
Short name T112
Test name
Test status
Simulation time 362692886 ps
CPU time 1.46 seconds
Started Apr 18 12:30:17 PM PDT 24
Finished Apr 18 12:30:19 PM PDT 24
Peak memory 197984 kb
Host smart-f8e4a895-49c7-42ba-a90c-3f5798eab694
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=631474733 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 15.gpio_tl_intg_err.631474733
Directory /workspace/15.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_csr_mem_rw_with_rand_reset.2219798046
Short name T831
Test name
Test status
Simulation time 17022262 ps
CPU time 0.63 seconds
Started Apr 18 12:30:10 PM PDT 24
Finished Apr 18 12:30:13 PM PDT 24
Peak memory 196420 kb
Host smart-a0ccb85d-dd95-4a52-a493-49216ca3abe4
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2219798046 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_csr_mem_rw_with_rand_reset.2219798046
Directory /workspace/16.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_csr_rw.487293452
Short name T78
Test name
Test status
Simulation time 15204521 ps
CPU time 0.64 seconds
Started Apr 18 12:30:23 PM PDT 24
Finished Apr 18 12:30:25 PM PDT 24
Peak memory 195544 kb
Host smart-63f5ad29-e688-418d-8d52-1efce15e8e38
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=487293452 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio
_csr_rw.487293452
Directory /workspace/16.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_intr_test.2262886740
Short name T826
Test name
Test status
Simulation time 42083912 ps
CPU time 0.54 seconds
Started Apr 18 12:30:12 PM PDT 24
Finished Apr 18 12:30:15 PM PDT 24
Peak memory 193632 kb
Host smart-ac461b31-5cc6-4c87-99ed-4bbf59442f20
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2262886740 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_intr_test.2262886740
Directory /workspace/16.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_same_csr_outstanding.3249049976
Short name T795
Test name
Test status
Simulation time 19881634 ps
CPU time 0.79 seconds
Started Apr 18 12:30:07 PM PDT 24
Finished Apr 18 12:30:09 PM PDT 24
Peak memory 196308 kb
Host smart-9e9c5844-9248-4087-90ba-d9b6f6fc2509
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3249049976 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 16.gpio_same_csr_outstanding.3249049976
Directory /workspace/16.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_tl_errors.3544177938
Short name T747
Test name
Test status
Simulation time 51214840 ps
CPU time 2.52 seconds
Started Apr 18 12:30:27 PM PDT 24
Finished Apr 18 12:30:31 PM PDT 24
Peak memory 197920 kb
Host smart-8c2f55be-ecbe-4a79-a13e-cf6908aa0e2f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3544177938 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_tl_errors.3544177938
Directory /workspace/16.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_tl_intg_err.3454497706
Short name T50
Test name
Test status
Simulation time 80338823 ps
CPU time 1.12 seconds
Started Apr 18 12:30:08 PM PDT 24
Finished Apr 18 12:30:10 PM PDT 24
Peak memory 197984 kb
Host smart-e998e547-cd58-46d4-8ef3-29bbb29ff99d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3454497706 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 16.gpio_tl_intg_err.3454497706
Directory /workspace/16.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_csr_mem_rw_with_rand_reset.1991548805
Short name T815
Test name
Test status
Simulation time 29074174 ps
CPU time 0.94 seconds
Started Apr 18 12:30:18 PM PDT 24
Finished Apr 18 12:30:20 PM PDT 24
Peak memory 197936 kb
Host smart-9999c96f-4642-4520-baff-55e0452d205f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1991548805 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_csr_mem_rw_with_rand_reset.1991548805
Directory /workspace/17.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_csr_rw.3895071448
Short name T85
Test name
Test status
Simulation time 14133539 ps
CPU time 0.6 seconds
Started Apr 18 12:30:06 PM PDT 24
Finished Apr 18 12:30:08 PM PDT 24
Peak memory 194916 kb
Host smart-58d7db90-a56a-4317-a46e-a5f5402affc2
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3895071448 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpi
o_csr_rw.3895071448
Directory /workspace/17.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_intr_test.3329672364
Short name T825
Test name
Test status
Simulation time 19138282 ps
CPU time 0.58 seconds
Started Apr 18 12:30:22 PM PDT 24
Finished Apr 18 12:30:24 PM PDT 24
Peak memory 194328 kb
Host smart-13fa3493-49cc-4a6e-b38c-8184b9a5dfff
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3329672364 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_intr_test.3329672364
Directory /workspace/17.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_same_csr_outstanding.2480364048
Short name T768
Test name
Test status
Simulation time 52628052 ps
CPU time 0.63 seconds
Started Apr 18 12:30:11 PM PDT 24
Finished Apr 18 12:30:14 PM PDT 24
Peak memory 195352 kb
Host smart-669be58c-f77c-41e0-a06d-b2b2d5ce44d5
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2480364048 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 17.gpio_same_csr_outstanding.2480364048
Directory /workspace/17.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_tl_errors.16459668
Short name T798
Test name
Test status
Simulation time 40761938 ps
CPU time 1.11 seconds
Started Apr 18 12:30:08 PM PDT 24
Finished Apr 18 12:30:11 PM PDT 24
Peak memory 197836 kb
Host smart-4399e1b3-e281-4ca9-948b-6e28e162f655
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16459668 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_tl_errors.16459668
Directory /workspace/17.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_tl_intg_err.1355224136
Short name T38
Test name
Test status
Simulation time 88301020 ps
CPU time 1.2 seconds
Started Apr 18 12:31:34 PM PDT 24
Finished Apr 18 12:31:36 PM PDT 24
Peak memory 197920 kb
Host smart-897efe71-5681-44d1-9336-d0eb8a993007
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1355224136 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 17.gpio_tl_intg_err.1355224136
Directory /workspace/17.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_csr_mem_rw_with_rand_reset.695781791
Short name T835
Test name
Test status
Simulation time 34540943 ps
CPU time 0.98 seconds
Started Apr 18 12:30:09 PM PDT 24
Finished Apr 18 12:30:12 PM PDT 24
Peak memory 197892 kb
Host smart-4efa2eac-fd86-4a73-801d-615c62b72aad
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=695781791 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_csr_mem_rw_with_rand_reset.695781791
Directory /workspace/18.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_csr_rw.1805772032
Short name T728
Test name
Test status
Simulation time 32024963 ps
CPU time 0.57 seconds
Started Apr 18 12:30:21 PM PDT 24
Finished Apr 18 12:30:23 PM PDT 24
Peak memory 194576 kb
Host smart-488c95d7-4565-41ca-8cde-2af694222606
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1805772032 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpi
o_csr_rw.1805772032
Directory /workspace/18.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_intr_test.4196569723
Short name T748
Test name
Test status
Simulation time 26763330 ps
CPU time 0.57 seconds
Started Apr 18 12:31:36 PM PDT 24
Finished Apr 18 12:31:38 PM PDT 24
Peak memory 193584 kb
Host smart-40870c6c-1e9e-427e-a517-5415f49f4dca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4196569723 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_intr_test.4196569723
Directory /workspace/18.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_same_csr_outstanding.4009165731
Short name T97
Test name
Test status
Simulation time 19276665 ps
CPU time 0.65 seconds
Started Apr 18 12:30:04 PM PDT 24
Finished Apr 18 12:30:05 PM PDT 24
Peak memory 194272 kb
Host smart-0f8fed74-3732-4b25-83ed-144a5a7f66bc
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4009165731 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 18.gpio_same_csr_outstanding.4009165731
Directory /workspace/18.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_tl_errors.3844126981
Short name T736
Test name
Test status
Simulation time 76664325 ps
CPU time 2.18 seconds
Started Apr 18 12:31:11 PM PDT 24
Finished Apr 18 12:31:19 PM PDT 24
Peak memory 196312 kb
Host smart-31062494-4b31-4174-833b-ada13e4c839a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3844126981 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_tl_errors.3844126981
Directory /workspace/18.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_tl_intg_err.1897837081
Short name T39
Test name
Test status
Simulation time 90125016 ps
CPU time 0.88 seconds
Started Apr 18 12:30:11 PM PDT 24
Finished Apr 18 12:30:15 PM PDT 24
Peak memory 197228 kb
Host smart-37463867-b4d4-476e-96b2-b82af8431fdc
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1897837081 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 18.gpio_tl_intg_err.1897837081
Directory /workspace/18.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_csr_mem_rw_with_rand_reset.2850049600
Short name T791
Test name
Test status
Simulation time 26959112 ps
CPU time 0.74 seconds
Started Apr 18 12:30:17 PM PDT 24
Finished Apr 18 12:30:19 PM PDT 24
Peak memory 197932 kb
Host smart-0cc4f549-2040-4bcc-95db-155d6b1adedc
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2850049600 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_csr_mem_rw_with_rand_reset.2850049600
Directory /workspace/19.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_intr_test.452624159
Short name T738
Test name
Test status
Simulation time 22624190 ps
CPU time 0.59 seconds
Started Apr 18 12:31:41 PM PDT 24
Finished Apr 18 12:31:43 PM PDT 24
Peak memory 194288 kb
Host smart-224ccfe2-40f4-41f2-bf07-6ba3a78b9a12
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=452624159 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_intr_test.452624159
Directory /workspace/19.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_same_csr_outstanding.2078755121
Short name T785
Test name
Test status
Simulation time 19987651 ps
CPU time 0.74 seconds
Started Apr 18 12:30:47 PM PDT 24
Finished Apr 18 12:30:54 PM PDT 24
Peak memory 194724 kb
Host smart-61d150c5-ee3f-47c5-87a3-ba0b0e5109d5
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2078755121 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 19.gpio_same_csr_outstanding.2078755121
Directory /workspace/19.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_tl_errors.988200115
Short name T822
Test name
Test status
Simulation time 83884132 ps
CPU time 1.51 seconds
Started Apr 18 12:30:11 PM PDT 24
Finished Apr 18 12:30:14 PM PDT 24
Peak memory 197916 kb
Host smart-a41b5caf-f61a-469d-bcb3-0128499d86e5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=988200115 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_tl_errors.988200115
Directory /workspace/19.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_tl_intg_err.2138735385
Short name T786
Test name
Test status
Simulation time 353392108 ps
CPU time 1.37 seconds
Started Apr 18 12:30:10 PM PDT 24
Finished Apr 18 12:30:14 PM PDT 24
Peak memory 197996 kb
Host smart-4302a949-7c49-4030-a6d9-91075bd380b1
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2138735385 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 19.gpio_tl_intg_err.2138735385
Directory /workspace/19.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_aliasing.2291800104
Short name T81
Test name
Test status
Simulation time 120706749 ps
CPU time 0.75 seconds
Started Apr 18 12:30:03 PM PDT 24
Finished Apr 18 12:30:10 PM PDT 24
Peak memory 195480 kb
Host smart-16bc823c-ca46-43ab-9dbc-c6e18e7aa7ca
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2291800104 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
2.gpio_csr_aliasing.2291800104
Directory /workspace/2.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_bit_bash.3416029273
Short name T766
Test name
Test status
Simulation time 114501628 ps
CPU time 2.22 seconds
Started Apr 18 12:29:57 PM PDT 24
Finished Apr 18 12:30:00 PM PDT 24
Peak memory 197972 kb
Host smart-f928f29b-0706-410c-b125-c840f4bac3bc
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3416029273 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_bit_bash.3416029273
Directory /workspace/2.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_hw_reset.72826783
Short name T89
Test name
Test status
Simulation time 27531557 ps
CPU time 0.6 seconds
Started Apr 18 12:30:01 PM PDT 24
Finished Apr 18 12:30:02 PM PDT 24
Peak memory 194368 kb
Host smart-473a7e41-a053-41dc-8c9b-0589bd4e87c0
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72826783 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_hw_reset.72826783
Directory /workspace/2.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_mem_rw_with_rand_reset.1142510453
Short name T730
Test name
Test status
Simulation time 24991436 ps
CPU time 0.81 seconds
Started Apr 18 12:30:03 PM PDT 24
Finished Apr 18 12:30:05 PM PDT 24
Peak memory 197976 kb
Host smart-b19dfdde-4c9c-4095-ac16-b2d9c4eedbb4
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1142510453 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_mem_rw_with_rand_reset.1142510453
Directory /workspace/2.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_rw.2151537947
Short name T88
Test name
Test status
Simulation time 20005285 ps
CPU time 0.63 seconds
Started Apr 18 12:30:04 PM PDT 24
Finished Apr 18 12:30:06 PM PDT 24
Peak memory 194672 kb
Host smart-921f82a5-5ef5-4270-bb11-60a9b7022081
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2151537947 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio
_csr_rw.2151537947
Directory /workspace/2.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_intr_test.3735700704
Short name T788
Test name
Test status
Simulation time 16157106 ps
CPU time 0.57 seconds
Started Apr 18 12:30:09 PM PDT 24
Finished Apr 18 12:30:11 PM PDT 24
Peak memory 194288 kb
Host smart-cea53048-a10f-4e5f-a949-fa90adecbe30
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3735700704 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_intr_test.3735700704
Directory /workspace/2.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_same_csr_outstanding.2655104868
Short name T751
Test name
Test status
Simulation time 60745160 ps
CPU time 0.8 seconds
Started Apr 18 12:30:03 PM PDT 24
Finished Apr 18 12:30:04 PM PDT 24
Peak memory 196100 kb
Host smart-f31293e7-cbce-43dc-ad7e-46e245ef321c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2655104868 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 2.gpio_same_csr_outstanding.2655104868
Directory /workspace/2.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_tl_errors.3245754440
Short name T725
Test name
Test status
Simulation time 152534547 ps
CPU time 1.02 seconds
Started Apr 18 12:30:00 PM PDT 24
Finished Apr 18 12:30:02 PM PDT 24
Peak memory 197840 kb
Host smart-01724ae8-7369-457e-b0c7-f5ffaa37fd21
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3245754440 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_tl_errors.3245754440
Directory /workspace/2.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_tl_intg_err.657189973
Short name T800
Test name
Test status
Simulation time 378076420 ps
CPU time 1.48 seconds
Started Apr 18 12:29:52 PM PDT 24
Finished Apr 18 12:29:55 PM PDT 24
Peak memory 198056 kb
Host smart-ebdb024d-12be-4914-bf7f-f60a8ca05a68
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=657189973 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 2.gpio_tl_intg_err.657189973
Directory /workspace/2.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.gpio_intr_test.4002897603
Short name T789
Test name
Test status
Simulation time 11369995 ps
CPU time 0.59 seconds
Started Apr 18 12:31:43 PM PDT 24
Finished Apr 18 12:31:45 PM PDT 24
Peak memory 194364 kb
Host smart-45de2f64-c865-4d2e-b2b8-5705aa8eb863
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4002897603 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.gpio_intr_test.4002897603
Directory /workspace/20.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.gpio_intr_test.1244550609
Short name T734
Test name
Test status
Simulation time 13947665 ps
CPU time 0.62 seconds
Started Apr 18 12:30:10 PM PDT 24
Finished Apr 18 12:30:13 PM PDT 24
Peak memory 193772 kb
Host smart-293436fb-b1ca-4427-9b5d-dd7380bf44b1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1244550609 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.gpio_intr_test.1244550609
Directory /workspace/21.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.gpio_intr_test.317647910
Short name T743
Test name
Test status
Simulation time 14917026 ps
CPU time 0.6 seconds
Started Apr 18 12:30:14 PM PDT 24
Finished Apr 18 12:30:17 PM PDT 24
Peak memory 193700 kb
Host smart-126e2176-fbac-4880-b742-fb67a457d462
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=317647910 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.gpio_intr_test.317647910
Directory /workspace/22.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.gpio_intr_test.543689132
Short name T774
Test name
Test status
Simulation time 13589475 ps
CPU time 0.61 seconds
Started Apr 18 12:30:06 PM PDT 24
Finished Apr 18 12:30:08 PM PDT 24
Peak memory 193752 kb
Host smart-2f59f360-2c72-40c6-a2ed-91ae38de3d3f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=543689132 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.gpio_intr_test.543689132
Directory /workspace/23.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.gpio_intr_test.1270978908
Short name T778
Test name
Test status
Simulation time 73066919 ps
CPU time 0.61 seconds
Started Apr 18 12:31:11 PM PDT 24
Finished Apr 18 12:31:18 PM PDT 24
Peak memory 192668 kb
Host smart-8d1d6304-29cb-439c-9f56-8630a19e7160
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1270978908 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.gpio_intr_test.1270978908
Directory /workspace/24.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.gpio_intr_test.1222762060
Short name T753
Test name
Test status
Simulation time 12123276 ps
CPU time 0.57 seconds
Started Apr 18 12:30:11 PM PDT 24
Finished Apr 18 12:30:13 PM PDT 24
Peak memory 193652 kb
Host smart-8f59b759-4bae-4ef3-95f9-a9a38d58ad55
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1222762060 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.gpio_intr_test.1222762060
Directory /workspace/25.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.gpio_intr_test.3962757816
Short name T716
Test name
Test status
Simulation time 38292621 ps
CPU time 0.59 seconds
Started Apr 18 12:30:11 PM PDT 24
Finished Apr 18 12:30:14 PM PDT 24
Peak memory 193712 kb
Host smart-e1dafc5d-4bf4-4cec-a8e1-22e145cba8ac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3962757816 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.gpio_intr_test.3962757816
Directory /workspace/26.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.gpio_intr_test.565703909
Short name T765
Test name
Test status
Simulation time 54418836 ps
CPU time 0.56 seconds
Started Apr 18 12:30:23 PM PDT 24
Finished Apr 18 12:30:25 PM PDT 24
Peak memory 193664 kb
Host smart-ffb03ec2-02d4-4b32-b06f-cb1dc5f922d4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=565703909 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.gpio_intr_test.565703909
Directory /workspace/27.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.gpio_intr_test.3331007002
Short name T741
Test name
Test status
Simulation time 35650963 ps
CPU time 0.6 seconds
Started Apr 18 12:30:09 PM PDT 24
Finished Apr 18 12:30:20 PM PDT 24
Peak memory 193636 kb
Host smart-d42d2dcf-b736-4630-9ae6-51957f6476df
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3331007002 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.gpio_intr_test.3331007002
Directory /workspace/28.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.gpio_intr_test.540328335
Short name T752
Test name
Test status
Simulation time 11668312 ps
CPU time 0.58 seconds
Started Apr 18 12:31:45 PM PDT 24
Finished Apr 18 12:31:47 PM PDT 24
Peak memory 193552 kb
Host smart-f1320409-a829-4a04-8500-c56a593f57e2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=540328335 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.gpio_intr_test.540328335
Directory /workspace/29.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_aliasing.4164747465
Short name T73
Test name
Test status
Simulation time 20886438 ps
CPU time 0.65 seconds
Started Apr 18 12:29:41 PM PDT 24
Finished Apr 18 12:29:42 PM PDT 24
Peak memory 194292 kb
Host smart-015e323a-61ff-47cc-b095-ca1f38cc9d70
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4164747465 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
3.gpio_csr_aliasing.4164747465
Directory /workspace/3.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_bit_bash.3842381093
Short name T74
Test name
Test status
Simulation time 5022715088 ps
CPU time 2.46 seconds
Started Apr 18 12:30:02 PM PDT 24
Finished Apr 18 12:30:05 PM PDT 24
Peak memory 196900 kb
Host smart-0d2fbe1c-7e40-4bea-8672-0b3a693c2a82
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3842381093 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_bit_bash.3842381093
Directory /workspace/3.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_hw_reset.4198187601
Short name T84
Test name
Test status
Simulation time 30392988 ps
CPU time 0.61 seconds
Started Apr 18 12:30:12 PM PDT 24
Finished Apr 18 12:30:15 PM PDT 24
Peak memory 194992 kb
Host smart-e7ce4887-2e5d-4d2d-b665-04f71d69cf9d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4198187601 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_hw_reset.4198187601
Directory /workspace/3.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_mem_rw_with_rand_reset.4071767075
Short name T796
Test name
Test status
Simulation time 20101234 ps
CPU time 0.89 seconds
Started Apr 18 12:29:55 PM PDT 24
Finished Apr 18 12:29:57 PM PDT 24
Peak memory 197812 kb
Host smart-db11d600-be2d-4de1-8218-8a420c005834
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4071767075 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_mem_rw_with_rand_reset.4071767075
Directory /workspace/3.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_rw.2674874715
Short name T737
Test name
Test status
Simulation time 41703986 ps
CPU time 0.63 seconds
Started Apr 18 12:29:54 PM PDT 24
Finished Apr 18 12:29:56 PM PDT 24
Peak memory 194908 kb
Host smart-b16c7314-8d25-42f3-9f92-9e2434d4ffef
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2674874715 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio
_csr_rw.2674874715
Directory /workspace/3.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_intr_test.2586904734
Short name T719
Test name
Test status
Simulation time 44340345 ps
CPU time 0.62 seconds
Started Apr 18 12:30:13 PM PDT 24
Finished Apr 18 12:30:16 PM PDT 24
Peak memory 193744 kb
Host smart-673edbee-f497-45e1-9e2a-d07d1ed123bf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2586904734 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_intr_test.2586904734
Directory /workspace/3.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_same_csr_outstanding.1615570879
Short name T804
Test name
Test status
Simulation time 74767397 ps
CPU time 0.72 seconds
Started Apr 18 12:30:03 PM PDT 24
Finished Apr 18 12:30:05 PM PDT 24
Peak memory 194872 kb
Host smart-13baad70-ee81-4b38-abd3-15abec3a9dca
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1615570879 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 3.gpio_same_csr_outstanding.1615570879
Directory /workspace/3.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_tl_errors.966574054
Short name T811
Test name
Test status
Simulation time 58971177 ps
CPU time 1.4 seconds
Started Apr 18 12:30:28 PM PDT 24
Finished Apr 18 12:30:31 PM PDT 24
Peak memory 198076 kb
Host smart-d0bc25af-6f9b-4291-a97b-9b658f9693c9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=966574054 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_tl_errors.966574054
Directory /workspace/3.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_tl_intg_err.1375591865
Short name T48
Test name
Test status
Simulation time 174321576 ps
CPU time 1.11 seconds
Started Apr 18 12:30:04 PM PDT 24
Finished Apr 18 12:30:07 PM PDT 24
Peak memory 197936 kb
Host smart-1e9e12df-d92e-40f2-8e1f-a8226df85565
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1375591865 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 3.gpio_tl_intg_err.1375591865
Directory /workspace/3.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.gpio_intr_test.2666991847
Short name T812
Test name
Test status
Simulation time 17088035 ps
CPU time 0.6 seconds
Started Apr 18 12:31:43 PM PDT 24
Finished Apr 18 12:31:44 PM PDT 24
Peak memory 193640 kb
Host smart-08211933-54e7-4274-aa4d-c93bde220afa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2666991847 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.gpio_intr_test.2666991847
Directory /workspace/30.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.gpio_intr_test.3373130099
Short name T807
Test name
Test status
Simulation time 42597981 ps
CPU time 0.62 seconds
Started Apr 18 12:30:10 PM PDT 24
Finished Apr 18 12:30:12 PM PDT 24
Peak memory 193708 kb
Host smart-081c4d21-345f-4b13-9438-474a28c747cb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3373130099 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.gpio_intr_test.3373130099
Directory /workspace/31.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.gpio_intr_test.3457033262
Short name T759
Test name
Test status
Simulation time 47828602 ps
CPU time 0.59 seconds
Started Apr 18 12:30:17 PM PDT 24
Finished Apr 18 12:30:19 PM PDT 24
Peak memory 193712 kb
Host smart-d66d702e-9c26-4877-8a43-98904e3cea24
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3457033262 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.gpio_intr_test.3457033262
Directory /workspace/32.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.gpio_intr_test.1314506523
Short name T770
Test name
Test status
Simulation time 53422903 ps
CPU time 0.63 seconds
Started Apr 18 12:31:46 PM PDT 24
Finished Apr 18 12:31:48 PM PDT 24
Peak memory 194256 kb
Host smart-fc4682f0-a622-47d4-aa2b-3c0edc2bdf71
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1314506523 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.gpio_intr_test.1314506523
Directory /workspace/33.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.gpio_intr_test.3212680267
Short name T717
Test name
Test status
Simulation time 12638871 ps
CPU time 0.62 seconds
Started Apr 18 12:30:03 PM PDT 24
Finished Apr 18 12:30:04 PM PDT 24
Peak memory 194360 kb
Host smart-6aafc20e-1f4d-4bd2-a3f1-e0bd82f6f743
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3212680267 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.gpio_intr_test.3212680267
Directory /workspace/34.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.gpio_intr_test.3448446258
Short name T790
Test name
Test status
Simulation time 12276356 ps
CPU time 0.59 seconds
Started Apr 18 12:30:11 PM PDT 24
Finished Apr 18 12:30:13 PM PDT 24
Peak memory 193652 kb
Host smart-9f719e5c-710f-42d3-8ca0-80f381092b8c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3448446258 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.gpio_intr_test.3448446258
Directory /workspace/35.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.gpio_intr_test.4043206206
Short name T810
Test name
Test status
Simulation time 23143039 ps
CPU time 0.61 seconds
Started Apr 18 12:30:09 PM PDT 24
Finished Apr 18 12:30:12 PM PDT 24
Peak memory 193700 kb
Host smart-ffdbb3f7-5683-4ac5-b73a-17ac88492221
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4043206206 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.gpio_intr_test.4043206206
Directory /workspace/36.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.gpio_intr_test.2494405201
Short name T722
Test name
Test status
Simulation time 55529480 ps
CPU time 0.59 seconds
Started Apr 18 12:30:11 PM PDT 24
Finished Apr 18 12:30:14 PM PDT 24
Peak memory 193664 kb
Host smart-765c87f4-516e-41dc-bbc2-d71bdd033eb8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2494405201 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.gpio_intr_test.2494405201
Directory /workspace/37.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.gpio_intr_test.1269542380
Short name T723
Test name
Test status
Simulation time 13213067 ps
CPU time 0.6 seconds
Started Apr 18 12:30:11 PM PDT 24
Finished Apr 18 12:30:14 PM PDT 24
Peak memory 193752 kb
Host smart-6a17c9f8-40c4-4b24-8fb1-3a823b659849
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1269542380 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.gpio_intr_test.1269542380
Directory /workspace/38.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.gpio_intr_test.3088903294
Short name T794
Test name
Test status
Simulation time 15208403 ps
CPU time 0.56 seconds
Started Apr 18 12:30:18 PM PDT 24
Finished Apr 18 12:30:19 PM PDT 24
Peak memory 193664 kb
Host smart-c8a50f95-9ada-4000-b20a-3eb9082ce9df
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3088903294 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.gpio_intr_test.3088903294
Directory /workspace/39.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_aliasing.319657093
Short name T82
Test name
Test status
Simulation time 91225093 ps
CPU time 0.81 seconds
Started Apr 18 12:29:54 PM PDT 24
Finished Apr 18 12:29:56 PM PDT 24
Peak memory 196088 kb
Host smart-0f5a29d6-7a25-4601-9796-b91cf68d7778
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=319657093 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4
.gpio_csr_aliasing.319657093
Directory /workspace/4.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_bit_bash.2513943845
Short name T91
Test name
Test status
Simulation time 303822204 ps
CPU time 2.9 seconds
Started Apr 18 12:30:04 PM PDT 24
Finished Apr 18 12:30:08 PM PDT 24
Peak memory 197156 kb
Host smart-ff38b10f-13cd-44bf-9cdc-92cabf66fc74
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2513943845 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_bit_bash.2513943845
Directory /workspace/4.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_hw_reset.4037587806
Short name T77
Test name
Test status
Simulation time 30566386 ps
CPU time 0.7 seconds
Started Apr 18 12:29:54 PM PDT 24
Finished Apr 18 12:29:56 PM PDT 24
Peak memory 195068 kb
Host smart-59368855-be06-4cfa-9525-0096f830df37
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4037587806 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_hw_reset.4037587806
Directory /workspace/4.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_mem_rw_with_rand_reset.2025261361
Short name T733
Test name
Test status
Simulation time 19972216 ps
CPU time 0.89 seconds
Started Apr 18 12:30:01 PM PDT 24
Finished Apr 18 12:30:03 PM PDT 24
Peak memory 198056 kb
Host smart-ca25ef6f-910e-427a-bf14-5fded8a2bdd8
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2025261361 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_mem_rw_with_rand_reset.2025261361
Directory /workspace/4.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_rw.1565033272
Short name T763
Test name
Test status
Simulation time 24942208 ps
CPU time 0.6 seconds
Started Apr 18 12:30:21 PM PDT 24
Finished Apr 18 12:30:23 PM PDT 24
Peak memory 194872 kb
Host smart-f0a23e7f-3dd3-4a2e-a382-1149fd6a74eb
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1565033272 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio
_csr_rw.1565033272
Directory /workspace/4.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_intr_test.629336479
Short name T801
Test name
Test status
Simulation time 28354724 ps
CPU time 0.58 seconds
Started Apr 18 12:30:04 PM PDT 24
Finished Apr 18 12:30:06 PM PDT 24
Peak memory 193620 kb
Host smart-a1ab7901-7c86-48ff-a44e-5df671331928
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=629336479 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_intr_test.629336479
Directory /workspace/4.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_same_csr_outstanding.456746807
Short name T95
Test name
Test status
Simulation time 119521778 ps
CPU time 0.88 seconds
Started Apr 18 12:29:50 PM PDT 24
Finished Apr 18 12:29:52 PM PDT 24
Peak memory 197068 kb
Host smart-e2ce7431-79b1-45c1-b42b-aefceef71e7b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=456746807 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 4.gpio_same_csr_outstanding.456746807
Directory /workspace/4.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_tl_errors.84851348
Short name T837
Test name
Test status
Simulation time 564902648 ps
CPU time 3.45 seconds
Started Apr 18 12:30:10 PM PDT 24
Finished Apr 18 12:30:15 PM PDT 24
Peak memory 197988 kb
Host smart-cfcbce4d-2886-4e0b-abe7-7b5635c5dbdf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84851348 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_tl_errors.84851348
Directory /workspace/4.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_tl_intg_err.2549059286
Short name T824
Test name
Test status
Simulation time 1026312949 ps
CPU time 1.47 seconds
Started Apr 18 12:29:59 PM PDT 24
Finished Apr 18 12:30:01 PM PDT 24
Peak memory 198020 kb
Host smart-1074bf15-8784-4667-9bce-f2020dbff0e0
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2549059286 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 4.gpio_tl_intg_err.2549059286
Directory /workspace/4.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.gpio_intr_test.1907348010
Short name T799
Test name
Test status
Simulation time 17775893 ps
CPU time 0.63 seconds
Started Apr 18 12:30:11 PM PDT 24
Finished Apr 18 12:30:14 PM PDT 24
Peak memory 193712 kb
Host smart-82962101-0f51-45fd-b27a-6608e2ef6580
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1907348010 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.gpio_intr_test.1907348010
Directory /workspace/40.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.gpio_intr_test.1453276396
Short name T773
Test name
Test status
Simulation time 17788368 ps
CPU time 0.61 seconds
Started Apr 18 12:30:14 PM PDT 24
Finished Apr 18 12:30:17 PM PDT 24
Peak memory 193748 kb
Host smart-c7b8d0d9-56c0-425c-8cfc-c2e40173bc56
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1453276396 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.gpio_intr_test.1453276396
Directory /workspace/41.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.gpio_intr_test.604497655
Short name T834
Test name
Test status
Simulation time 19294306 ps
CPU time 0.61 seconds
Started Apr 18 12:30:16 PM PDT 24
Finished Apr 18 12:30:18 PM PDT 24
Peak memory 194524 kb
Host smart-28233e44-7a9e-4b2f-afa0-1a28e1b77149
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=604497655 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.gpio_intr_test.604497655
Directory /workspace/42.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.gpio_intr_test.392753633
Short name T750
Test name
Test status
Simulation time 60590659 ps
CPU time 0.62 seconds
Started Apr 18 12:30:09 PM PDT 24
Finished Apr 18 12:30:12 PM PDT 24
Peak memory 193696 kb
Host smart-e4af321c-311d-40d1-a266-3b897caa861d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=392753633 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.gpio_intr_test.392753633
Directory /workspace/43.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.gpio_intr_test.308304059
Short name T821
Test name
Test status
Simulation time 12629617 ps
CPU time 0.58 seconds
Started Apr 18 12:30:20 PM PDT 24
Finished Apr 18 12:30:22 PM PDT 24
Peak memory 194352 kb
Host smart-94310c01-f7e3-4082-96d9-6ea26856771a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=308304059 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.gpio_intr_test.308304059
Directory /workspace/44.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.gpio_intr_test.1601301567
Short name T816
Test name
Test status
Simulation time 12579273 ps
CPU time 0.59 seconds
Started Apr 18 12:30:19 PM PDT 24
Finished Apr 18 12:30:20 PM PDT 24
Peak memory 193732 kb
Host smart-ee471932-3040-4850-a229-d9741f3d9a00
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1601301567 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.gpio_intr_test.1601301567
Directory /workspace/45.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.gpio_intr_test.3664443233
Short name T727
Test name
Test status
Simulation time 15377663 ps
CPU time 0.6 seconds
Started Apr 18 12:30:25 PM PDT 24
Finished Apr 18 12:30:28 PM PDT 24
Peak memory 193672 kb
Host smart-8c0bd91e-d03b-443d-898e-f05e4c108c28
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3664443233 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.gpio_intr_test.3664443233
Directory /workspace/46.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.gpio_intr_test.955944583
Short name T806
Test name
Test status
Simulation time 42456096 ps
CPU time 0.63 seconds
Started Apr 18 12:30:52 PM PDT 24
Finished Apr 18 12:30:54 PM PDT 24
Peak memory 194588 kb
Host smart-ce506489-4e24-4649-9165-062b601f842a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=955944583 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.gpio_intr_test.955944583
Directory /workspace/47.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.gpio_intr_test.3350683264
Short name T817
Test name
Test status
Simulation time 84725553 ps
CPU time 0.57 seconds
Started Apr 18 12:30:26 PM PDT 24
Finished Apr 18 12:30:28 PM PDT 24
Peak memory 193684 kb
Host smart-addd4cc7-1281-4e37-aa72-9f394a04cd24
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3350683264 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.gpio_intr_test.3350683264
Directory /workspace/48.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.gpio_intr_test.1365733921
Short name T823
Test name
Test status
Simulation time 48169285 ps
CPU time 0.58 seconds
Started Apr 18 12:30:09 PM PDT 24
Finished Apr 18 12:30:11 PM PDT 24
Peak memory 194304 kb
Host smart-96463ccd-3772-4f01-9a6c-0235249e4825
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1365733921 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.gpio_intr_test.1365733921
Directory /workspace/49.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_csr_mem_rw_with_rand_reset.1070922492
Short name T827
Test name
Test status
Simulation time 64408935 ps
CPU time 0.98 seconds
Started Apr 18 12:30:09 PM PDT 24
Finished Apr 18 12:30:11 PM PDT 24
Peak memory 197936 kb
Host smart-c76ae7e1-188b-4b00-95a6-ede6216484ef
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1070922492 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_csr_mem_rw_with_rand_reset.1070922492
Directory /workspace/5.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_csr_rw.447273475
Short name T90
Test name
Test status
Simulation time 44336054 ps
CPU time 0.61 seconds
Started Apr 18 12:29:55 PM PDT 24
Finished Apr 18 12:29:56 PM PDT 24
Peak memory 194848 kb
Host smart-f74b3ab9-83b0-43a4-80e9-9f6e0f8ebd61
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=447273475 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_
csr_rw.447273475
Directory /workspace/5.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_intr_test.2376437351
Short name T797
Test name
Test status
Simulation time 20538070 ps
CPU time 0.57 seconds
Started Apr 18 12:30:24 PM PDT 24
Finished Apr 18 12:30:27 PM PDT 24
Peak memory 194288 kb
Host smart-592c32c3-ea8e-49f3-9d89-42d8a6964635
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2376437351 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_intr_test.2376437351
Directory /workspace/5.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_same_csr_outstanding.2535356163
Short name T805
Test name
Test status
Simulation time 28080004 ps
CPU time 0.73 seconds
Started Apr 18 12:30:00 PM PDT 24
Finished Apr 18 12:30:01 PM PDT 24
Peak memory 195900 kb
Host smart-3ff19aef-b1d7-4d96-a915-812d45e4fc27
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2535356163 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 5.gpio_same_csr_outstanding.2535356163
Directory /workspace/5.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_tl_errors.4132327274
Short name T836
Test name
Test status
Simulation time 71287188 ps
CPU time 1.91 seconds
Started Apr 18 12:30:17 PM PDT 24
Finished Apr 18 12:30:20 PM PDT 24
Peak memory 197952 kb
Host smart-c7884daa-3b92-40e4-a1e9-c8727623999e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4132327274 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_tl_errors.4132327274
Directory /workspace/5.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_tl_intg_err.1771193755
Short name T46
Test name
Test status
Simulation time 115144966 ps
CPU time 1.13 seconds
Started Apr 18 12:30:11 PM PDT 24
Finished Apr 18 12:30:15 PM PDT 24
Peak memory 198032 kb
Host smart-ff6d7c19-7389-4a22-bda9-094ea6375b3a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1771193755 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 5.gpio_tl_intg_err.1771193755
Directory /workspace/5.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_csr_mem_rw_with_rand_reset.4256263572
Short name T746
Test name
Test status
Simulation time 249054836 ps
CPU time 1.2 seconds
Started Apr 18 12:30:05 PM PDT 24
Finished Apr 18 12:30:08 PM PDT 24
Peak memory 198024 kb
Host smart-3ad34e74-68ad-457f-b430-8f1c5bff97f3
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4256263572 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_csr_mem_rw_with_rand_reset.4256263572
Directory /workspace/6.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_csr_rw.997280004
Short name T838
Test name
Test status
Simulation time 12861287 ps
CPU time 0.62 seconds
Started Apr 18 12:30:40 PM PDT 24
Finished Apr 18 12:30:42 PM PDT 24
Peak memory 194976 kb
Host smart-f0bd3591-d463-4a71-9041-00ba4cc012bf
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=997280004 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_
csr_rw.997280004
Directory /workspace/6.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_intr_test.214264552
Short name T780
Test name
Test status
Simulation time 36421000 ps
CPU time 0.57 seconds
Started Apr 18 12:30:10 PM PDT 24
Finished Apr 18 12:30:13 PM PDT 24
Peak memory 194332 kb
Host smart-d79c36ab-0fd7-4187-9c5c-bd4cd90fca4c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=214264552 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_intr_test.214264552
Directory /workspace/6.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_same_csr_outstanding.3515079017
Short name T762
Test name
Test status
Simulation time 36889470 ps
CPU time 0.83 seconds
Started Apr 18 12:29:54 PM PDT 24
Finished Apr 18 12:29:56 PM PDT 24
Peak memory 196132 kb
Host smart-badcd187-01f6-4a0e-b117-1e6bb9b798ad
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3515079017 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 6.gpio_same_csr_outstanding.3515079017
Directory /workspace/6.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_tl_errors.1198858722
Short name T819
Test name
Test status
Simulation time 46955483 ps
CPU time 2.57 seconds
Started Apr 18 12:30:00 PM PDT 24
Finished Apr 18 12:30:04 PM PDT 24
Peak memory 197992 kb
Host smart-5b7cc3d6-e113-4337-aa1c-eef8586d2709
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1198858722 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_tl_errors.1198858722
Directory /workspace/6.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_tl_intg_err.1271489445
Short name T40
Test name
Test status
Simulation time 122902728 ps
CPU time 1.19 seconds
Started Apr 18 12:30:00 PM PDT 24
Finished Apr 18 12:30:03 PM PDT 24
Peak memory 197992 kb
Host smart-35b2b9db-ff85-4c7d-847d-6ca4b73c6e15
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1271489445 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 6.gpio_tl_intg_err.1271489445
Directory /workspace/6.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_csr_mem_rw_with_rand_reset.1731195339
Short name T740
Test name
Test status
Simulation time 39544313 ps
CPU time 0.74 seconds
Started Apr 18 12:29:56 PM PDT 24
Finished Apr 18 12:29:58 PM PDT 24
Peak memory 197876 kb
Host smart-d7a4b65c-ab02-4c55-b4f3-514df94a8ca3
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1731195339 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_csr_mem_rw_with_rand_reset.1731195339
Directory /workspace/7.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_csr_rw.209766164
Short name T775
Test name
Test status
Simulation time 42799404 ps
CPU time 0.64 seconds
Started Apr 18 12:30:33 PM PDT 24
Finished Apr 18 12:30:34 PM PDT 24
Peak memory 194676 kb
Host smart-9c8b318d-90ca-4c30-9b5f-b69e6c5d810f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=209766164 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_
csr_rw.209766164
Directory /workspace/7.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_intr_test.2697544558
Short name T720
Test name
Test status
Simulation time 99861218 ps
CPU time 0.67 seconds
Started Apr 18 12:29:56 PM PDT 24
Finished Apr 18 12:29:58 PM PDT 24
Peak memory 193656 kb
Host smart-68af90d9-27ce-4d02-96dd-0e7e5fb9c594
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2697544558 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_intr_test.2697544558
Directory /workspace/7.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_same_csr_outstanding.995633210
Short name T813
Test name
Test status
Simulation time 24317871 ps
CPU time 0.61 seconds
Started Apr 18 12:30:07 PM PDT 24
Finished Apr 18 12:30:09 PM PDT 24
Peak memory 194820 kb
Host smart-09bff332-9157-4bb6-835e-e330c4b8e91d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=995633210 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 7.gpio_same_csr_outstanding.995633210
Directory /workspace/7.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_tl_errors.2976416139
Short name T757
Test name
Test status
Simulation time 553926408 ps
CPU time 2.46 seconds
Started Apr 18 12:30:02 PM PDT 24
Finished Apr 18 12:30:05 PM PDT 24
Peak memory 198060 kb
Host smart-32b7ea95-287a-431a-9539-1306888a5e9c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2976416139 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_tl_errors.2976416139
Directory /workspace/7.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_tl_intg_err.3653955984
Short name T833
Test name
Test status
Simulation time 206244720 ps
CPU time 1.46 seconds
Started Apr 18 12:30:08 PM PDT 24
Finished Apr 18 12:30:11 PM PDT 24
Peak memory 198232 kb
Host smart-a25be4d8-1e78-4ac7-8085-b5f84e6d06ee
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3653955984 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 7.gpio_tl_intg_err.3653955984
Directory /workspace/7.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_csr_mem_rw_with_rand_reset.2870918258
Short name T742
Test name
Test status
Simulation time 31726649 ps
CPU time 0.89 seconds
Started Apr 18 12:30:10 PM PDT 24
Finished Apr 18 12:30:13 PM PDT 24
Peak memory 197940 kb
Host smart-33129327-52be-438b-94c9-78fbbb6a7b05
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2870918258 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_csr_mem_rw_with_rand_reset.2870918258
Directory /workspace/8.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_csr_rw.820909630
Short name T86
Test name
Test status
Simulation time 24303967 ps
CPU time 0.58 seconds
Started Apr 18 12:30:13 PM PDT 24
Finished Apr 18 12:30:16 PM PDT 24
Peak memory 194348 kb
Host smart-b45966d0-e785-4c7a-8ee8-03896f8de8cf
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=820909630 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_
csr_rw.820909630
Directory /workspace/8.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_intr_test.582558123
Short name T718
Test name
Test status
Simulation time 15312264 ps
CPU time 0.59 seconds
Started Apr 18 12:30:08 PM PDT 24
Finished Apr 18 12:30:10 PM PDT 24
Peak memory 194528 kb
Host smart-291b1369-cbba-477a-8f46-3488a34ab0cb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=582558123 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_intr_test.582558123
Directory /workspace/8.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_same_csr_outstanding.4244790737
Short name T100
Test name
Test status
Simulation time 32155508 ps
CPU time 0.8 seconds
Started Apr 18 12:30:06 PM PDT 24
Finished Apr 18 12:30:08 PM PDT 24
Peak memory 196256 kb
Host smart-dc28f283-68aa-49d2-acca-501573df4566
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4244790737 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 8.gpio_same_csr_outstanding.4244790737
Directory /workspace/8.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_tl_errors.1740676679
Short name T758
Test name
Test status
Simulation time 134580669 ps
CPU time 2.49 seconds
Started Apr 18 12:30:08 PM PDT 24
Finished Apr 18 12:30:12 PM PDT 24
Peak memory 197996 kb
Host smart-1778e234-45ca-41de-8677-1580e8e3ac24
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1740676679 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_tl_errors.1740676679
Directory /workspace/8.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_tl_intg_err.609672589
Short name T781
Test name
Test status
Simulation time 90194093 ps
CPU time 1.3 seconds
Started Apr 18 12:30:12 PM PDT 24
Finished Apr 18 12:30:16 PM PDT 24
Peak memory 198012 kb
Host smart-bfcf8965-5cfc-49a0-bb0f-c737264e593b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=609672589 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 8.gpio_tl_intg_err.609672589
Directory /workspace/8.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_csr_mem_rw_with_rand_reset.578364045
Short name T721
Test name
Test status
Simulation time 155773076 ps
CPU time 1.55 seconds
Started Apr 18 12:30:09 PM PDT 24
Finished Apr 18 12:30:13 PM PDT 24
Peak memory 198004 kb
Host smart-c5454be8-da0c-42b9-ae2f-7ae61084daeb
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=578364045 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_csr_mem_rw_with_rand_reset.578364045
Directory /workspace/9.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_csr_rw.1651603225
Short name T828
Test name
Test status
Simulation time 24371485 ps
CPU time 0.6 seconds
Started Apr 18 12:30:08 PM PDT 24
Finished Apr 18 12:30:10 PM PDT 24
Peak memory 194468 kb
Host smart-ea2f86fd-99e5-4189-89b9-cc8b8ee925c8
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1651603225 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio
_csr_rw.1651603225
Directory /workspace/9.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_intr_test.2479930060
Short name T808
Test name
Test status
Simulation time 26273721 ps
CPU time 0.61 seconds
Started Apr 18 12:29:59 PM PDT 24
Finished Apr 18 12:30:00 PM PDT 24
Peak memory 193664 kb
Host smart-9f3e612f-27a4-41c2-ba45-8df7081bdda8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2479930060 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_intr_test.2479930060
Directory /workspace/9.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_same_csr_outstanding.4250435915
Short name T98
Test name
Test status
Simulation time 25275065 ps
CPU time 0.66 seconds
Started Apr 18 12:30:08 PM PDT 24
Finished Apr 18 12:30:10 PM PDT 24
Peak memory 195432 kb
Host smart-52dedf42-f04a-44f0-97b0-51f0abf7a755
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4250435915 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 9.gpio_same_csr_outstanding.4250435915
Directory /workspace/9.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_tl_errors.3936029855
Short name T809
Test name
Test status
Simulation time 70401305 ps
CPU time 1.91 seconds
Started Apr 18 12:29:57 PM PDT 24
Finished Apr 18 12:30:00 PM PDT 24
Peak memory 197996 kb
Host smart-091e138b-60ed-45ea-8e61-ac9a9855d64f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3936029855 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_tl_errors.3936029855
Directory /workspace/9.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_tl_intg_err.2043890808
Short name T787
Test name
Test status
Simulation time 51336134 ps
CPU time 0.92 seconds
Started Apr 18 12:29:57 PM PDT 24
Finished Apr 18 12:29:59 PM PDT 24
Peak memory 197232 kb
Host smart-4d75252b-65e2-4202-be3f-6d59c5d5d865
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2043890808 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 9.gpio_tl_intg_err.2043890808
Directory /workspace/9.gpio_tl_intg_err/latest

Test location /workspace/coverage/default/0.gpio_alert_test.1002071859
Short name T645
Test name
Test status
Simulation time 67441530 ps
CPU time 0.57 seconds
Started Apr 18 12:30:40 PM PDT 24
Finished Apr 18 12:30:42 PM PDT 24
Peak memory 194236 kb
Host smart-e05747f1-ef27-4c84-ab6c-7d5dea5caf07
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1002071859 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_alert_test.1002071859
Directory /workspace/0.gpio_alert_test/latest

Test location /workspace/coverage/default/0.gpio_dout_din_regs_random_rw.1080173943
Short name T350
Test name
Test status
Simulation time 57346315 ps
CPU time 0.76 seconds
Started Apr 18 12:30:28 PM PDT 24
Finished Apr 18 12:30:30 PM PDT 24
Peak memory 195296 kb
Host smart-ba7b14be-1ea8-4e9c-8ef0-87402c76aef3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1080173943 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_dout_din_regs_random_rw.1080173943
Directory /workspace/0.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/0.gpio_filter_stress.3144503403
Short name T143
Test name
Test status
Simulation time 6525688840 ps
CPU time 18.44 seconds
Started Apr 18 12:30:49 PM PDT 24
Finished Apr 18 12:31:09 PM PDT 24
Peak memory 198052 kb
Host smart-7bf3b95c-2203-4aa1-bdde-372b155e707a
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3144503403 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_filter_stres
s.3144503403
Directory /workspace/0.gpio_filter_stress/latest

Test location /workspace/coverage/default/0.gpio_full_random.2821872505
Short name T313
Test name
Test status
Simulation time 298802545 ps
CPU time 0.7 seconds
Started Apr 18 12:30:26 PM PDT 24
Finished Apr 18 12:30:29 PM PDT 24
Peak memory 194668 kb
Host smart-e6795050-b64e-4fc8-b7b7-12b9ac1f2930
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2821872505 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_full_random.2821872505
Directory /workspace/0.gpio_full_random/latest

Test location /workspace/coverage/default/0.gpio_intr_rand_pgm.2105968017
Short name T70
Test name
Test status
Simulation time 295100822 ps
CPU time 0.73 seconds
Started Apr 18 12:30:22 PM PDT 24
Finished Apr 18 12:30:24 PM PDT 24
Peak memory 195472 kb
Host smart-09132a35-8083-4c70-9bec-8549b85dea57
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2105968017 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_intr_rand_pgm.2105968017
Directory /workspace/0.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/0.gpio_intr_with_filter_rand_intr_event.1915227294
Short name T16
Test name
Test status
Simulation time 41785427 ps
CPU time 1.73 seconds
Started Apr 18 12:30:41 PM PDT 24
Finished Apr 18 12:30:43 PM PDT 24
Peak memory 198064 kb
Host smart-c5ad3786-aa92-4212-9924-f736f6f0482a
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1915227294 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 0.gpio_intr_with_filter_rand_intr_event.1915227294
Directory /workspace/0.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/0.gpio_rand_intr_trigger.4214826360
Short name T705
Test name
Test status
Simulation time 478749272 ps
CPU time 2.2 seconds
Started Apr 18 12:30:32 PM PDT 24
Finished Apr 18 12:30:35 PM PDT 24
Peak memory 198016 kb
Host smart-94b55f36-d499-4a2e-aa18-d8826a2624f7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4214826360 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_rand_intr_trigger.
4214826360
Directory /workspace/0.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/0.gpio_random_dout_din.4044828395
Short name T559
Test name
Test status
Simulation time 64258695 ps
CPU time 0.85 seconds
Started Apr 18 12:30:25 PM PDT 24
Finished Apr 18 12:30:28 PM PDT 24
Peak memory 196376 kb
Host smart-960d2c7f-8380-4a12-a6d4-4b7f93a58fb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4044828395 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_random_dout_din.4044828395
Directory /workspace/0.gpio_random_dout_din/latest

Test location /workspace/coverage/default/0.gpio_random_dout_din_no_pullup_pulldown.1015525627
Short name T231
Test name
Test status
Simulation time 148995090 ps
CPU time 0.82 seconds
Started Apr 18 12:30:32 PM PDT 24
Finished Apr 18 12:30:34 PM PDT 24
Peak memory 196500 kb
Host smart-0e1afd32-6dc5-442c-9577-cbbede044aee
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1015525627 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_random_dout_din_no_pullup
_pulldown.1015525627
Directory /workspace/0.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/0.gpio_random_long_reg_writes_reg_reads.2326583911
Short name T4
Test name
Test status
Simulation time 2312501567 ps
CPU time 4.65 seconds
Started Apr 18 12:30:35 PM PDT 24
Finished Apr 18 12:30:40 PM PDT 24
Peak memory 197988 kb
Host smart-a6ced260-120f-46ee-ad51-b9b73e86ed4a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2326583911 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_ran
dom_long_reg_writes_reg_reads.2326583911
Directory /workspace/0.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/0.gpio_sec_cm.2306148042
Short name T41
Test name
Test status
Simulation time 388676314 ps
CPU time 0.97 seconds
Started Apr 18 12:30:25 PM PDT 24
Finished Apr 18 12:30:28 PM PDT 24
Peak memory 213568 kb
Host smart-dbb9d8be-8033-4abd-ab3a-84ac84ca0a06
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2306148042 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_sec_cm.2306148042
Directory /workspace/0.gpio_sec_cm/latest

Test location /workspace/coverage/default/0.gpio_smoke.2475116728
Short name T609
Test name
Test status
Simulation time 242431475 ps
CPU time 1.21 seconds
Started Apr 18 12:30:24 PM PDT 24
Finished Apr 18 12:30:27 PM PDT 24
Peak memory 196592 kb
Host smart-159ab199-29b1-44c9-b571-3626451ae9af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2475116728 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_smoke.2475116728
Directory /workspace/0.gpio_smoke/latest

Test location /workspace/coverage/default/0.gpio_smoke_no_pullup_pulldown.2902628504
Short name T701
Test name
Test status
Simulation time 134218651 ps
CPU time 1.11 seconds
Started Apr 18 12:30:26 PM PDT 24
Finished Apr 18 12:30:29 PM PDT 24
Peak memory 195720 kb
Host smart-4c9ce45f-c151-4a22-adde-74d9b25f0c90
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2902628504 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_no_pullup_pulldown.2902628504
Directory /workspace/0.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/0.gpio_stress_all.2751398447
Short name T251
Test name
Test status
Simulation time 14713076865 ps
CPU time 173.51 seconds
Started Apr 18 12:30:20 PM PDT 24
Finished Apr 18 12:33:15 PM PDT 24
Peak memory 198004 kb
Host smart-abc0256f-3470-440a-a9ee-38d7c528d1b0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2751398447 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.g
pio_stress_all.2751398447
Directory /workspace/0.gpio_stress_all/latest

Test location /workspace/coverage/default/1.gpio_alert_test.2965591872
Short name T637
Test name
Test status
Simulation time 13438487 ps
CPU time 0.57 seconds
Started Apr 18 12:30:30 PM PDT 24
Finished Apr 18 12:30:31 PM PDT 24
Peak memory 193812 kb
Host smart-02eb72c2-218a-4c58-a3f8-51ed52a1e1bb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2965591872 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_alert_test.2965591872
Directory /workspace/1.gpio_alert_test/latest

Test location /workspace/coverage/default/1.gpio_dout_din_regs_random_rw.1435318349
Short name T255
Test name
Test status
Simulation time 40955816 ps
CPU time 0.7 seconds
Started Apr 18 12:30:39 PM PDT 24
Finished Apr 18 12:30:41 PM PDT 24
Peak memory 194236 kb
Host smart-9d2b8fde-1dd5-461d-afd8-446a1d738073
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1435318349 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_dout_din_regs_random_rw.1435318349
Directory /workspace/1.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/1.gpio_filter_stress.3286280118
Short name T654
Test name
Test status
Simulation time 663559318 ps
CPU time 16.04 seconds
Started Apr 18 12:30:55 PM PDT 24
Finished Apr 18 12:31:13 PM PDT 24
Peak memory 197932 kb
Host smart-bed14376-f433-4aa2-8664-f8239271a6be
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3286280118 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_filter_stres
s.3286280118
Directory /workspace/1.gpio_filter_stress/latest

Test location /workspace/coverage/default/1.gpio_full_random.2825587851
Short name T461
Test name
Test status
Simulation time 388429053 ps
CPU time 1 seconds
Started Apr 18 12:30:33 PM PDT 24
Finished Apr 18 12:30:34 PM PDT 24
Peak memory 196688 kb
Host smart-4b6ce4ac-ccbb-4035-86af-7a135f6622e5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2825587851 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_full_random.2825587851
Directory /workspace/1.gpio_full_random/latest

Test location /workspace/coverage/default/1.gpio_intr_rand_pgm.863176796
Short name T487
Test name
Test status
Simulation time 35930778 ps
CPU time 0.77 seconds
Started Apr 18 12:30:21 PM PDT 24
Finished Apr 18 12:30:24 PM PDT 24
Peak memory 195528 kb
Host smart-f399a7e5-9732-4068-b830-852ce8af3dc6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=863176796 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_intr_rand_pgm.863176796
Directory /workspace/1.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/1.gpio_rand_intr_trigger.3858618426
Short name T325
Test name
Test status
Simulation time 221051392 ps
CPU time 3.18 seconds
Started Apr 18 12:30:38 PM PDT 24
Finished Apr 18 12:30:42 PM PDT 24
Peak memory 195744 kb
Host smart-01adbb7b-385f-4bb1-965f-c85bfdc8b2a7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3858618426 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_rand_intr_trigger.
3858618426
Directory /workspace/1.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/1.gpio_random_dout_din.2923855466
Short name T426
Test name
Test status
Simulation time 53812809 ps
CPU time 0.67 seconds
Started Apr 18 12:30:24 PM PDT 24
Finished Apr 18 12:30:26 PM PDT 24
Peak memory 195340 kb
Host smart-82dd507d-639d-43aa-a575-7300494a5b18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2923855466 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_random_dout_din.2923855466
Directory /workspace/1.gpio_random_dout_din/latest

Test location /workspace/coverage/default/1.gpio_random_dout_din_no_pullup_pulldown.1649585393
Short name T686
Test name
Test status
Simulation time 22056226 ps
CPU time 0.83 seconds
Started Apr 18 12:30:38 PM PDT 24
Finished Apr 18 12:30:40 PM PDT 24
Peak memory 196056 kb
Host smart-7a1f1e3c-00c6-4876-8848-0d7a8554191d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1649585393 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_random_dout_din_no_pullup
_pulldown.1649585393
Directory /workspace/1.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/1.gpio_random_long_reg_writes_reg_reads.3192691229
Short name T619
Test name
Test status
Simulation time 100931714 ps
CPU time 4.44 seconds
Started Apr 18 12:30:40 PM PDT 24
Finished Apr 18 12:30:46 PM PDT 24
Peak memory 197968 kb
Host smart-84e1d9ec-87c3-4af6-9c05-a8e05668873e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3192691229 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_ran
dom_long_reg_writes_reg_reads.3192691229
Directory /workspace/1.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/1.gpio_sec_cm.1087181092
Short name T42
Test name
Test status
Simulation time 35985836 ps
CPU time 0.77 seconds
Started Apr 18 12:30:14 PM PDT 24
Finished Apr 18 12:30:17 PM PDT 24
Peak memory 213560 kb
Host smart-92d671b8-b43d-47ee-b26d-2353a815f8ec
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1087181092 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_sec_cm.1087181092
Directory /workspace/1.gpio_sec_cm/latest

Test location /workspace/coverage/default/1.gpio_smoke.2415205345
Short name T287
Test name
Test status
Simulation time 160675304 ps
CPU time 0.94 seconds
Started Apr 18 12:30:26 PM PDT 24
Finished Apr 18 12:30:29 PM PDT 24
Peak memory 196036 kb
Host smart-542e66cb-ddbd-4d1b-88fa-2e320524062b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2415205345 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_smoke.2415205345
Directory /workspace/1.gpio_smoke/latest

Test location /workspace/coverage/default/1.gpio_smoke_no_pullup_pulldown.1454661599
Short name T443
Test name
Test status
Simulation time 42090836 ps
CPU time 1.19 seconds
Started Apr 18 12:30:23 PM PDT 24
Finished Apr 18 12:30:26 PM PDT 24
Peak memory 196780 kb
Host smart-7370a1cd-636a-459a-b1cd-e3a15400efcd
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1454661599 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_no_pullup_pulldown.1454661599
Directory /workspace/1.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/1.gpio_stress_all.216459510
Short name T537
Test name
Test status
Simulation time 132112606745 ps
CPU time 164 seconds
Started Apr 18 12:30:26 PM PDT 24
Finished Apr 18 12:33:12 PM PDT 24
Peak memory 198288 kb
Host smart-e14298bd-4aeb-4147-a651-801a6b2bda72
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=216459510 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gp
io_stress_all.216459510
Directory /workspace/1.gpio_stress_all/latest

Test location /workspace/coverage/default/1.gpio_stress_all_with_rand_reset.556117794
Short name T575
Test name
Test status
Simulation time 44574678076 ps
CPU time 1123.25 seconds
Started Apr 18 12:30:34 PM PDT 24
Finished Apr 18 12:49:18 PM PDT 24
Peak memory 198196 kb
Host smart-44584540-9359-4737-82ea-09946abcb04a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=556117794 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_stress_all_with_rand_reset.556117794
Directory /workspace/1.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.gpio_alert_test.3762028441
Short name T257
Test name
Test status
Simulation time 13988743 ps
CPU time 0.56 seconds
Started Apr 18 12:30:46 PM PDT 24
Finished Apr 18 12:30:47 PM PDT 24
Peak memory 194000 kb
Host smart-18a3e20c-ba85-4758-b1ab-7d207ae14790
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3762028441 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_alert_test.3762028441
Directory /workspace/10.gpio_alert_test/latest

Test location /workspace/coverage/default/10.gpio_filter_stress.3434024057
Short name T232
Test name
Test status
Simulation time 2764324975 ps
CPU time 16.83 seconds
Started Apr 18 12:30:59 PM PDT 24
Finished Apr 18 12:31:17 PM PDT 24
Peak memory 197412 kb
Host smart-0d5b8b4e-0e48-4181-9ffd-28ed1a616308
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3434024057 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_filter_stre
ss.3434024057
Directory /workspace/10.gpio_filter_stress/latest

Test location /workspace/coverage/default/10.gpio_full_random.1132872009
Short name T258
Test name
Test status
Simulation time 79469399 ps
CPU time 0.83 seconds
Started Apr 18 12:30:49 PM PDT 24
Finished Apr 18 12:30:52 PM PDT 24
Peak memory 195808 kb
Host smart-9c09c04c-ad09-48d2-a2dd-3736ac0674f2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1132872009 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_full_random.1132872009
Directory /workspace/10.gpio_full_random/latest

Test location /workspace/coverage/default/10.gpio_intr_rand_pgm.1897856340
Short name T587
Test name
Test status
Simulation time 244040040 ps
CPU time 1.12 seconds
Started Apr 18 12:30:50 PM PDT 24
Finished Apr 18 12:30:52 PM PDT 24
Peak memory 196660 kb
Host smart-6dceacce-ab60-43a1-b14f-c7650649f315
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1897856340 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_intr_rand_pgm.1897856340
Directory /workspace/10.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/10.gpio_intr_with_filter_rand_intr_event.2719328081
Short name T320
Test name
Test status
Simulation time 76478648 ps
CPU time 2.91 seconds
Started Apr 18 12:30:59 PM PDT 24
Finished Apr 18 12:31:04 PM PDT 24
Peak memory 198100 kb
Host smart-58170288-c829-45b4-ba67-b64fce61a860
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2719328081 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 10.gpio_intr_with_filter_rand_intr_event.2719328081
Directory /workspace/10.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/10.gpio_rand_intr_trigger.483220858
Short name T138
Test name
Test status
Simulation time 131800367 ps
CPU time 0.96 seconds
Started Apr 18 12:30:50 PM PDT 24
Finished Apr 18 12:30:52 PM PDT 24
Peak memory 196056 kb
Host smart-cb7b5d5a-7245-4fbd-b497-e8ffdaf25880
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=483220858 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_rand_intr_trigger.
483220858
Directory /workspace/10.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/10.gpio_random_dout_din.1233528116
Short name T553
Test name
Test status
Simulation time 57243968 ps
CPU time 1.07 seconds
Started Apr 18 12:30:57 PM PDT 24
Finished Apr 18 12:30:59 PM PDT 24
Peak memory 196768 kb
Host smart-2c0f0014-1718-4ef9-8181-a9ad45a7d34b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1233528116 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_random_dout_din.1233528116
Directory /workspace/10.gpio_random_dout_din/latest

Test location /workspace/coverage/default/10.gpio_random_dout_din_no_pullup_pulldown.160921772
Short name T680
Test name
Test status
Simulation time 105116350 ps
CPU time 0.82 seconds
Started Apr 18 12:30:48 PM PDT 24
Finished Apr 18 12:30:49 PM PDT 24
Peak memory 196688 kb
Host smart-01088b80-ca4c-4dcd-b47e-e43f41ee8041
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=160921772 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_random_dout_din_no_pullup
_pulldown.160921772
Directory /workspace/10.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/10.gpio_random_long_reg_writes_reg_reads.4238013060
Short name T635
Test name
Test status
Simulation time 242525860 ps
CPU time 1.78 seconds
Started Apr 18 12:30:57 PM PDT 24
Finished Apr 18 12:31:00 PM PDT 24
Peak memory 197948 kb
Host smart-bbf741a0-e28c-46ba-bd09-4a878617a007
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4238013060 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_ra
ndom_long_reg_writes_reg_reads.4238013060
Directory /workspace/10.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/10.gpio_smoke.1336258430
Short name T656
Test name
Test status
Simulation time 45081058 ps
CPU time 1.3 seconds
Started Apr 18 12:31:03 PM PDT 24
Finished Apr 18 12:31:10 PM PDT 24
Peak memory 196780 kb
Host smart-dad0bad0-2392-45c1-8eb3-5ec37d2ac8e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1336258430 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_smoke.1336258430
Directory /workspace/10.gpio_smoke/latest

Test location /workspace/coverage/default/10.gpio_smoke_no_pullup_pulldown.2888365213
Short name T669
Test name
Test status
Simulation time 661950217 ps
CPU time 1.1 seconds
Started Apr 18 12:31:07 PM PDT 24
Finished Apr 18 12:31:15 PM PDT 24
Peak memory 197056 kb
Host smart-758f1025-509b-471b-88bb-6790184d86e2
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2888365213 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_no_pullup_pulldown.2888365213
Directory /workspace/10.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/10.gpio_stress_all.2870022898
Short name T167
Test name
Test status
Simulation time 37366843528 ps
CPU time 219.16 seconds
Started Apr 18 12:30:59 PM PDT 24
Finished Apr 18 12:34:39 PM PDT 24
Peak memory 198068 kb
Host smart-31fda603-7fb0-4e12-8963-3c97b2ee7902
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2870022898 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.
gpio_stress_all.2870022898
Directory /workspace/10.gpio_stress_all/latest

Test location /workspace/coverage/default/10.gpio_stress_all_with_rand_reset.3124822920
Short name T473
Test name
Test status
Simulation time 423488879080 ps
CPU time 1157.07 seconds
Started Apr 18 12:30:58 PM PDT 24
Finished Apr 18 12:50:16 PM PDT 24
Peak memory 198068 kb
Host smart-0f8cb1e8-2d34-437a-aa98-387b39042142
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3124822920 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_stress_all_with_rand_reset.3124822920
Directory /workspace/10.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.gpio_alert_test.633035382
Short name T552
Test name
Test status
Simulation time 54723025 ps
CPU time 0.58 seconds
Started Apr 18 12:31:15 PM PDT 24
Finished Apr 18 12:31:19 PM PDT 24
Peak memory 194672 kb
Host smart-94c1074c-09ee-48e6-b985-6a8483f76d0d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=633035382 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_alert_test.633035382
Directory /workspace/11.gpio_alert_test/latest

Test location /workspace/coverage/default/11.gpio_dout_din_regs_random_rw.386881126
Short name T173
Test name
Test status
Simulation time 294092078 ps
CPU time 0.75 seconds
Started Apr 18 12:31:00 PM PDT 24
Finished Apr 18 12:31:04 PM PDT 24
Peak memory 195348 kb
Host smart-c38c265e-80ff-495a-b802-ea7465dce419
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=386881126 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_dout_din_regs_random_rw.386881126
Directory /workspace/11.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/11.gpio_filter_stress.1157342874
Short name T673
Test name
Test status
Simulation time 1437970760 ps
CPU time 10.53 seconds
Started Apr 18 12:31:04 PM PDT 24
Finished Apr 18 12:31:21 PM PDT 24
Peak memory 196808 kb
Host smart-e1f3ee5c-9bd6-48c8-ae93-037bd156a19f
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1157342874 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_filter_stre
ss.1157342874
Directory /workspace/11.gpio_filter_stress/latest

Test location /workspace/coverage/default/11.gpio_full_random.307203924
Short name T318
Test name
Test status
Simulation time 353089819 ps
CPU time 0.86 seconds
Started Apr 18 12:30:56 PM PDT 24
Finished Apr 18 12:30:58 PM PDT 24
Peak memory 195824 kb
Host smart-1018b841-e0ad-43a1-93ff-d13589366c17
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=307203924 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_full_random.307203924
Directory /workspace/11.gpio_full_random/latest

Test location /workspace/coverage/default/11.gpio_intr_rand_pgm.3433831439
Short name T595
Test name
Test status
Simulation time 44488193 ps
CPU time 1.2 seconds
Started Apr 18 12:31:03 PM PDT 24
Finished Apr 18 12:31:09 PM PDT 24
Peak memory 195732 kb
Host smart-9f6967d9-5f1d-4c63-a562-51a4c7dc491f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3433831439 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_intr_rand_pgm.3433831439
Directory /workspace/11.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/11.gpio_intr_with_filter_rand_intr_event.2463429296
Short name T527
Test name
Test status
Simulation time 57666693 ps
CPU time 1.2 seconds
Started Apr 18 12:30:56 PM PDT 24
Finished Apr 18 12:30:59 PM PDT 24
Peak memory 196292 kb
Host smart-e565ac22-1175-44fb-9921-eb5519c70e2d
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2463429296 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 11.gpio_intr_with_filter_rand_intr_event.2463429296
Directory /workspace/11.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/11.gpio_rand_intr_trigger.2009695751
Short name T413
Test name
Test status
Simulation time 46906616 ps
CPU time 1.37 seconds
Started Apr 18 12:31:06 PM PDT 24
Finished Apr 18 12:31:15 PM PDT 24
Peak memory 196812 kb
Host smart-e49623c2-96e3-44ed-ab2f-f3b714de94ca
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2009695751 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_rand_intr_trigger
.2009695751
Directory /workspace/11.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/11.gpio_random_dout_din.3938000337
Short name T53
Test name
Test status
Simulation time 99699477 ps
CPU time 0.97 seconds
Started Apr 18 12:31:04 PM PDT 24
Finished Apr 18 12:31:11 PM PDT 24
Peak memory 195716 kb
Host smart-54674a1c-04e3-4960-819d-3ca0ce31c310
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3938000337 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_random_dout_din.3938000337
Directory /workspace/11.gpio_random_dout_din/latest

Test location /workspace/coverage/default/11.gpio_random_dout_din_no_pullup_pulldown.3321566174
Short name T361
Test name
Test status
Simulation time 73813512 ps
CPU time 0.81 seconds
Started Apr 18 12:30:59 PM PDT 24
Finished Apr 18 12:31:15 PM PDT 24
Peak memory 196552 kb
Host smart-3cfd4c4a-21b0-42d5-8e2e-3b26f03cf5b4
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3321566174 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_random_dout_din_no_pullu
p_pulldown.3321566174
Directory /workspace/11.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/11.gpio_random_long_reg_writes_reg_reads.3195114755
Short name T696
Test name
Test status
Simulation time 54334502 ps
CPU time 1.23 seconds
Started Apr 18 12:30:54 PM PDT 24
Finished Apr 18 12:30:56 PM PDT 24
Peak memory 198000 kb
Host smart-23e8b59a-8b7d-4a6b-a774-108603c9d5e1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3195114755 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_ra
ndom_long_reg_writes_reg_reads.3195114755
Directory /workspace/11.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/11.gpio_smoke.1715629458
Short name T192
Test name
Test status
Simulation time 279556124 ps
CPU time 1.15 seconds
Started Apr 18 12:31:02 PM PDT 24
Finished Apr 18 12:31:10 PM PDT 24
Peak memory 195768 kb
Host smart-31179a4e-12cc-4868-919b-310fc66ddb28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1715629458 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_smoke.1715629458
Directory /workspace/11.gpio_smoke/latest

Test location /workspace/coverage/default/11.gpio_smoke_no_pullup_pulldown.3466681963
Short name T331
Test name
Test status
Simulation time 72121170 ps
CPU time 1.18 seconds
Started Apr 18 12:30:58 PM PDT 24
Finished Apr 18 12:31:00 PM PDT 24
Peak memory 195708 kb
Host smart-76b90055-914a-4933-aa7f-ef95dce75077
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3466681963 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_no_pullup_pulldown.3466681963
Directory /workspace/11.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/11.gpio_stress_all.553326865
Short name T280
Test name
Test status
Simulation time 160244718994 ps
CPU time 199 seconds
Started Apr 18 12:30:49 PM PDT 24
Finished Apr 18 12:34:09 PM PDT 24
Peak memory 198028 kb
Host smart-1b1a9c24-7177-4741-a770-4dd3377bdf28
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=553326865 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.g
pio_stress_all.553326865
Directory /workspace/11.gpio_stress_all/latest

Test location /workspace/coverage/default/12.gpio_alert_test.33761623
Short name T681
Test name
Test status
Simulation time 10637728 ps
CPU time 0.54 seconds
Started Apr 18 12:31:04 PM PDT 24
Finished Apr 18 12:31:10 PM PDT 24
Peak memory 193816 kb
Host smart-d923119a-0948-4caa-8dae-617b3c172d7e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33761623 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_alert_test.33761623
Directory /workspace/12.gpio_alert_test/latest

Test location /workspace/coverage/default/12.gpio_dout_din_regs_random_rw.4123603983
Short name T395
Test name
Test status
Simulation time 133197307 ps
CPU time 0.85 seconds
Started Apr 18 12:31:02 PM PDT 24
Finished Apr 18 12:31:07 PM PDT 24
Peak memory 195212 kb
Host smart-ee9adff5-c27d-4313-a6c6-32002d3863a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4123603983 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_dout_din_regs_random_rw.4123603983
Directory /workspace/12.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/12.gpio_filter_stress.2719516413
Short name T507
Test name
Test status
Simulation time 777708937 ps
CPU time 12.36 seconds
Started Apr 18 12:30:44 PM PDT 24
Finished Apr 18 12:30:57 PM PDT 24
Peak memory 198044 kb
Host smart-f9bea3fa-52b4-4397-88b1-618b000642c7
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2719516413 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_filter_stre
ss.2719516413
Directory /workspace/12.gpio_filter_stress/latest

Test location /workspace/coverage/default/12.gpio_full_random.4163737012
Short name T545
Test name
Test status
Simulation time 74911140 ps
CPU time 0.69 seconds
Started Apr 18 12:31:00 PM PDT 24
Finished Apr 18 12:31:03 PM PDT 24
Peak memory 195132 kb
Host smart-b1168d67-9ce5-4899-8d33-82736bb71e38
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4163737012 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_full_random.4163737012
Directory /workspace/12.gpio_full_random/latest

Test location /workspace/coverage/default/12.gpio_intr_rand_pgm.3895236866
Short name T256
Test name
Test status
Simulation time 220505183 ps
CPU time 1.21 seconds
Started Apr 18 12:31:02 PM PDT 24
Finished Apr 18 12:31:08 PM PDT 24
Peak memory 196008 kb
Host smart-2b47c10c-2715-419d-933d-0ea150a607ef
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3895236866 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_intr_rand_pgm.3895236866
Directory /workspace/12.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/12.gpio_intr_with_filter_rand_intr_event.2069698125
Short name T129
Test name
Test status
Simulation time 22207221 ps
CPU time 0.98 seconds
Started Apr 18 12:31:06 PM PDT 24
Finished Apr 18 12:31:13 PM PDT 24
Peak memory 195996 kb
Host smart-a937a26f-b93d-4392-9cb2-c5ec1a70be7f
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2069698125 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 12.gpio_intr_with_filter_rand_intr_event.2069698125
Directory /workspace/12.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/12.gpio_rand_intr_trigger.2598171025
Short name T252
Test name
Test status
Simulation time 193476305 ps
CPU time 2.75 seconds
Started Apr 18 12:31:00 PM PDT 24
Finished Apr 18 12:31:05 PM PDT 24
Peak memory 197112 kb
Host smart-dc07ba63-bd3c-4c32-a223-5c3e26211da7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2598171025 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_rand_intr_trigger
.2598171025
Directory /workspace/12.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/12.gpio_random_dout_din.753852250
Short name T472
Test name
Test status
Simulation time 167731582 ps
CPU time 1.09 seconds
Started Apr 18 12:30:45 PM PDT 24
Finished Apr 18 12:30:47 PM PDT 24
Peak memory 196500 kb
Host smart-cca89598-ee1e-4d44-b452-eafbfd9ef603
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=753852250 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_random_dout_din.753852250
Directory /workspace/12.gpio_random_dout_din/latest

Test location /workspace/coverage/default/12.gpio_random_dout_din_no_pullup_pulldown.1958152067
Short name T663
Test name
Test status
Simulation time 60641281 ps
CPU time 1.21 seconds
Started Apr 18 12:31:00 PM PDT 24
Finished Apr 18 12:31:03 PM PDT 24
Peak memory 197972 kb
Host smart-1f191908-2e0e-4733-993a-feaf5ce3461a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1958152067 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_random_dout_din_no_pullu
p_pulldown.1958152067
Directory /workspace/12.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/12.gpio_random_long_reg_writes_reg_reads.1222351320
Short name T435
Test name
Test status
Simulation time 111196362 ps
CPU time 5.24 seconds
Started Apr 18 12:30:58 PM PDT 24
Finished Apr 18 12:31:04 PM PDT 24
Peak memory 197952 kb
Host smart-8922c087-c250-40ba-99ab-892a19778571
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1222351320 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_ra
ndom_long_reg_writes_reg_reads.1222351320
Directory /workspace/12.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/12.gpio_smoke.3964268796
Short name T103
Test name
Test status
Simulation time 32021233 ps
CPU time 0.76 seconds
Started Apr 18 12:31:05 PM PDT 24
Finished Apr 18 12:31:13 PM PDT 24
Peak memory 195104 kb
Host smart-eabef6a9-a1fe-48a8-b523-67d4a4164548
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3964268796 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_smoke.3964268796
Directory /workspace/12.gpio_smoke/latest

Test location /workspace/coverage/default/12.gpio_smoke_no_pullup_pulldown.830852606
Short name T25
Test name
Test status
Simulation time 112358260 ps
CPU time 0.96 seconds
Started Apr 18 12:31:00 PM PDT 24
Finished Apr 18 12:31:03 PM PDT 24
Peak memory 195652 kb
Host smart-6833217b-44e8-41dd-ae11-8bb9d5a7d73a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=830852606 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_no_pullup_pulldown.830852606
Directory /workspace/12.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/12.gpio_stress_all.3887819704
Short name T380
Test name
Test status
Simulation time 29907961604 ps
CPU time 96.34 seconds
Started Apr 18 12:31:04 PM PDT 24
Finished Apr 18 12:32:46 PM PDT 24
Peak memory 198068 kb
Host smart-cd2922c1-574d-4e29-846a-8b06546ee885
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3887819704 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.
gpio_stress_all.3887819704
Directory /workspace/12.gpio_stress_all/latest

Test location /workspace/coverage/default/13.gpio_alert_test.2295131363
Short name T189
Test name
Test status
Simulation time 13959362 ps
CPU time 0.58 seconds
Started Apr 18 12:31:46 PM PDT 24
Finished Apr 18 12:31:47 PM PDT 24
Peak memory 193828 kb
Host smart-86a1f9f1-5021-4c93-898b-230fd26929de
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2295131363 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_alert_test.2295131363
Directory /workspace/13.gpio_alert_test/latest

Test location /workspace/coverage/default/13.gpio_dout_din_regs_random_rw.2862556592
Short name T370
Test name
Test status
Simulation time 17208431 ps
CPU time 0.68 seconds
Started Apr 18 12:30:54 PM PDT 24
Finished Apr 18 12:30:56 PM PDT 24
Peak memory 194868 kb
Host smart-da02652f-eb5f-4f91-941a-a2a2379c4659
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2862556592 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_dout_din_regs_random_rw.2862556592
Directory /workspace/13.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/13.gpio_filter_stress.1811829762
Short name T131
Test name
Test status
Simulation time 968389369 ps
CPU time 18.27 seconds
Started Apr 18 12:31:02 PM PDT 24
Finished Apr 18 12:31:24 PM PDT 24
Peak memory 197964 kb
Host smart-27fcf2cc-f9b3-404a-828c-041fc10ff9b6
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1811829762 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_filter_stre
ss.1811829762
Directory /workspace/13.gpio_filter_stress/latest

Test location /workspace/coverage/default/13.gpio_full_random.326563849
Short name T494
Test name
Test status
Simulation time 70858151 ps
CPU time 0.97 seconds
Started Apr 18 12:31:06 PM PDT 24
Finished Apr 18 12:31:13 PM PDT 24
Peak memory 198004 kb
Host smart-b043edc6-9fee-44af-8177-45017e08cf0d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=326563849 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_full_random.326563849
Directory /workspace/13.gpio_full_random/latest

Test location /workspace/coverage/default/13.gpio_intr_rand_pgm.3575521098
Short name T363
Test name
Test status
Simulation time 109911913 ps
CPU time 1.31 seconds
Started Apr 18 12:30:52 PM PDT 24
Finished Apr 18 12:30:54 PM PDT 24
Peak memory 196060 kb
Host smart-ba2d3d48-28f6-4668-bde8-ca5cad54e7e5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3575521098 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_intr_rand_pgm.3575521098
Directory /workspace/13.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/13.gpio_intr_with_filter_rand_intr_event.2353220709
Short name T193
Test name
Test status
Simulation time 301503996 ps
CPU time 3.03 seconds
Started Apr 18 12:31:00 PM PDT 24
Finished Apr 18 12:31:06 PM PDT 24
Peak memory 197964 kb
Host smart-0932c84d-5ef7-482b-9201-b97a1bd3b0f2
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2353220709 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 13.gpio_intr_with_filter_rand_intr_event.2353220709
Directory /workspace/13.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/13.gpio_rand_intr_trigger.694128297
Short name T63
Test name
Test status
Simulation time 82223704 ps
CPU time 1.25 seconds
Started Apr 18 12:31:04 PM PDT 24
Finished Apr 18 12:31:12 PM PDT 24
Peak memory 195748 kb
Host smart-de23765d-118a-4c9a-945a-e255424aa948
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=694128297 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_rand_intr_trigger.
694128297
Directory /workspace/13.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/13.gpio_random_dout_din.2323405933
Short name T642
Test name
Test status
Simulation time 45682057 ps
CPU time 1.1 seconds
Started Apr 18 12:31:00 PM PDT 24
Finished Apr 18 12:31:03 PM PDT 24
Peak memory 196124 kb
Host smart-b650080b-0eb3-4937-81ed-2273734284c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2323405933 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_random_dout_din.2323405933
Directory /workspace/13.gpio_random_dout_din/latest

Test location /workspace/coverage/default/13.gpio_random_dout_din_no_pullup_pulldown.2455293322
Short name T283
Test name
Test status
Simulation time 30116803 ps
CPU time 0.81 seconds
Started Apr 18 12:31:00 PM PDT 24
Finished Apr 18 12:31:04 PM PDT 24
Peak memory 195604 kb
Host smart-be7f5e43-f016-4d27-b29f-fbef47f9774a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2455293322 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_random_dout_din_no_pullu
p_pulldown.2455293322
Directory /workspace/13.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/13.gpio_random_long_reg_writes_reg_reads.3043832320
Short name T617
Test name
Test status
Simulation time 266104624 ps
CPU time 3.43 seconds
Started Apr 18 12:31:00 PM PDT 24
Finished Apr 18 12:31:05 PM PDT 24
Peak memory 197948 kb
Host smart-a6f76f0d-d3a7-4a58-8d57-56a4b82c2c2c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3043832320 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_ra
ndom_long_reg_writes_reg_reads.3043832320
Directory /workspace/13.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/13.gpio_smoke.240562876
Short name T404
Test name
Test status
Simulation time 26325304 ps
CPU time 0.74 seconds
Started Apr 18 12:31:08 PM PDT 24
Finished Apr 18 12:31:16 PM PDT 24
Peak memory 194780 kb
Host smart-ab65243d-fc0e-4c95-9764-80baa9ddee29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=240562876 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_smoke.240562876
Directory /workspace/13.gpio_smoke/latest

Test location /workspace/coverage/default/13.gpio_smoke_no_pullup_pulldown.3745864281
Short name T517
Test name
Test status
Simulation time 96133888 ps
CPU time 0.86 seconds
Started Apr 18 12:30:54 PM PDT 24
Finished Apr 18 12:30:56 PM PDT 24
Peak memory 196068 kb
Host smart-487fceed-bc07-4f1a-8e11-5f12652aae5d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3745864281 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_no_pullup_pulldown.3745864281
Directory /workspace/13.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/13.gpio_stress_all.2923747685
Short name T699
Test name
Test status
Simulation time 34098981344 ps
CPU time 206.97 seconds
Started Apr 18 12:30:56 PM PDT 24
Finished Apr 18 12:34:24 PM PDT 24
Peak memory 198128 kb
Host smart-11f9c84c-b2e4-422d-bb77-69c6d9c17a5d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2923747685 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.
gpio_stress_all.2923747685
Directory /workspace/13.gpio_stress_all/latest

Test location /workspace/coverage/default/13.gpio_stress_all_with_rand_reset.657258763
Short name T61
Test name
Test status
Simulation time 15722357302 ps
CPU time 458.58 seconds
Started Apr 18 12:31:00 PM PDT 24
Finished Apr 18 12:38:41 PM PDT 24
Peak memory 198256 kb
Host smart-9cd665f4-9068-44e1-a057-44e19d883bca
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=657258763 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_stress_all_with_rand_reset.657258763
Directory /workspace/13.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.gpio_dout_din_regs_random_rw.2997886246
Short name T676
Test name
Test status
Simulation time 69644871 ps
CPU time 0.73 seconds
Started Apr 18 12:31:04 PM PDT 24
Finished Apr 18 12:31:11 PM PDT 24
Peak memory 195184 kb
Host smart-1637f431-a99c-4541-a7fc-c4b42ed14813
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2997886246 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_dout_din_regs_random_rw.2997886246
Directory /workspace/14.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/14.gpio_filter_stress.3935555430
Short name T712
Test name
Test status
Simulation time 270548979 ps
CPU time 4.06 seconds
Started Apr 18 12:31:04 PM PDT 24
Finished Apr 18 12:31:14 PM PDT 24
Peak memory 195676 kb
Host smart-96c8cff7-4964-4e75-8e21-4869eb3bb03a
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3935555430 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_filter_stre
ss.3935555430
Directory /workspace/14.gpio_filter_stress/latest

Test location /workspace/coverage/default/14.gpio_full_random.418907717
Short name T310
Test name
Test status
Simulation time 103628233 ps
CPU time 1.11 seconds
Started Apr 18 12:31:13 PM PDT 24
Finished Apr 18 12:31:19 PM PDT 24
Peak memory 196660 kb
Host smart-13fe6868-2d06-4eff-99d3-ed5574bed756
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=418907717 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_full_random.418907717
Directory /workspace/14.gpio_full_random/latest

Test location /workspace/coverage/default/14.gpio_intr_rand_pgm.2590977661
Short name T227
Test name
Test status
Simulation time 34485848 ps
CPU time 1 seconds
Started Apr 18 12:31:00 PM PDT 24
Finished Apr 18 12:31:03 PM PDT 24
Peak memory 196064 kb
Host smart-a21e6b0f-e641-44cf-954c-656705214545
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2590977661 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_intr_rand_pgm.2590977661
Directory /workspace/14.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/14.gpio_intr_with_filter_rand_intr_event.3216887117
Short name T277
Test name
Test status
Simulation time 238946113 ps
CPU time 2.05 seconds
Started Apr 18 12:31:16 PM PDT 24
Finished Apr 18 12:31:22 PM PDT 24
Peak memory 196508 kb
Host smart-68b0c989-7cc3-4846-9b0d-1c405ef07e3f
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3216887117 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 14.gpio_intr_with_filter_rand_intr_event.3216887117
Directory /workspace/14.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/14.gpio_rand_intr_trigger.1109223239
Short name T458
Test name
Test status
Simulation time 261973267 ps
CPU time 1.89 seconds
Started Apr 18 12:31:02 PM PDT 24
Finished Apr 18 12:31:08 PM PDT 24
Peak memory 197020 kb
Host smart-257df2f9-e281-4c30-a007-81b84e059499
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1109223239 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_rand_intr_trigger
.1109223239
Directory /workspace/14.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/14.gpio_random_dout_din.761106766
Short name T145
Test name
Test status
Simulation time 46282600 ps
CPU time 0.77 seconds
Started Apr 18 12:31:07 PM PDT 24
Finished Apr 18 12:31:15 PM PDT 24
Peak memory 195388 kb
Host smart-4e4a1019-c6a7-4c33-bf63-605993210176
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=761106766 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_random_dout_din.761106766
Directory /workspace/14.gpio_random_dout_din/latest

Test location /workspace/coverage/default/14.gpio_random_dout_din_no_pullup_pulldown.1411491868
Short name T240
Test name
Test status
Simulation time 265384388 ps
CPU time 1.16 seconds
Started Apr 18 12:31:10 PM PDT 24
Finished Apr 18 12:31:17 PM PDT 24
Peak memory 196776 kb
Host smart-d7b72348-2fb8-4cfc-a8ef-aec9e25be507
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1411491868 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_random_dout_din_no_pullu
p_pulldown.1411491868
Directory /workspace/14.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/14.gpio_random_long_reg_writes_reg_reads.4226096606
Short name T9
Test name
Test status
Simulation time 587630540 ps
CPU time 3.33 seconds
Started Apr 18 12:31:00 PM PDT 24
Finished Apr 18 12:31:05 PM PDT 24
Peak memory 197928 kb
Host smart-c1759485-7296-4b64-adac-72432af538f2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4226096606 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_ra
ndom_long_reg_writes_reg_reads.4226096606
Directory /workspace/14.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/14.gpio_smoke.3141072375
Short name T163
Test name
Test status
Simulation time 65772767 ps
CPU time 1.15 seconds
Started Apr 18 12:31:03 PM PDT 24
Finished Apr 18 12:31:10 PM PDT 24
Peak memory 195796 kb
Host smart-4f7b8950-1bc6-4641-8aef-96330e08c097
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3141072375 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_smoke.3141072375
Directory /workspace/14.gpio_smoke/latest

Test location /workspace/coverage/default/14.gpio_smoke_no_pullup_pulldown.618532864
Short name T511
Test name
Test status
Simulation time 36149988 ps
CPU time 1.01 seconds
Started Apr 18 12:31:12 PM PDT 24
Finished Apr 18 12:31:18 PM PDT 24
Peak memory 195668 kb
Host smart-4e9ff0ae-ce90-4ef2-8bee-ac1c9c3678bf
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=618532864 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_no_pullup_pulldown.618532864
Directory /workspace/14.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/14.gpio_stress_all.71217259
Short name T534
Test name
Test status
Simulation time 4482080600 ps
CPU time 50.67 seconds
Started Apr 18 12:31:01 PM PDT 24
Finished Apr 18 12:31:55 PM PDT 24
Peak memory 198196 kb
Host smart-165b43f0-b736-4adf-a250-6f6ffc737e0a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71217259 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TE
ST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gp
io_stress_all.71217259
Directory /workspace/14.gpio_stress_all/latest

Test location /workspace/coverage/default/14.gpio_stress_all_with_rand_reset.754587631
Short name T57
Test name
Test status
Simulation time 139935016795 ps
CPU time 1686.8 seconds
Started Apr 18 12:31:08 PM PDT 24
Finished Apr 18 12:59:22 PM PDT 24
Peak memory 198136 kb
Host smart-404928e2-2335-4496-8c1b-1e90b6436a74
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=754587631 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_stress_all_with_rand_reset.754587631
Directory /workspace/14.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.gpio_alert_test.3381957604
Short name T299
Test name
Test status
Simulation time 35185104 ps
CPU time 0.61 seconds
Started Apr 18 12:31:01 PM PDT 24
Finished Apr 18 12:31:04 PM PDT 24
Peak memory 193912 kb
Host smart-e6d50fe0-6399-4764-ad70-71e2e128daf4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3381957604 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_alert_test.3381957604
Directory /workspace/15.gpio_alert_test/latest

Test location /workspace/coverage/default/15.gpio_dout_din_regs_random_rw.2194506199
Short name T65
Test name
Test status
Simulation time 60121511 ps
CPU time 0.78 seconds
Started Apr 18 12:31:11 PM PDT 24
Finished Apr 18 12:31:18 PM PDT 24
Peak memory 195280 kb
Host smart-0994672e-12f7-408b-931f-843d9579ef2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2194506199 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_dout_din_regs_random_rw.2194506199
Directory /workspace/15.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/15.gpio_filter_stress.3606659844
Short name T207
Test name
Test status
Simulation time 1658348119 ps
CPU time 26.71 seconds
Started Apr 18 12:31:05 PM PDT 24
Finished Apr 18 12:31:38 PM PDT 24
Peak memory 197912 kb
Host smart-3411760d-8e60-4e01-8cb1-265f41d6e2f1
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3606659844 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_filter_stre
ss.3606659844
Directory /workspace/15.gpio_filter_stress/latest

Test location /workspace/coverage/default/15.gpio_full_random.2967313864
Short name T62
Test name
Test status
Simulation time 67784847 ps
CPU time 0.98 seconds
Started Apr 18 12:31:07 PM PDT 24
Finished Apr 18 12:31:16 PM PDT 24
Peak memory 196304 kb
Host smart-b13a2fce-535c-4ce6-8815-eac0214a96df
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2967313864 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_full_random.2967313864
Directory /workspace/15.gpio_full_random/latest

Test location /workspace/coverage/default/15.gpio_intr_rand_pgm.2485511494
Short name T230
Test name
Test status
Simulation time 214853539 ps
CPU time 1.24 seconds
Started Apr 18 12:31:02 PM PDT 24
Finished Apr 18 12:31:06 PM PDT 24
Peak memory 196664 kb
Host smart-0e362ca0-2323-4042-98af-1dbc4c6e5016
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2485511494 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_intr_rand_pgm.2485511494
Directory /workspace/15.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/15.gpio_intr_with_filter_rand_intr_event.2110956590
Short name T197
Test name
Test status
Simulation time 200407584 ps
CPU time 2.01 seconds
Started Apr 18 12:31:04 PM PDT 24
Finished Apr 18 12:31:12 PM PDT 24
Peak memory 197988 kb
Host smart-518d7f14-7859-4bbd-8c4c-b97cd2864b26
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2110956590 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 15.gpio_intr_with_filter_rand_intr_event.2110956590
Directory /workspace/15.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/15.gpio_rand_intr_trigger.374739669
Short name T589
Test name
Test status
Simulation time 75332633 ps
CPU time 2.3 seconds
Started Apr 18 12:31:08 PM PDT 24
Finished Apr 18 12:31:18 PM PDT 24
Peak memory 196968 kb
Host smart-934d6d24-c860-4bcb-8d36-c9ea2d8a55a6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=374739669 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_rand_intr_trigger.
374739669
Directory /workspace/15.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/15.gpio_random_dout_din.4058843909
Short name T500
Test name
Test status
Simulation time 37707831 ps
CPU time 0.83 seconds
Started Apr 18 12:31:04 PM PDT 24
Finished Apr 18 12:31:10 PM PDT 24
Peak memory 197292 kb
Host smart-024ec4f7-d80c-4530-9c7e-7fbe2f934ce4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4058843909 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_random_dout_din.4058843909
Directory /workspace/15.gpio_random_dout_din/latest

Test location /workspace/coverage/default/15.gpio_random_dout_din_no_pullup_pulldown.3999807515
Short name T631
Test name
Test status
Simulation time 386735587 ps
CPU time 0.85 seconds
Started Apr 18 12:31:01 PM PDT 24
Finished Apr 18 12:31:05 PM PDT 24
Peak memory 196364 kb
Host smart-9cc77453-8ab0-4d28-b369-4f2aeadf13f6
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3999807515 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_random_dout_din_no_pullu
p_pulldown.3999807515
Directory /workspace/15.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/15.gpio_random_long_reg_writes_reg_reads.942767168
Short name T459
Test name
Test status
Simulation time 442466546 ps
CPU time 6.16 seconds
Started Apr 18 12:31:23 PM PDT 24
Finished Apr 18 12:31:31 PM PDT 24
Peak memory 197964 kb
Host smart-67a012ee-6dff-4b32-b529-6ca58e524a90
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=942767168 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_ran
dom_long_reg_writes_reg_reads.942767168
Directory /workspace/15.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/15.gpio_smoke.4050253581
Short name T128
Test name
Test status
Simulation time 84123609 ps
CPU time 1.3 seconds
Started Apr 18 12:31:11 PM PDT 24
Finished Apr 18 12:31:18 PM PDT 24
Peak memory 197032 kb
Host smart-f106ec12-4ff3-452c-9a63-ff9be03501a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4050253581 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_smoke.4050253581
Directory /workspace/15.gpio_smoke/latest

Test location /workspace/coverage/default/15.gpio_smoke_no_pullup_pulldown.2116834494
Short name T422
Test name
Test status
Simulation time 81442190 ps
CPU time 0.91 seconds
Started Apr 18 12:30:58 PM PDT 24
Finished Apr 18 12:31:00 PM PDT 24
Peak memory 196388 kb
Host smart-d324b62e-d190-46f3-96dc-7439f51363ec
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2116834494 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_no_pullup_pulldown.2116834494
Directory /workspace/15.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/15.gpio_stress_all.4243450256
Short name T479
Test name
Test status
Simulation time 8643780198 ps
CPU time 104.94 seconds
Started Apr 18 12:31:02 PM PDT 24
Finished Apr 18 12:32:50 PM PDT 24
Peak memory 197992 kb
Host smart-3c6b1f00-b8cd-411f-bd5e-43cc91a628c1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4243450256 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.
gpio_stress_all.4243450256
Directory /workspace/15.gpio_stress_all/latest

Test location /workspace/coverage/default/16.gpio_alert_test.3873639331
Short name T603
Test name
Test status
Simulation time 41942971 ps
CPU time 0.59 seconds
Started Apr 18 12:31:04 PM PDT 24
Finished Apr 18 12:31:10 PM PDT 24
Peak memory 194956 kb
Host smart-0a47d463-386c-47ac-b7aa-9e3441b066a2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3873639331 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_alert_test.3873639331
Directory /workspace/16.gpio_alert_test/latest

Test location /workspace/coverage/default/16.gpio_dout_din_regs_random_rw.2067283299
Short name T610
Test name
Test status
Simulation time 17970151 ps
CPU time 0.69 seconds
Started Apr 18 12:31:17 PM PDT 24
Finished Apr 18 12:31:25 PM PDT 24
Peak memory 193988 kb
Host smart-81a36ad2-8c46-4aeb-a543-478b34117636
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2067283299 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_dout_din_regs_random_rw.2067283299
Directory /workspace/16.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/16.gpio_filter_stress.2715890674
Short name T411
Test name
Test status
Simulation time 98382991 ps
CPU time 5 seconds
Started Apr 18 12:31:04 PM PDT 24
Finished Apr 18 12:31:15 PM PDT 24
Peak memory 196560 kb
Host smart-4549e2bf-39b6-436e-bc5a-78c36cc2061b
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2715890674 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_filter_stre
ss.2715890674
Directory /workspace/16.gpio_filter_stress/latest

Test location /workspace/coverage/default/16.gpio_full_random.3257869885
Short name T480
Test name
Test status
Simulation time 52166706 ps
CPU time 0.77 seconds
Started Apr 18 12:32:03 PM PDT 24
Finished Apr 18 12:32:11 PM PDT 24
Peak memory 194704 kb
Host smart-b693a211-deff-44b3-9288-d7fa781b4a6e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3257869885 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_full_random.3257869885
Directory /workspace/16.gpio_full_random/latest

Test location /workspace/coverage/default/16.gpio_intr_rand_pgm.603238237
Short name T450
Test name
Test status
Simulation time 430293110 ps
CPU time 1.24 seconds
Started Apr 18 12:31:12 PM PDT 24
Finished Apr 18 12:31:19 PM PDT 24
Peak memory 196912 kb
Host smart-dca1c811-4d53-4595-97ab-1712588c8b0c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=603238237 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_intr_rand_pgm.603238237
Directory /workspace/16.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/16.gpio_intr_with_filter_rand_intr_event.3515495813
Short name T26
Test name
Test status
Simulation time 215840465 ps
CPU time 2.12 seconds
Started Apr 18 12:31:20 PM PDT 24
Finished Apr 18 12:31:25 PM PDT 24
Peak memory 197948 kb
Host smart-65587940-88a7-43ec-b7fa-749d6105acf6
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3515495813 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 16.gpio_intr_with_filter_rand_intr_event.3515495813
Directory /workspace/16.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/16.gpio_rand_intr_trigger.3891873533
Short name T249
Test name
Test status
Simulation time 479482017 ps
CPU time 3.06 seconds
Started Apr 18 12:31:13 PM PDT 24
Finished Apr 18 12:31:21 PM PDT 24
Peak memory 197420 kb
Host smart-ff8595de-2e0a-4f5d-8713-00cea2c804b3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3891873533 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_rand_intr_trigger
.3891873533
Directory /workspace/16.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/16.gpio_random_dout_din.3261511136
Short name T171
Test name
Test status
Simulation time 125660787 ps
CPU time 0.78 seconds
Started Apr 18 12:31:03 PM PDT 24
Finished Apr 18 12:31:09 PM PDT 24
Peak memory 195464 kb
Host smart-d4b3a283-61de-4a46-a938-55f86f4bf333
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3261511136 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_random_dout_din.3261511136
Directory /workspace/16.gpio_random_dout_din/latest

Test location /workspace/coverage/default/16.gpio_random_dout_din_no_pullup_pulldown.383480250
Short name T335
Test name
Test status
Simulation time 53106338 ps
CPU time 0.64 seconds
Started Apr 18 12:31:14 PM PDT 24
Finished Apr 18 12:31:19 PM PDT 24
Peak memory 194964 kb
Host smart-a7740538-b908-4819-897b-3755d35a458c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=383480250 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_random_dout_din_no_pullup
_pulldown.383480250
Directory /workspace/16.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/16.gpio_random_long_reg_writes_reg_reads.1318967624
Short name T561
Test name
Test status
Simulation time 181770528 ps
CPU time 1.51 seconds
Started Apr 18 12:31:09 PM PDT 24
Finished Apr 18 12:31:18 PM PDT 24
Peak memory 197868 kb
Host smart-8be30ebc-310e-407f-ae03-0c0a248e1eef
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1318967624 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_ra
ndom_long_reg_writes_reg_reads.1318967624
Directory /workspace/16.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/16.gpio_smoke.520098796
Short name T334
Test name
Test status
Simulation time 76956199 ps
CPU time 0.9 seconds
Started Apr 18 12:31:13 PM PDT 24
Finished Apr 18 12:31:19 PM PDT 24
Peak memory 196280 kb
Host smart-95f78525-7521-46a3-8e3d-87f6d53428d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=520098796 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_smoke.520098796
Directory /workspace/16.gpio_smoke/latest

Test location /workspace/coverage/default/16.gpio_smoke_no_pullup_pulldown.3315383626
Short name T525
Test name
Test status
Simulation time 119550412 ps
CPU time 0.87 seconds
Started Apr 18 12:31:05 PM PDT 24
Finished Apr 18 12:31:13 PM PDT 24
Peak memory 196056 kb
Host smart-2382592d-89f4-4eef-8716-ac691b469803
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3315383626 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_no_pullup_pulldown.3315383626
Directory /workspace/16.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/16.gpio_stress_all.998975486
Short name T10
Test name
Test status
Simulation time 148454220047 ps
CPU time 196.01 seconds
Started Apr 18 12:31:00 PM PDT 24
Finished Apr 18 12:34:18 PM PDT 24
Peak memory 198008 kb
Host smart-7d60b3a7-274c-481a-a55f-3340fa0638d8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=998975486 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.g
pio_stress_all.998975486
Directory /workspace/16.gpio_stress_all/latest

Test location /workspace/coverage/default/17.gpio_alert_test.1272104844
Short name T551
Test name
Test status
Simulation time 18579602 ps
CPU time 0.56 seconds
Started Apr 18 12:31:00 PM PDT 24
Finished Apr 18 12:31:03 PM PDT 24
Peak memory 194564 kb
Host smart-f120b423-e53d-4e48-8277-ee68fd6e0899
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1272104844 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_alert_test.1272104844
Directory /workspace/17.gpio_alert_test/latest

Test location /workspace/coverage/default/17.gpio_dout_din_regs_random_rw.4193825522
Short name T308
Test name
Test status
Simulation time 210500184 ps
CPU time 0.99 seconds
Started Apr 18 12:32:03 PM PDT 24
Finished Apr 18 12:32:07 PM PDT 24
Peak memory 192948 kb
Host smart-d6fc0b19-9ad4-4657-9c86-d7162b329ae2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4193825522 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_dout_din_regs_random_rw.4193825522
Directory /workspace/17.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/17.gpio_filter_stress.4033006296
Short name T455
Test name
Test status
Simulation time 622443030 ps
CPU time 21.05 seconds
Started Apr 18 12:32:03 PM PDT 24
Finished Apr 18 12:32:27 PM PDT 24
Peak memory 192604 kb
Host smart-1b22b518-529a-40bf-a491-a80ac270d2a2
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4033006296 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_filter_stre
ss.4033006296
Directory /workspace/17.gpio_filter_stress/latest

Test location /workspace/coverage/default/17.gpio_full_random.1296344077
Short name T674
Test name
Test status
Simulation time 58035077 ps
CPU time 0.84 seconds
Started Apr 18 12:32:28 PM PDT 24
Finished Apr 18 12:32:30 PM PDT 24
Peak memory 196640 kb
Host smart-3a26b904-cf48-44ee-b996-0892f51053c8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1296344077 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_full_random.1296344077
Directory /workspace/17.gpio_full_random/latest

Test location /workspace/coverage/default/17.gpio_intr_rand_pgm.3976089935
Short name T468
Test name
Test status
Simulation time 282399600 ps
CPU time 1.35 seconds
Started Apr 18 12:32:03 PM PDT 24
Finished Apr 18 12:32:07 PM PDT 24
Peak memory 194444 kb
Host smart-c8818f54-2bf6-4a30-8af0-27c4c311ea6c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3976089935 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_intr_rand_pgm.3976089935
Directory /workspace/17.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/17.gpio_intr_with_filter_rand_intr_event.959103514
Short name T688
Test name
Test status
Simulation time 303951092 ps
CPU time 2.95 seconds
Started Apr 18 12:31:10 PM PDT 24
Finished Apr 18 12:31:22 PM PDT 24
Peak memory 198280 kb
Host smart-e0fc000b-1ea2-4e9b-af48-3afe97e0a15b
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=959103514 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 17.gpio_intr_with_filter_rand_intr_event.959103514
Directory /workspace/17.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/17.gpio_rand_intr_trigger.2358693476
Short name T652
Test name
Test status
Simulation time 112716693 ps
CPU time 2.5 seconds
Started Apr 18 12:31:15 PM PDT 24
Finished Apr 18 12:31:26 PM PDT 24
Peak memory 197956 kb
Host smart-01c3f50d-d6f6-4af4-97f0-d5ff3f73100f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2358693476 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_rand_intr_trigger
.2358693476
Directory /workspace/17.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/17.gpio_random_dout_din.1516859040
Short name T434
Test name
Test status
Simulation time 27484455 ps
CPU time 0.67 seconds
Started Apr 18 12:31:11 PM PDT 24
Finished Apr 18 12:31:17 PM PDT 24
Peak memory 195256 kb
Host smart-d55f042e-843e-4951-a0a6-52c6e988f31a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1516859040 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_random_dout_din.1516859040
Directory /workspace/17.gpio_random_dout_din/latest

Test location /workspace/coverage/default/17.gpio_random_dout_din_no_pullup_pulldown.1580276475
Short name T620
Test name
Test status
Simulation time 131352214 ps
CPU time 1.24 seconds
Started Apr 18 12:31:14 PM PDT 24
Finished Apr 18 12:31:19 PM PDT 24
Peak memory 196992 kb
Host smart-7ed00079-10be-4b19-9644-b231c671e5ca
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1580276475 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_random_dout_din_no_pullu
p_pulldown.1580276475
Directory /workspace/17.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/17.gpio_random_long_reg_writes_reg_reads.3496446907
Short name T685
Test name
Test status
Simulation time 847845196 ps
CPU time 3.99 seconds
Started Apr 18 12:31:19 PM PDT 24
Finished Apr 18 12:31:26 PM PDT 24
Peak memory 198092 kb
Host smart-676223ab-d86e-4e8f-b3c8-238c23661974
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3496446907 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_ra
ndom_long_reg_writes_reg_reads.3496446907
Directory /workspace/17.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/17.gpio_smoke.3795139063
Short name T342
Test name
Test status
Simulation time 79199580 ps
CPU time 0.9 seconds
Started Apr 18 12:31:09 PM PDT 24
Finished Apr 18 12:31:17 PM PDT 24
Peak memory 196232 kb
Host smart-2e061660-ffc7-4d39-a0f5-b365f0641978
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3795139063 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_smoke.3795139063
Directory /workspace/17.gpio_smoke/latest

Test location /workspace/coverage/default/17.gpio_smoke_no_pullup_pulldown.3305440574
Short name T290
Test name
Test status
Simulation time 35817565 ps
CPU time 0.88 seconds
Started Apr 18 12:31:04 PM PDT 24
Finished Apr 18 12:31:11 PM PDT 24
Peak memory 195980 kb
Host smart-b3fb28ae-4cab-4048-bd4c-6e140c81a3ae
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3305440574 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_no_pullup_pulldown.3305440574
Directory /workspace/17.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/17.gpio_stress_all.1932882537
Short name T238
Test name
Test status
Simulation time 13863478593 ps
CPU time 45.09 seconds
Started Apr 18 12:31:01 PM PDT 24
Finished Apr 18 12:31:50 PM PDT 24
Peak memory 198304 kb
Host smart-9afc69ca-6502-4401-817c-534dce9aa24d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1932882537 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.
gpio_stress_all.1932882537
Directory /workspace/17.gpio_stress_all/latest

Test location /workspace/coverage/default/18.gpio_alert_test.4227048443
Short name T373
Test name
Test status
Simulation time 23738591 ps
CPU time 0.57 seconds
Started Apr 18 12:31:02 PM PDT 24
Finished Apr 18 12:31:07 PM PDT 24
Peak memory 194700 kb
Host smart-a96490fa-dfac-4590-8a87-de1578c9e61b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4227048443 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_alert_test.4227048443
Directory /workspace/18.gpio_alert_test/latest

Test location /workspace/coverage/default/18.gpio_dout_din_regs_random_rw.2172753467
Short name T130
Test name
Test status
Simulation time 106522133 ps
CPU time 0.76 seconds
Started Apr 18 12:31:03 PM PDT 24
Finished Apr 18 12:31:09 PM PDT 24
Peak memory 196140 kb
Host smart-c0dc77b6-97bf-4d0f-b19a-6453e65ce3dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2172753467 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_dout_din_regs_random_rw.2172753467
Directory /workspace/18.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/18.gpio_filter_stress.493881266
Short name T166
Test name
Test status
Simulation time 750127926 ps
CPU time 25.52 seconds
Started Apr 18 12:31:05 PM PDT 24
Finished Apr 18 12:31:36 PM PDT 24
Peak memory 196892 kb
Host smart-9152f61a-bb84-46e3-a07c-a6901af4d88c
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=493881266 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_filter_stres
s.493881266
Directory /workspace/18.gpio_filter_stress/latest

Test location /workspace/coverage/default/18.gpio_full_random.900476780
Short name T638
Test name
Test status
Simulation time 167022690 ps
CPU time 0.79 seconds
Started Apr 18 12:31:07 PM PDT 24
Finished Apr 18 12:31:15 PM PDT 24
Peak memory 195760 kb
Host smart-90f142b9-6d9f-4552-b6b1-1c6c51725d97
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=900476780 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_full_random.900476780
Directory /workspace/18.gpio_full_random/latest

Test location /workspace/coverage/default/18.gpio_intr_rand_pgm.876630028
Short name T489
Test name
Test status
Simulation time 100594294 ps
CPU time 1.25 seconds
Started Apr 18 12:31:14 PM PDT 24
Finished Apr 18 12:31:20 PM PDT 24
Peak memory 196936 kb
Host smart-2e8838c6-c244-4e06-a3e4-78d4fd09327a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=876630028 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_intr_rand_pgm.876630028
Directory /workspace/18.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/18.gpio_intr_with_filter_rand_intr_event.3602311795
Short name T351
Test name
Test status
Simulation time 246121258 ps
CPU time 1.42 seconds
Started Apr 18 12:31:10 PM PDT 24
Finished Apr 18 12:31:18 PM PDT 24
Peak memory 196612 kb
Host smart-67247ad1-4142-47b9-b2fa-247e8efe32e0
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3602311795 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 18.gpio_intr_with_filter_rand_intr_event.3602311795
Directory /workspace/18.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/18.gpio_rand_intr_trigger.925662751
Short name T440
Test name
Test status
Simulation time 92220445 ps
CPU time 2.48 seconds
Started Apr 18 12:31:11 PM PDT 24
Finished Apr 18 12:31:22 PM PDT 24
Peak memory 197248 kb
Host smart-5efaea4c-14a7-4055-b7d7-bd35af483782
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=925662751 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_rand_intr_trigger.
925662751
Directory /workspace/18.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/18.gpio_random_dout_din.4260596366
Short name T389
Test name
Test status
Simulation time 22909641 ps
CPU time 0.89 seconds
Started Apr 18 12:32:32 PM PDT 24
Finished Apr 18 12:32:33 PM PDT 24
Peak memory 195924 kb
Host smart-dd182c86-7b6e-43de-ac70-18e4fab1c4a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4260596366 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_random_dout_din.4260596366
Directory /workspace/18.gpio_random_dout_din/latest

Test location /workspace/coverage/default/18.gpio_random_dout_din_no_pullup_pulldown.1302343976
Short name T451
Test name
Test status
Simulation time 46517013 ps
CPU time 0.94 seconds
Started Apr 18 12:31:11 PM PDT 24
Finished Apr 18 12:31:18 PM PDT 24
Peak memory 196480 kb
Host smart-0144615b-be9f-4805-89a6-cbab95783a6f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1302343976 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_random_dout_din_no_pullu
p_pulldown.1302343976
Directory /workspace/18.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/18.gpio_random_long_reg_writes_reg_reads.3029864710
Short name T5
Test name
Test status
Simulation time 507191505 ps
CPU time 5.77 seconds
Started Apr 18 12:31:23 PM PDT 24
Finished Apr 18 12:31:30 PM PDT 24
Peak memory 197940 kb
Host smart-6c6bf3dc-34c4-4cad-8d58-d9685d76b0f7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3029864710 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_ra
ndom_long_reg_writes_reg_reads.3029864710
Directory /workspace/18.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/18.gpio_smoke.3807701066
Short name T427
Test name
Test status
Simulation time 97863116 ps
CPU time 1.1 seconds
Started Apr 18 12:31:09 PM PDT 24
Finished Apr 18 12:31:17 PM PDT 24
Peak memory 195484 kb
Host smart-640f58d5-27bf-426a-937e-fd99b4a91e95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3807701066 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_smoke.3807701066
Directory /workspace/18.gpio_smoke/latest

Test location /workspace/coverage/default/18.gpio_smoke_no_pullup_pulldown.3624878383
Short name T215
Test name
Test status
Simulation time 463196009 ps
CPU time 1.19 seconds
Started Apr 18 12:32:03 PM PDT 24
Finished Apr 18 12:32:07 PM PDT 24
Peak memory 193152 kb
Host smart-53cd0c97-d8c4-45a9-aec8-2d60bdf11118
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3624878383 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_no_pullup_pulldown.3624878383
Directory /workspace/18.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/18.gpio_stress_all.261268880
Short name T439
Test name
Test status
Simulation time 2250223741 ps
CPU time 57.11 seconds
Started Apr 18 12:31:13 PM PDT 24
Finished Apr 18 12:32:15 PM PDT 24
Peak memory 198228 kb
Host smart-45893aa8-49b1-4111-a1f0-2a40faf65ac2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=261268880 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.g
pio_stress_all.261268880
Directory /workspace/18.gpio_stress_all/latest

Test location /workspace/coverage/default/19.gpio_alert_test.2362714623
Short name T661
Test name
Test status
Simulation time 21207890 ps
CPU time 0.54 seconds
Started Apr 18 12:31:06 PM PDT 24
Finished Apr 18 12:31:14 PM PDT 24
Peak memory 193828 kb
Host smart-73078858-063d-496c-91fd-d693fcd151ce
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2362714623 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_alert_test.2362714623
Directory /workspace/19.gpio_alert_test/latest

Test location /workspace/coverage/default/19.gpio_dout_din_regs_random_rw.1508138073
Short name T300
Test name
Test status
Simulation time 147148729 ps
CPU time 0.83 seconds
Started Apr 18 12:31:14 PM PDT 24
Finished Apr 18 12:31:23 PM PDT 24
Peak memory 196388 kb
Host smart-79c99cfc-fc78-47fb-94b3-d4dad864cb24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1508138073 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_dout_din_regs_random_rw.1508138073
Directory /workspace/19.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/19.gpio_filter_stress.1646602808
Short name T117
Test name
Test status
Simulation time 461885596 ps
CPU time 15.82 seconds
Started Apr 18 12:31:04 PM PDT 24
Finished Apr 18 12:31:26 PM PDT 24
Peak memory 195488 kb
Host smart-f6dc297b-1cbf-4594-a8f2-67a59fe06185
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1646602808 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_filter_stre
ss.1646602808
Directory /workspace/19.gpio_filter_stress/latest

Test location /workspace/coverage/default/19.gpio_full_random.2873639310
Short name T662
Test name
Test status
Simulation time 252366188 ps
CPU time 0.92 seconds
Started Apr 18 12:31:08 PM PDT 24
Finished Apr 18 12:31:16 PM PDT 24
Peak memory 197756 kb
Host smart-ac026125-94e2-4148-972e-8de3ca472dbc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2873639310 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_full_random.2873639310
Directory /workspace/19.gpio_full_random/latest

Test location /workspace/coverage/default/19.gpio_intr_rand_pgm.85057319
Short name T436
Test name
Test status
Simulation time 150657388 ps
CPU time 1.1 seconds
Started Apr 18 12:32:46 PM PDT 24
Finished Apr 18 12:32:48 PM PDT 24
Peak memory 196612 kb
Host smart-8a1d8dac-6625-4b9f-bb8d-3e1c73115c40
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85057319 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_intr_rand_pgm.85057319
Directory /workspace/19.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/19.gpio_intr_with_filter_rand_intr_event.994384996
Short name T376
Test name
Test status
Simulation time 325152143 ps
CPU time 3.18 seconds
Started Apr 18 12:31:02 PM PDT 24
Finished Apr 18 12:31:10 PM PDT 24
Peak memory 198076 kb
Host smart-aef20875-123c-459f-910f-52d72041980c
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=994384996 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 19.gpio_intr_with_filter_rand_intr_event.994384996
Directory /workspace/19.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/19.gpio_rand_intr_trigger.2119365349
Short name T695
Test name
Test status
Simulation time 488074804 ps
CPU time 1.96 seconds
Started Apr 18 12:31:17 PM PDT 24
Finished Apr 18 12:31:22 PM PDT 24
Peak memory 196004 kb
Host smart-35ddcd5f-e6fe-47ac-acf1-759a7c8e2e0f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2119365349 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_rand_intr_trigger
.2119365349
Directory /workspace/19.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/19.gpio_random_dout_din.1790366060
Short name T592
Test name
Test status
Simulation time 69120389 ps
CPU time 0.67 seconds
Started Apr 18 12:31:07 PM PDT 24
Finished Apr 18 12:31:15 PM PDT 24
Peak memory 193972 kb
Host smart-fdb98961-1cd9-4c34-baa4-ba132c9063cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1790366060 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_random_dout_din.1790366060
Directory /workspace/19.gpio_random_dout_din/latest

Test location /workspace/coverage/default/19.gpio_random_dout_din_no_pullup_pulldown.2488383863
Short name T172
Test name
Test status
Simulation time 44562488 ps
CPU time 0.77 seconds
Started Apr 18 12:31:13 PM PDT 24
Finished Apr 18 12:31:19 PM PDT 24
Peak memory 195244 kb
Host smart-ccee53e7-8f17-4453-8170-f48faa666016
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2488383863 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_random_dout_din_no_pullu
p_pulldown.2488383863
Directory /workspace/19.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/19.gpio_random_long_reg_writes_reg_reads.611685605
Short name T17
Test name
Test status
Simulation time 116231204 ps
CPU time 2.06 seconds
Started Apr 18 12:31:11 PM PDT 24
Finished Apr 18 12:31:19 PM PDT 24
Peak memory 197960 kb
Host smart-f8b7ebf2-f703-49cb-b140-99b7f1a6ec15
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=611685605 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_ran
dom_long_reg_writes_reg_reads.611685605
Directory /workspace/19.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/19.gpio_smoke.2934641880
Short name T68
Test name
Test status
Simulation time 431449229 ps
CPU time 1.23 seconds
Started Apr 18 12:31:04 PM PDT 24
Finished Apr 18 12:31:11 PM PDT 24
Peak memory 197144 kb
Host smart-2c36798d-0be5-4a0e-a9eb-d1e9e13b3b95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2934641880 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_smoke.2934641880
Directory /workspace/19.gpio_smoke/latest

Test location /workspace/coverage/default/19.gpio_smoke_no_pullup_pulldown.3967359961
Short name T349
Test name
Test status
Simulation time 43881666 ps
CPU time 1.11 seconds
Started Apr 18 12:31:09 PM PDT 24
Finished Apr 18 12:31:17 PM PDT 24
Peak memory 195864 kb
Host smart-9855f6a1-21bf-4e8b-8d96-1e6c3586c64c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3967359961 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_no_pullup_pulldown.3967359961
Directory /workspace/19.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/19.gpio_stress_all.1660112512
Short name T657
Test name
Test status
Simulation time 48500342090 ps
CPU time 161.33 seconds
Started Apr 18 12:31:02 PM PDT 24
Finished Apr 18 12:33:47 PM PDT 24
Peak memory 198208 kb
Host smart-75178dce-1142-4f6f-b7db-cdcd3b4b492b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1660112512 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.
gpio_stress_all.1660112512
Directory /workspace/19.gpio_stress_all/latest

Test location /workspace/coverage/default/19.gpio_stress_all_with_rand_reset.467467234
Short name T59
Test name
Test status
Simulation time 356567214179 ps
CPU time 1958.5 seconds
Started Apr 18 12:31:10 PM PDT 24
Finished Apr 18 01:03:55 PM PDT 24
Peak memory 198092 kb
Host smart-ccfe8ba3-8f66-49b1-bdcc-ed4c73b53c41
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=467467234 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_stress_all_with_rand_reset.467467234
Directory /workspace/19.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.gpio_alert_test.3407216151
Short name T179
Test name
Test status
Simulation time 22604759 ps
CPU time 0.58 seconds
Started Apr 18 12:30:52 PM PDT 24
Finished Apr 18 12:30:54 PM PDT 24
Peak memory 194852 kb
Host smart-a0c891fb-cf0b-49ab-9efc-c4159089da01
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3407216151 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_alert_test.3407216151
Directory /workspace/2.gpio_alert_test/latest

Test location /workspace/coverage/default/2.gpio_dout_din_regs_random_rw.3938919024
Short name T614
Test name
Test status
Simulation time 118025186 ps
CPU time 0.85 seconds
Started Apr 18 12:30:39 PM PDT 24
Finished Apr 18 12:30:40 PM PDT 24
Peak memory 197304 kb
Host smart-e94e14a4-d149-4dc3-a12d-01e0793f13ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3938919024 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_dout_din_regs_random_rw.3938919024
Directory /workspace/2.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/2.gpio_filter_stress.2701645856
Short name T265
Test name
Test status
Simulation time 368109624 ps
CPU time 9.78 seconds
Started Apr 18 12:30:39 PM PDT 24
Finished Apr 18 12:30:50 PM PDT 24
Peak memory 197924 kb
Host smart-9998c204-6443-4423-bf3d-4a2121b1d6b7
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2701645856 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_filter_stres
s.2701645856
Directory /workspace/2.gpio_filter_stress/latest

Test location /workspace/coverage/default/2.gpio_full_random.2728413521
Short name T476
Test name
Test status
Simulation time 110300682 ps
CPU time 0.65 seconds
Started Apr 18 12:30:34 PM PDT 24
Finished Apr 18 12:30:35 PM PDT 24
Peak memory 194524 kb
Host smart-ee70bdc0-04ac-4197-9b4c-a1b05b1cdc9f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2728413521 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_full_random.2728413521
Directory /workspace/2.gpio_full_random/latest

Test location /workspace/coverage/default/2.gpio_intr_rand_pgm.3989365739
Short name T174
Test name
Test status
Simulation time 77559952 ps
CPU time 1.13 seconds
Started Apr 18 12:30:42 PM PDT 24
Finished Apr 18 12:30:44 PM PDT 24
Peak memory 195872 kb
Host smart-b08ee338-72d0-4591-b999-372188be665a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3989365739 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_intr_rand_pgm.3989365739
Directory /workspace/2.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/2.gpio_intr_with_filter_rand_intr_event.2154109669
Short name T228
Test name
Test status
Simulation time 58062443 ps
CPU time 1.91 seconds
Started Apr 18 12:30:28 PM PDT 24
Finished Apr 18 12:30:31 PM PDT 24
Peak memory 198116 kb
Host smart-97532d05-6c18-4226-8763-d9d0277ba189
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2154109669 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 2.gpio_intr_with_filter_rand_intr_event.2154109669
Directory /workspace/2.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/2.gpio_rand_intr_trigger.4081404528
Short name T579
Test name
Test status
Simulation time 267772208 ps
CPU time 2.14 seconds
Started Apr 18 12:30:39 PM PDT 24
Finished Apr 18 12:30:42 PM PDT 24
Peak memory 195932 kb
Host smart-c26304be-e26c-4f99-bc62-e5c399ef7304
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4081404528 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_rand_intr_trigger.
4081404528
Directory /workspace/2.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/2.gpio_random_dout_din.3315824375
Short name T18
Test name
Test status
Simulation time 84313932 ps
CPU time 1.06 seconds
Started Apr 18 12:31:01 PM PDT 24
Finished Apr 18 12:31:05 PM PDT 24
Peak memory 195920 kb
Host smart-436c7430-fb66-4895-ab33-05869e122bdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3315824375 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_random_dout_din.3315824375
Directory /workspace/2.gpio_random_dout_din/latest

Test location /workspace/coverage/default/2.gpio_random_dout_din_no_pullup_pulldown.4035442156
Short name T328
Test name
Test status
Simulation time 115736193 ps
CPU time 0.67 seconds
Started Apr 18 12:30:26 PM PDT 24
Finished Apr 18 12:30:28 PM PDT 24
Peak memory 196048 kb
Host smart-e56e9b2d-ad14-45f9-9afb-b1d0590f9bee
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4035442156 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_random_dout_din_no_pullup
_pulldown.4035442156
Directory /workspace/2.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/2.gpio_random_long_reg_writes_reg_reads.594797411
Short name T572
Test name
Test status
Simulation time 1682159820 ps
CPU time 5.08 seconds
Started Apr 18 12:30:39 PM PDT 24
Finished Apr 18 12:30:45 PM PDT 24
Peak memory 197916 kb
Host smart-f21c910c-f0c7-4626-b521-c29b977e8d28
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=594797411 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_rand
om_long_reg_writes_reg_reads.594797411
Directory /workspace/2.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/2.gpio_sec_cm.1722089436
Short name T52
Test name
Test status
Simulation time 177225970 ps
CPU time 0.96 seconds
Started Apr 18 12:30:44 PM PDT 24
Finished Apr 18 12:30:46 PM PDT 24
Peak memory 214676 kb
Host smart-b6ae88ab-c3e4-4045-b14c-858aabef4311
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1722089436 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_sec_cm.1722089436
Directory /workspace/2.gpio_sec_cm/latest

Test location /workspace/coverage/default/2.gpio_smoke.3313312673
Short name T263
Test name
Test status
Simulation time 201570879 ps
CPU time 1.06 seconds
Started Apr 18 12:30:25 PM PDT 24
Finished Apr 18 12:30:28 PM PDT 24
Peak memory 195628 kb
Host smart-962aa593-8c0a-4ac7-ad66-a3b2def2c4ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3313312673 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_smoke.3313312673
Directory /workspace/2.gpio_smoke/latest

Test location /workspace/coverage/default/2.gpio_smoke_no_pullup_pulldown.2360357990
Short name T183
Test name
Test status
Simulation time 80983434 ps
CPU time 1.17 seconds
Started Apr 18 12:30:27 PM PDT 24
Finished Apr 18 12:30:35 PM PDT 24
Peak memory 195816 kb
Host smart-c193ddf5-8818-4e45-aeef-c14675973079
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2360357990 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_no_pullup_pulldown.2360357990
Directory /workspace/2.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/2.gpio_stress_all.2523468491
Short name T186
Test name
Test status
Simulation time 4404324156 ps
CPU time 67.87 seconds
Started Apr 18 12:30:29 PM PDT 24
Finished Apr 18 12:31:38 PM PDT 24
Peak memory 198040 kb
Host smart-c3011fe4-bd67-47ac-a5e7-af9a6c54177a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2523468491 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.g
pio_stress_all.2523468491
Directory /workspace/2.gpio_stress_all/latest

Test location /workspace/coverage/default/20.gpio_alert_test.538638580
Short name T560
Test name
Test status
Simulation time 40761921 ps
CPU time 0.55 seconds
Started Apr 18 12:31:12 PM PDT 24
Finished Apr 18 12:31:18 PM PDT 24
Peak memory 194520 kb
Host smart-d6933c80-36fe-47a2-8620-f381f718f78c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=538638580 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_alert_test.538638580
Directory /workspace/20.gpio_alert_test/latest

Test location /workspace/coverage/default/20.gpio_dout_din_regs_random_rw.1492991905
Short name T475
Test name
Test status
Simulation time 37297408 ps
CPU time 0.64 seconds
Started Apr 18 12:31:16 PM PDT 24
Finished Apr 18 12:31:20 PM PDT 24
Peak memory 193764 kb
Host smart-d6f49378-4da7-4fff-8cb2-ede12800f178
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1492991905 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_dout_din_regs_random_rw.1492991905
Directory /workspace/20.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/20.gpio_filter_stress.2589374775
Short name T571
Test name
Test status
Simulation time 724073607 ps
CPU time 26.23 seconds
Started Apr 18 12:31:02 PM PDT 24
Finished Apr 18 12:31:35 PM PDT 24
Peak memory 196796 kb
Host smart-f00ec8db-fae0-4d70-ab88-ec591c29f171
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2589374775 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_filter_stre
ss.2589374775
Directory /workspace/20.gpio_filter_stress/latest

Test location /workspace/coverage/default/20.gpio_full_random.3569876025
Short name T302
Test name
Test status
Simulation time 32320081 ps
CPU time 0.65 seconds
Started Apr 18 12:31:26 PM PDT 24
Finished Apr 18 12:31:28 PM PDT 24
Peak memory 195480 kb
Host smart-ba8f2814-24c1-4952-ada5-7e3d9ad747ff
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3569876025 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_full_random.3569876025
Directory /workspace/20.gpio_full_random/latest

Test location /workspace/coverage/default/20.gpio_intr_rand_pgm.3564907474
Short name T250
Test name
Test status
Simulation time 119185078 ps
CPU time 1.01 seconds
Started Apr 18 12:30:57 PM PDT 24
Finished Apr 18 12:30:59 PM PDT 24
Peak memory 196756 kb
Host smart-85495e9c-8835-463a-9d01-16d96146d6fa
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3564907474 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_intr_rand_pgm.3564907474
Directory /workspace/20.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/20.gpio_intr_with_filter_rand_intr_event.219734447
Short name T286
Test name
Test status
Simulation time 87375137 ps
CPU time 3.1 seconds
Started Apr 18 12:31:06 PM PDT 24
Finished Apr 18 12:31:17 PM PDT 24
Peak memory 196452 kb
Host smart-ba35580d-f4b5-42be-ba77-37072e1f3240
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=219734447 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 20.gpio_intr_with_filter_rand_intr_event.219734447
Directory /workspace/20.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/20.gpio_rand_intr_trigger.1402478209
Short name T359
Test name
Test status
Simulation time 111563225 ps
CPU time 0.86 seconds
Started Apr 18 12:31:11 PM PDT 24
Finished Apr 18 12:31:18 PM PDT 24
Peak memory 194380 kb
Host smart-9cc68d23-f2e9-4c2d-aac7-1546f594cb98
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1402478209 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_rand_intr_trigger
.1402478209
Directory /workspace/20.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/20.gpio_random_dout_din.4074329240
Short name T513
Test name
Test status
Simulation time 33443357 ps
CPU time 1.11 seconds
Started Apr 18 12:31:18 PM PDT 24
Finished Apr 18 12:31:22 PM PDT 24
Peak memory 195940 kb
Host smart-8dc300e9-7491-4627-b126-41e68fcd528f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4074329240 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_random_dout_din.4074329240
Directory /workspace/20.gpio_random_dout_din/latest

Test location /workspace/coverage/default/20.gpio_random_dout_din_no_pullup_pulldown.3032233091
Short name T281
Test name
Test status
Simulation time 45583770 ps
CPU time 0.96 seconds
Started Apr 18 12:31:07 PM PDT 24
Finished Apr 18 12:31:15 PM PDT 24
Peak memory 195788 kb
Host smart-086ddf53-ce31-4efc-a7a1-9eb398fe0d1c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3032233091 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_random_dout_din_no_pullu
p_pulldown.3032233091
Directory /workspace/20.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/20.gpio_random_long_reg_writes_reg_reads.286366288
Short name T692
Test name
Test status
Simulation time 54785751 ps
CPU time 2.27 seconds
Started Apr 18 12:31:14 PM PDT 24
Finished Apr 18 12:31:20 PM PDT 24
Peak memory 197700 kb
Host smart-71d45c5c-66f7-4949-b416-0b9638da7a0a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=286366288 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_ran
dom_long_reg_writes_reg_reads.286366288
Directory /workspace/20.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/20.gpio_smoke.420829035
Short name T175
Test name
Test status
Simulation time 72304073 ps
CPU time 1.28 seconds
Started Apr 18 12:31:02 PM PDT 24
Finished Apr 18 12:31:06 PM PDT 24
Peak memory 197972 kb
Host smart-897766d9-f8d6-4087-b139-fb7efc1252b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=420829035 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_smoke.420829035
Directory /workspace/20.gpio_smoke/latest

Test location /workspace/coverage/default/20.gpio_smoke_no_pullup_pulldown.3576330575
Short name T622
Test name
Test status
Simulation time 132984938 ps
CPU time 1.15 seconds
Started Apr 18 12:31:15 PM PDT 24
Finished Apr 18 12:31:20 PM PDT 24
Peak memory 195880 kb
Host smart-ea29fd43-87cd-4dc9-993b-7257290a8611
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3576330575 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_no_pullup_pulldown.3576330575
Directory /workspace/20.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/20.gpio_stress_all.1020401645
Short name T160
Test name
Test status
Simulation time 2721799343 ps
CPU time 67.21 seconds
Started Apr 18 12:30:57 PM PDT 24
Finished Apr 18 12:32:05 PM PDT 24
Peak memory 198072 kb
Host smart-6cef9567-5a8a-43ea-bd5f-cad76a789a84
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1020401645 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.
gpio_stress_all.1020401645
Directory /workspace/20.gpio_stress_all/latest

Test location /workspace/coverage/default/20.gpio_stress_all_with_rand_reset.2344510372
Short name T55
Test name
Test status
Simulation time 25939934513 ps
CPU time 443.12 seconds
Started Apr 18 12:31:04 PM PDT 24
Finished Apr 18 12:38:34 PM PDT 24
Peak memory 198168 kb
Host smart-bc203036-464c-45a4-af73-45a9b702a951
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2344510372 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_stress_all_with_rand_reset.2344510372
Directory /workspace/20.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.gpio_alert_test.15937916
Short name T636
Test name
Test status
Simulation time 26583991 ps
CPU time 0.58 seconds
Started Apr 18 12:31:16 PM PDT 24
Finished Apr 18 12:31:20 PM PDT 24
Peak memory 194764 kb
Host smart-b704ff56-6bd6-4ca6-aa29-c479227340c4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15937916 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_alert_test.15937916
Directory /workspace/21.gpio_alert_test/latest

Test location /workspace/coverage/default/21.gpio_dout_din_regs_random_rw.1905398474
Short name T366
Test name
Test status
Simulation time 43172982 ps
CPU time 0.73 seconds
Started Apr 18 12:32:29 PM PDT 24
Finished Apr 18 12:32:31 PM PDT 24
Peak memory 195264 kb
Host smart-c892b3fc-1f66-45a0-81b6-2b431edab315
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1905398474 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_dout_din_regs_random_rw.1905398474
Directory /workspace/21.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/21.gpio_filter_stress.1915762122
Short name T241
Test name
Test status
Simulation time 570135587 ps
CPU time 6.49 seconds
Started Apr 18 12:32:25 PM PDT 24
Finished Apr 18 12:32:32 PM PDT 24
Peak memory 196680 kb
Host smart-1349ea59-56b3-40e2-b1a4-c4f94b818b7d
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1915762122 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_filter_stre
ss.1915762122
Directory /workspace/21.gpio_filter_stress/latest

Test location /workspace/coverage/default/21.gpio_full_random.829410812
Short name T556
Test name
Test status
Simulation time 215603375 ps
CPU time 0.86 seconds
Started Apr 18 12:31:11 PM PDT 24
Finished Apr 18 12:31:18 PM PDT 24
Peak memory 196556 kb
Host smart-8f7b961d-25c1-406e-8308-58d8858ee9fb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=829410812 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_full_random.829410812
Directory /workspace/21.gpio_full_random/latest

Test location /workspace/coverage/default/21.gpio_intr_rand_pgm.1200176859
Short name T358
Test name
Test status
Simulation time 74483255 ps
CPU time 0.87 seconds
Started Apr 18 12:31:15 PM PDT 24
Finished Apr 18 12:31:20 PM PDT 24
Peak memory 196288 kb
Host smart-49c00900-71f9-40e9-a1d4-89b6bc288821
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1200176859 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_intr_rand_pgm.1200176859
Directory /workspace/21.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/21.gpio_intr_with_filter_rand_intr_event.3043782960
Short name T122
Test name
Test status
Simulation time 54669250 ps
CPU time 1.27 seconds
Started Apr 18 12:31:06 PM PDT 24
Finished Apr 18 12:31:13 PM PDT 24
Peak memory 196884 kb
Host smart-b5a167cf-5350-46ea-b93d-605f9cd790d2
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3043782960 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 21.gpio_intr_with_filter_rand_intr_event.3043782960
Directory /workspace/21.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/21.gpio_rand_intr_trigger.3685633534
Short name T643
Test name
Test status
Simulation time 130212494 ps
CPU time 2.42 seconds
Started Apr 18 12:31:05 PM PDT 24
Finished Apr 18 12:31:14 PM PDT 24
Peak memory 198028 kb
Host smart-16335fa8-243d-4993-b216-18229d42db31
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3685633534 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_rand_intr_trigger
.3685633534
Directory /workspace/21.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/21.gpio_random_dout_din.1276909532
Short name T415
Test name
Test status
Simulation time 28585558 ps
CPU time 1.09 seconds
Started Apr 18 12:31:05 PM PDT 24
Finished Apr 18 12:31:13 PM PDT 24
Peak memory 196076 kb
Host smart-59499eb7-5775-4eee-a738-b6188d134447
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1276909532 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_random_dout_din.1276909532
Directory /workspace/21.gpio_random_dout_din/latest

Test location /workspace/coverage/default/21.gpio_random_dout_din_no_pullup_pulldown.2921908055
Short name T317
Test name
Test status
Simulation time 103262959 ps
CPU time 0.79 seconds
Started Apr 18 12:31:20 PM PDT 24
Finished Apr 18 12:31:23 PM PDT 24
Peak memory 195508 kb
Host smart-be371b93-a6a1-4324-ac3c-c5111a7d4d37
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2921908055 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_random_dout_din_no_pullu
p_pulldown.2921908055
Directory /workspace/21.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/21.gpio_random_long_reg_writes_reg_reads.1053600230
Short name T446
Test name
Test status
Simulation time 115015678 ps
CPU time 2.07 seconds
Started Apr 18 12:31:15 PM PDT 24
Finished Apr 18 12:31:21 PM PDT 24
Peak memory 198116 kb
Host smart-e1ac8249-1527-4f84-8c7e-880d5053679f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1053600230 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_ra
ndom_long_reg_writes_reg_reads.1053600230
Directory /workspace/21.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/21.gpio_smoke.1113049545
Short name T568
Test name
Test status
Simulation time 50674008 ps
CPU time 0.94 seconds
Started Apr 18 12:31:06 PM PDT 24
Finished Apr 18 12:31:13 PM PDT 24
Peak memory 197200 kb
Host smart-f1df0413-e1b1-44b8-b8e1-acc9b848d163
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1113049545 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_smoke.1113049545
Directory /workspace/21.gpio_smoke/latest

Test location /workspace/coverage/default/21.gpio_smoke_no_pullup_pulldown.4063498347
Short name T618
Test name
Test status
Simulation time 95769772 ps
CPU time 0.99 seconds
Started Apr 18 12:31:14 PM PDT 24
Finished Apr 18 12:31:19 PM PDT 24
Peak memory 195852 kb
Host smart-8a64fa26-64b6-416b-aa4d-202d21776a28
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4063498347 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_no_pullup_pulldown.4063498347
Directory /workspace/21.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/21.gpio_stress_all.3267514894
Short name T664
Test name
Test status
Simulation time 2496649850 ps
CPU time 62.33 seconds
Started Apr 18 12:31:07 PM PDT 24
Finished Apr 18 12:32:17 PM PDT 24
Peak memory 198084 kb
Host smart-348351a2-d902-4212-93ab-4f940cb4ef05
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3267514894 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.
gpio_stress_all.3267514894
Directory /workspace/21.gpio_stress_all/latest

Test location /workspace/coverage/default/22.gpio_alert_test.877474409
Short name T185
Test name
Test status
Simulation time 38098140 ps
CPU time 0.57 seconds
Started Apr 18 12:31:02 PM PDT 24
Finished Apr 18 12:31:05 PM PDT 24
Peak memory 194488 kb
Host smart-45ccfa6d-08ba-4d20-90c2-d77db2eadf6d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=877474409 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_alert_test.877474409
Directory /workspace/22.gpio_alert_test/latest

Test location /workspace/coverage/default/22.gpio_dout_din_regs_random_rw.2842750109
Short name T616
Test name
Test status
Simulation time 71465761 ps
CPU time 0.78 seconds
Started Apr 18 12:31:02 PM PDT 24
Finished Apr 18 12:31:07 PM PDT 24
Peak memory 196048 kb
Host smart-66ae9e55-4be5-4356-b041-2d17397d9b22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2842750109 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_dout_din_regs_random_rw.2842750109
Directory /workspace/22.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/22.gpio_filter_stress.708283308
Short name T311
Test name
Test status
Simulation time 4619828890 ps
CPU time 23.32 seconds
Started Apr 18 12:31:17 PM PDT 24
Finished Apr 18 12:31:44 PM PDT 24
Peak memory 198028 kb
Host smart-430a5508-2bc9-446b-b9b5-e03008972e80
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=708283308 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_filter_stres
s.708283308
Directory /workspace/22.gpio_filter_stress/latest

Test location /workspace/coverage/default/22.gpio_full_random.2134908853
Short name T157
Test name
Test status
Simulation time 18805282 ps
CPU time 0.6 seconds
Started Apr 18 12:31:17 PM PDT 24
Finished Apr 18 12:31:21 PM PDT 24
Peak memory 194340 kb
Host smart-60790a07-3570-47d4-89a7-945797cef7c8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2134908853 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_full_random.2134908853
Directory /workspace/22.gpio_full_random/latest

Test location /workspace/coverage/default/22.gpio_intr_rand_pgm.2172178535
Short name T414
Test name
Test status
Simulation time 73235044 ps
CPU time 1.02 seconds
Started Apr 18 12:31:10 PM PDT 24
Finished Apr 18 12:31:18 PM PDT 24
Peak memory 196016 kb
Host smart-d25ba250-fa66-4214-bca8-58873895d1ad
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2172178535 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_intr_rand_pgm.2172178535
Directory /workspace/22.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/22.gpio_intr_with_filter_rand_intr_event.1246583236
Short name T566
Test name
Test status
Simulation time 37711197 ps
CPU time 0.91 seconds
Started Apr 18 12:31:13 PM PDT 24
Finished Apr 18 12:31:19 PM PDT 24
Peak memory 196052 kb
Host smart-aeaeec4b-87de-4f19-a60f-fe86e94952a1
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1246583236 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 22.gpio_intr_with_filter_rand_intr_event.1246583236
Directory /workspace/22.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/22.gpio_rand_intr_trigger.4072387635
Short name T141
Test name
Test status
Simulation time 413424112 ps
CPU time 1.99 seconds
Started Apr 18 12:31:04 PM PDT 24
Finished Apr 18 12:31:11 PM PDT 24
Peak memory 196184 kb
Host smart-f5ac080d-ce96-4081-8764-23a4e014525f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4072387635 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_rand_intr_trigger
.4072387635
Directory /workspace/22.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/22.gpio_random_dout_din.1557895445
Short name T120
Test name
Test status
Simulation time 23879875 ps
CPU time 0.64 seconds
Started Apr 18 12:31:21 PM PDT 24
Finished Apr 18 12:31:24 PM PDT 24
Peak memory 194240 kb
Host smart-72475002-cff8-4288-8911-d29c6dcf836c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1557895445 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_random_dout_din.1557895445
Directory /workspace/22.gpio_random_dout_din/latest

Test location /workspace/coverage/default/22.gpio_random_dout_din_no_pullup_pulldown.3235464740
Short name T362
Test name
Test status
Simulation time 109124976 ps
CPU time 0.87 seconds
Started Apr 18 12:31:05 PM PDT 24
Finished Apr 18 12:31:12 PM PDT 24
Peak memory 196376 kb
Host smart-d3167bad-c221-48bf-9e03-0142bfaf1327
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3235464740 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_random_dout_din_no_pullu
p_pulldown.3235464740
Directory /workspace/22.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/22.gpio_random_long_reg_writes_reg_reads.127490766
Short name T508
Test name
Test status
Simulation time 101449182 ps
CPU time 1.6 seconds
Started Apr 18 12:31:05 PM PDT 24
Finished Apr 18 12:31:12 PM PDT 24
Peak memory 198008 kb
Host smart-c045f1cd-bca1-4799-991f-d40dc143beb5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=127490766 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_ran
dom_long_reg_writes_reg_reads.127490766
Directory /workspace/22.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/22.gpio_smoke.1893417574
Short name T505
Test name
Test status
Simulation time 32020097 ps
CPU time 0.98 seconds
Started Apr 18 12:31:33 PM PDT 24
Finished Apr 18 12:31:34 PM PDT 24
Peak memory 195700 kb
Host smart-841ea5c6-a342-4709-9c0d-749b132925c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1893417574 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_smoke.1893417574
Directory /workspace/22.gpio_smoke/latest

Test location /workspace/coverage/default/22.gpio_smoke_no_pullup_pulldown.713409056
Short name T288
Test name
Test status
Simulation time 1328520723 ps
CPU time 1.32 seconds
Started Apr 18 12:31:04 PM PDT 24
Finished Apr 18 12:31:10 PM PDT 24
Peak memory 195516 kb
Host smart-9a24217b-a64d-464a-88f6-2705bcf0a41e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=713409056 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_no_pullup_pulldown.713409056
Directory /workspace/22.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/22.gpio_stress_all.1014112525
Short name T482
Test name
Test status
Simulation time 22543418667 ps
CPU time 119.33 seconds
Started Apr 18 12:31:05 PM PDT 24
Finished Apr 18 12:33:11 PM PDT 24
Peak memory 197968 kb
Host smart-fab37c21-9778-480e-85b6-91a29765ee23
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1014112525 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.
gpio_stress_all.1014112525
Directory /workspace/22.gpio_stress_all/latest

Test location /workspace/coverage/default/22.gpio_stress_all_with_rand_reset.2639999386
Short name T671
Test name
Test status
Simulation time 1140673947511 ps
CPU time 753.45 seconds
Started Apr 18 12:31:02 PM PDT 24
Finished Apr 18 12:43:40 PM PDT 24
Peak memory 198140 kb
Host smart-780d771f-eeb8-4293-8a7e-458ecc9ffe10
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2639999386 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_stress_all_with_rand_reset.2639999386
Directory /workspace/22.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.gpio_alert_test.1397230682
Short name T155
Test name
Test status
Simulation time 11083405 ps
CPU time 0.55 seconds
Started Apr 18 12:31:19 PM PDT 24
Finished Apr 18 12:31:23 PM PDT 24
Peak memory 193832 kb
Host smart-b0dc2f89-c232-4121-8a84-65de90eca923
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1397230682 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_alert_test.1397230682
Directory /workspace/23.gpio_alert_test/latest

Test location /workspace/coverage/default/23.gpio_dout_din_regs_random_rw.3944101421
Short name T447
Test name
Test status
Simulation time 69948899 ps
CPU time 0.66 seconds
Started Apr 18 12:31:25 PM PDT 24
Finished Apr 18 12:31:27 PM PDT 24
Peak memory 194792 kb
Host smart-c80d7c37-5d41-40a9-889c-ccefe3fd5ab9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3944101421 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_dout_din_regs_random_rw.3944101421
Directory /workspace/23.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/23.gpio_filter_stress.772562997
Short name T608
Test name
Test status
Simulation time 167899499 ps
CPU time 8.72 seconds
Started Apr 18 12:31:18 PM PDT 24
Finished Apr 18 12:31:30 PM PDT 24
Peak memory 196852 kb
Host smart-e18d4689-bb42-45a7-8d9e-1d39770db437
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=772562997 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_filter_stres
s.772562997
Directory /workspace/23.gpio_filter_stress/latest

Test location /workspace/coverage/default/23.gpio_full_random.3845640423
Short name T470
Test name
Test status
Simulation time 83133209 ps
CPU time 0.96 seconds
Started Apr 18 12:31:17 PM PDT 24
Finished Apr 18 12:31:22 PM PDT 24
Peak memory 197684 kb
Host smart-72d7216b-cfd0-4e5f-91bc-3f174a41bc9c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3845640423 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_full_random.3845640423
Directory /workspace/23.gpio_full_random/latest

Test location /workspace/coverage/default/23.gpio_intr_rand_pgm.2113039995
Short name T187
Test name
Test status
Simulation time 164903490 ps
CPU time 1.46 seconds
Started Apr 18 12:31:20 PM PDT 24
Finished Apr 18 12:31:25 PM PDT 24
Peak memory 197980 kb
Host smart-f28d33f2-a98f-48f8-b115-bd574afb6cdb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2113039995 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_intr_rand_pgm.2113039995
Directory /workspace/23.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/23.gpio_intr_with_filter_rand_intr_event.3059935023
Short name T646
Test name
Test status
Simulation time 157765827 ps
CPU time 1.89 seconds
Started Apr 18 12:31:06 PM PDT 24
Finished Apr 18 12:31:15 PM PDT 24
Peak memory 196308 kb
Host smart-948d57ca-dd83-45e9-ab1d-7157dda9d617
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3059935023 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 23.gpio_intr_with_filter_rand_intr_event.3059935023
Directory /workspace/23.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/23.gpio_rand_intr_trigger.2554504911
Short name T132
Test name
Test status
Simulation time 234600997 ps
CPU time 3.35 seconds
Started Apr 18 12:31:05 PM PDT 24
Finished Apr 18 12:31:14 PM PDT 24
Peak memory 198044 kb
Host smart-f6d027d8-0981-46f1-80e0-da250b1f0a27
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2554504911 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_rand_intr_trigger
.2554504911
Directory /workspace/23.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/23.gpio_random_dout_din.3673053117
Short name T191
Test name
Test status
Simulation time 72599713 ps
CPU time 1.28 seconds
Started Apr 18 12:31:16 PM PDT 24
Finished Apr 18 12:31:21 PM PDT 24
Peak memory 197072 kb
Host smart-e18fc6e5-0765-405e-ad77-177fcd0e9d79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3673053117 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_random_dout_din.3673053117
Directory /workspace/23.gpio_random_dout_din/latest

Test location /workspace/coverage/default/23.gpio_random_dout_din_no_pullup_pulldown.1656086882
Short name T703
Test name
Test status
Simulation time 20118453 ps
CPU time 0.64 seconds
Started Apr 18 12:31:07 PM PDT 24
Finished Apr 18 12:31:15 PM PDT 24
Peak memory 194196 kb
Host smart-7e381f69-7d21-4a27-afe0-83097871a73e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1656086882 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_random_dout_din_no_pullu
p_pulldown.1656086882
Directory /workspace/23.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/23.gpio_random_long_reg_writes_reg_reads.1628910762
Short name T14
Test name
Test status
Simulation time 836355783 ps
CPU time 4.85 seconds
Started Apr 18 12:31:18 PM PDT 24
Finished Apr 18 12:31:26 PM PDT 24
Peak memory 197936 kb
Host smart-a6743ddd-b8e8-4863-966a-d6c068f9bf17
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1628910762 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_ra
ndom_long_reg_writes_reg_reads.1628910762
Directory /workspace/23.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/23.gpio_smoke.3578627185
Short name T124
Test name
Test status
Simulation time 31077332 ps
CPU time 0.94 seconds
Started Apr 18 12:31:19 PM PDT 24
Finished Apr 18 12:31:23 PM PDT 24
Peak memory 195880 kb
Host smart-925669c8-d21f-4c92-8eb6-299fea071d2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3578627185 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_smoke.3578627185
Directory /workspace/23.gpio_smoke/latest

Test location /workspace/coverage/default/23.gpio_smoke_no_pullup_pulldown.1893531592
Short name T71
Test name
Test status
Simulation time 59625291 ps
CPU time 1.03 seconds
Started Apr 18 12:30:58 PM PDT 24
Finished Apr 18 12:31:01 PM PDT 24
Peak memory 196504 kb
Host smart-e1b1a216-16d8-4f48-b2ca-e2ed335e0333
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1893531592 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_no_pullup_pulldown.1893531592
Directory /workspace/23.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/23.gpio_stress_all.3348365854
Short name T606
Test name
Test status
Simulation time 3285623505 ps
CPU time 37.16 seconds
Started Apr 18 12:31:06 PM PDT 24
Finished Apr 18 12:31:51 PM PDT 24
Peak memory 198080 kb
Host smart-860ea559-a69a-4a58-9a52-a2d2822490ee
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3348365854 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.
gpio_stress_all.3348365854
Directory /workspace/23.gpio_stress_all/latest

Test location /workspace/coverage/default/24.gpio_alert_test.1055451042
Short name T27
Test name
Test status
Simulation time 12336373 ps
CPU time 0.57 seconds
Started Apr 18 12:31:18 PM PDT 24
Finished Apr 18 12:31:22 PM PDT 24
Peak memory 194544 kb
Host smart-41ae1ad5-3744-4a96-b9b8-91f4f0ae2d67
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1055451042 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_alert_test.1055451042
Directory /workspace/24.gpio_alert_test/latest

Test location /workspace/coverage/default/24.gpio_dout_din_regs_random_rw.1462314112
Short name T106
Test name
Test status
Simulation time 103186759 ps
CPU time 0.76 seconds
Started Apr 18 12:31:02 PM PDT 24
Finished Apr 18 12:31:06 PM PDT 24
Peak memory 194140 kb
Host smart-5a1fe45e-4a68-47cc-8696-8730c62fe59a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1462314112 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_dout_din_regs_random_rw.1462314112
Directory /workspace/24.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/24.gpio_filter_stress.2964475919
Short name T324
Test name
Test status
Simulation time 1162191839 ps
CPU time 9.53 seconds
Started Apr 18 12:31:05 PM PDT 24
Finished Apr 18 12:31:20 PM PDT 24
Peak memory 196708 kb
Host smart-e5d9f335-34e1-45cb-9fcf-940b953a3aee
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2964475919 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_filter_stre
ss.2964475919
Directory /workspace/24.gpio_filter_stress/latest

Test location /workspace/coverage/default/24.gpio_full_random.1890525312
Short name T597
Test name
Test status
Simulation time 16791391 ps
CPU time 0.63 seconds
Started Apr 18 12:31:25 PM PDT 24
Finished Apr 18 12:31:27 PM PDT 24
Peak memory 195176 kb
Host smart-fa4d9549-2a62-42f2-b5ca-8f39eb794f46
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1890525312 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_full_random.1890525312
Directory /workspace/24.gpio_full_random/latest

Test location /workspace/coverage/default/24.gpio_intr_rand_pgm.785716184
Short name T531
Test name
Test status
Simulation time 90015921 ps
CPU time 1.21 seconds
Started Apr 18 12:31:35 PM PDT 24
Finished Apr 18 12:31:37 PM PDT 24
Peak memory 197012 kb
Host smart-4eb64a19-8d36-444f-b190-2e3170456d92
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=785716184 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_intr_rand_pgm.785716184
Directory /workspace/24.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/24.gpio_intr_with_filter_rand_intr_event.1393102605
Short name T624
Test name
Test status
Simulation time 97725971 ps
CPU time 3.54 seconds
Started Apr 18 12:31:03 PM PDT 24
Finished Apr 18 12:31:12 PM PDT 24
Peak memory 198024 kb
Host smart-838818a4-3e5e-443e-9d5c-68bf7991ace5
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1393102605 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 24.gpio_intr_with_filter_rand_intr_event.1393102605
Directory /workspace/24.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/24.gpio_rand_intr_trigger.3335959859
Short name T666
Test name
Test status
Simulation time 222534411 ps
CPU time 1.24 seconds
Started Apr 18 12:31:05 PM PDT 24
Finished Apr 18 12:31:13 PM PDT 24
Peak memory 196744 kb
Host smart-e218c7e1-bc43-495e-afa0-be682bec1fdd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3335959859 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_rand_intr_trigger
.3335959859
Directory /workspace/24.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/24.gpio_random_dout_din.896136544
Short name T381
Test name
Test status
Simulation time 26446698 ps
CPU time 0.77 seconds
Started Apr 18 12:31:19 PM PDT 24
Finished Apr 18 12:31:23 PM PDT 24
Peak memory 195376 kb
Host smart-535a06a1-880c-4347-8a63-8b42de838ac7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=896136544 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_random_dout_din.896136544
Directory /workspace/24.gpio_random_dout_din/latest

Test location /workspace/coverage/default/24.gpio_random_dout_din_no_pullup_pulldown.130778231
Short name T387
Test name
Test status
Simulation time 121559659 ps
CPU time 1.14 seconds
Started Apr 18 12:31:04 PM PDT 24
Finished Apr 18 12:31:10 PM PDT 24
Peak memory 198052 kb
Host smart-ff4c69f0-666f-4a65-837d-f78d6b73cf74
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=130778231 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_random_dout_din_no_pullup
_pulldown.130778231
Directory /workspace/24.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/24.gpio_random_long_reg_writes_reg_reads.381398166
Short name T569
Test name
Test status
Simulation time 448991011 ps
CPU time 3.62 seconds
Started Apr 18 12:31:06 PM PDT 24
Finished Apr 18 12:31:17 PM PDT 24
Peak memory 197948 kb
Host smart-3269387f-8c8d-4970-b929-6ca06ac111c3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=381398166 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_ran
dom_long_reg_writes_reg_reads.381398166
Directory /workspace/24.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/24.gpio_smoke.1873292537
Short name T220
Test name
Test status
Simulation time 164838457 ps
CPU time 1.11 seconds
Started Apr 18 12:31:14 PM PDT 24
Finished Apr 18 12:31:19 PM PDT 24
Peak memory 196416 kb
Host smart-2a64b80f-d843-4512-b3b8-764190299998
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1873292537 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_smoke.1873292537
Directory /workspace/24.gpio_smoke/latest

Test location /workspace/coverage/default/24.gpio_smoke_no_pullup_pulldown.786213317
Short name T347
Test name
Test status
Simulation time 399881527 ps
CPU time 1.4 seconds
Started Apr 18 12:31:15 PM PDT 24
Finished Apr 18 12:31:21 PM PDT 24
Peak memory 195480 kb
Host smart-ec474a80-9df6-4e5d-868e-f4edc4eb85b6
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=786213317 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_no_pullup_pulldown.786213317
Directory /workspace/24.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/24.gpio_stress_all.3688332536
Short name T573
Test name
Test status
Simulation time 8481548312 ps
CPU time 203.44 seconds
Started Apr 18 12:31:17 PM PDT 24
Finished Apr 18 12:34:44 PM PDT 24
Peak memory 198040 kb
Host smart-d4fd736b-a2cb-4162-9fc9-54277f6328e9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3688332536 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.
gpio_stress_all.3688332536
Directory /workspace/24.gpio_stress_all/latest

Test location /workspace/coverage/default/25.gpio_alert_test.796265683
Short name T353
Test name
Test status
Simulation time 16554908 ps
CPU time 0.56 seconds
Started Apr 18 12:31:20 PM PDT 24
Finished Apr 18 12:31:23 PM PDT 24
Peak memory 193824 kb
Host smart-5873c6fb-527e-4df8-91da-230ebe1c85d2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=796265683 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_alert_test.796265683
Directory /workspace/25.gpio_alert_test/latest

Test location /workspace/coverage/default/25.gpio_dout_din_regs_random_rw.46221947
Short name T284
Test name
Test status
Simulation time 161628586 ps
CPU time 0.85 seconds
Started Apr 18 12:31:17 PM PDT 24
Finished Apr 18 12:31:22 PM PDT 24
Peak memory 195280 kb
Host smart-43f5f52b-9552-4a77-ba6c-7e59c811f7a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=46221947 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_dout_din_regs_random_rw.46221947
Directory /workspace/25.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/25.gpio_filter_stress.3231480617
Short name T396
Test name
Test status
Simulation time 1232504042 ps
CPU time 26.76 seconds
Started Apr 18 12:31:27 PM PDT 24
Finished Apr 18 12:31:54 PM PDT 24
Peak memory 195700 kb
Host smart-6d5b866c-7d10-48af-b15c-327bad4648c9
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3231480617 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_filter_stre
ss.3231480617
Directory /workspace/25.gpio_filter_stress/latest

Test location /workspace/coverage/default/25.gpio_full_random.3617676499
Short name T8
Test name
Test status
Simulation time 307848685 ps
CPU time 0.97 seconds
Started Apr 18 12:31:19 PM PDT 24
Finished Apr 18 12:31:23 PM PDT 24
Peak memory 197340 kb
Host smart-d9e1ba23-6f5a-4ca4-8c01-32450fa29f07
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3617676499 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_full_random.3617676499
Directory /workspace/25.gpio_full_random/latest

Test location /workspace/coverage/default/25.gpio_intr_rand_pgm.227714434
Short name T634
Test name
Test status
Simulation time 101468239 ps
CPU time 1.4 seconds
Started Apr 18 12:31:20 PM PDT 24
Finished Apr 18 12:31:24 PM PDT 24
Peak memory 195768 kb
Host smart-c06b97de-c45e-4f43-8583-c858c8d16379
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=227714434 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_intr_rand_pgm.227714434
Directory /workspace/25.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/25.gpio_intr_with_filter_rand_intr_event.1812212339
Short name T430
Test name
Test status
Simulation time 57125123 ps
CPU time 2.14 seconds
Started Apr 18 12:31:18 PM PDT 24
Finished Apr 18 12:31:24 PM PDT 24
Peak memory 196496 kb
Host smart-cbef2de0-ef49-43c1-bf03-a31bff1f1989
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1812212339 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 25.gpio_intr_with_filter_rand_intr_event.1812212339
Directory /workspace/25.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/25.gpio_rand_intr_trigger.2458117464
Short name T444
Test name
Test status
Simulation time 177829037 ps
CPU time 2.07 seconds
Started Apr 18 12:31:17 PM PDT 24
Finished Apr 18 12:31:23 PM PDT 24
Peak memory 196080 kb
Host smart-905461db-5229-466f-abf6-5671fe49c7d3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2458117464 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_rand_intr_trigger
.2458117464
Directory /workspace/25.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/25.gpio_random_dout_din.2071035428
Short name T433
Test name
Test status
Simulation time 122858128 ps
CPU time 1.1 seconds
Started Apr 18 12:31:13 PM PDT 24
Finished Apr 18 12:31:19 PM PDT 24
Peak memory 196752 kb
Host smart-b16db845-656e-4e20-ae66-da22bb1915f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2071035428 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_random_dout_din.2071035428
Directory /workspace/25.gpio_random_dout_din/latest

Test location /workspace/coverage/default/25.gpio_random_dout_din_no_pullup_pulldown.3155204561
Short name T462
Test name
Test status
Simulation time 102609476 ps
CPU time 1.2 seconds
Started Apr 18 12:31:34 PM PDT 24
Finished Apr 18 12:31:36 PM PDT 24
Peak memory 196960 kb
Host smart-6f5a27d3-1bb3-4943-9779-c77c95542eb4
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3155204561 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_random_dout_din_no_pullu
p_pulldown.3155204561
Directory /workspace/25.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/25.gpio_random_long_reg_writes_reg_reads.2056643404
Short name T660
Test name
Test status
Simulation time 57396510 ps
CPU time 1.22 seconds
Started Apr 18 12:31:25 PM PDT 24
Finished Apr 18 12:31:27 PM PDT 24
Peak memory 197824 kb
Host smart-fbaff9af-e151-4517-932d-496694ca966a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2056643404 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_ra
ndom_long_reg_writes_reg_reads.2056643404
Directory /workspace/25.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/25.gpio_smoke.2823024012
Short name T22
Test name
Test status
Simulation time 25532516 ps
CPU time 0.84 seconds
Started Apr 18 12:31:20 PM PDT 24
Finished Apr 18 12:31:24 PM PDT 24
Peak memory 196416 kb
Host smart-0c9839e7-7bd3-469b-8ea0-721fbe6118df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2823024012 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_smoke.2823024012
Directory /workspace/25.gpio_smoke/latest

Test location /workspace/coverage/default/25.gpio_smoke_no_pullup_pulldown.973513268
Short name T460
Test name
Test status
Simulation time 36505821 ps
CPU time 0.69 seconds
Started Apr 18 12:31:17 PM PDT 24
Finished Apr 18 12:31:21 PM PDT 24
Peak memory 194160 kb
Host smart-2d0e1ee2-d95a-4e60-acf0-b5bc6b5099ff
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=973513268 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_no_pullup_pulldown.973513268
Directory /workspace/25.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/25.gpio_stress_all.3948325751
Short name T31
Test name
Test status
Simulation time 8446688917 ps
CPU time 44.55 seconds
Started Apr 18 12:31:17 PM PDT 24
Finished Apr 18 12:32:05 PM PDT 24
Peak memory 198028 kb
Host smart-71e79e43-a45d-4982-a647-32a6224c942b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3948325751 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.
gpio_stress_all.3948325751
Directory /workspace/25.gpio_stress_all/latest

Test location /workspace/coverage/default/26.gpio_alert_test.4264370891
Short name T598
Test name
Test status
Simulation time 13476631 ps
CPU time 0.54 seconds
Started Apr 18 12:31:05 PM PDT 24
Finished Apr 18 12:31:11 PM PDT 24
Peak memory 193840 kb
Host smart-ae33644d-77e7-419d-8d3a-827e15728b02
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4264370891 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_alert_test.4264370891
Directory /workspace/26.gpio_alert_test/latest

Test location /workspace/coverage/default/26.gpio_dout_din_regs_random_rw.1644341958
Short name T710
Test name
Test status
Simulation time 28534210 ps
CPU time 0.77 seconds
Started Apr 18 12:31:11 PM PDT 24
Finished Apr 18 12:31:18 PM PDT 24
Peak memory 195168 kb
Host smart-641a45ed-2fb9-44b3-afe3-a5a755f52318
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1644341958 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_dout_din_regs_random_rw.1644341958
Directory /workspace/26.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/26.gpio_filter_stress.2667481996
Short name T583
Test name
Test status
Simulation time 1509070609 ps
CPU time 5.25 seconds
Started Apr 18 12:31:05 PM PDT 24
Finished Apr 18 12:31:16 PM PDT 24
Peak memory 195444 kb
Host smart-d341171f-ce1f-4611-9757-f243d5869f25
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2667481996 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_filter_stre
ss.2667481996
Directory /workspace/26.gpio_filter_stress/latest

Test location /workspace/coverage/default/26.gpio_full_random.461022932
Short name T338
Test name
Test status
Simulation time 177823260 ps
CPU time 0.72 seconds
Started Apr 18 12:31:20 PM PDT 24
Finished Apr 18 12:31:24 PM PDT 24
Peak memory 195932 kb
Host smart-c138d546-b7f1-44e6-815c-5466d912b4a0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=461022932 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_full_random.461022932
Directory /workspace/26.gpio_full_random/latest

Test location /workspace/coverage/default/26.gpio_intr_rand_pgm.1382327055
Short name T538
Test name
Test status
Simulation time 75343418 ps
CPU time 0.66 seconds
Started Apr 18 12:31:02 PM PDT 24
Finished Apr 18 12:31:06 PM PDT 24
Peak memory 194380 kb
Host smart-edcf4dfe-ed6f-4ca1-96a0-cdf7c5204b7a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1382327055 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_intr_rand_pgm.1382327055
Directory /workspace/26.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/26.gpio_intr_with_filter_rand_intr_event.2253329857
Short name T554
Test name
Test status
Simulation time 303136133 ps
CPU time 3.44 seconds
Started Apr 18 12:31:03 PM PDT 24
Finished Apr 18 12:31:12 PM PDT 24
Peak memory 198124 kb
Host smart-cddc3b2c-1899-4e4e-99e8-0a1d62c9c5db
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2253329857 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 26.gpio_intr_with_filter_rand_intr_event.2253329857
Directory /workspace/26.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/26.gpio_rand_intr_trigger.3063563317
Short name T225
Test name
Test status
Simulation time 78212547 ps
CPU time 2.35 seconds
Started Apr 18 12:31:15 PM PDT 24
Finished Apr 18 12:31:21 PM PDT 24
Peak memory 197936 kb
Host smart-65b49c34-f810-47a1-88a2-853651629e9d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3063563317 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_rand_intr_trigger
.3063563317
Directory /workspace/26.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/26.gpio_random_dout_din.1255694790
Short name T497
Test name
Test status
Simulation time 39116001 ps
CPU time 1.25 seconds
Started Apr 18 12:31:06 PM PDT 24
Finished Apr 18 12:31:15 PM PDT 24
Peak memory 196932 kb
Host smart-5a1f5bd9-745b-4892-befa-3d0fac2b20cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1255694790 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_random_dout_din.1255694790
Directory /workspace/26.gpio_random_dout_din/latest

Test location /workspace/coverage/default/26.gpio_random_dout_din_no_pullup_pulldown.3247926719
Short name T611
Test name
Test status
Simulation time 38476391 ps
CPU time 1.3 seconds
Started Apr 18 12:31:18 PM PDT 24
Finished Apr 18 12:31:23 PM PDT 24
Peak memory 197980 kb
Host smart-36355121-9b8a-4238-8508-626dc5f47e58
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3247926719 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_random_dout_din_no_pullu
p_pulldown.3247926719
Directory /workspace/26.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/26.gpio_random_long_reg_writes_reg_reads.3428601040
Short name T452
Test name
Test status
Simulation time 224392301 ps
CPU time 2.83 seconds
Started Apr 18 12:31:05 PM PDT 24
Finished Apr 18 12:31:14 PM PDT 24
Peak memory 197964 kb
Host smart-75182951-5e43-43a1-994c-2d70b3824e6c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3428601040 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_ra
ndom_long_reg_writes_reg_reads.3428601040
Directory /workspace/26.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/26.gpio_smoke.4091650619
Short name T343
Test name
Test status
Simulation time 64013787 ps
CPU time 1.19 seconds
Started Apr 18 12:31:05 PM PDT 24
Finished Apr 18 12:31:17 PM PDT 24
Peak memory 195832 kb
Host smart-3d9ce5cb-7582-42f9-b326-5805aa9070b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4091650619 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_smoke.4091650619
Directory /workspace/26.gpio_smoke/latest

Test location /workspace/coverage/default/26.gpio_smoke_no_pullup_pulldown.2653084532
Short name T690
Test name
Test status
Simulation time 362374790 ps
CPU time 1.21 seconds
Started Apr 18 12:31:19 PM PDT 24
Finished Apr 18 12:31:24 PM PDT 24
Peak memory 196820 kb
Host smart-477c058d-c734-4d3b-b43f-c58603b6d647
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2653084532 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_no_pullup_pulldown.2653084532
Directory /workspace/26.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/26.gpio_stress_all.2341678947
Short name T243
Test name
Test status
Simulation time 8180177628 ps
CPU time 100.3 seconds
Started Apr 18 12:31:04 PM PDT 24
Finished Apr 18 12:32:50 PM PDT 24
Peak memory 198196 kb
Host smart-2ed5597a-00cc-4a92-b169-5c97a4037542
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2341678947 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.
gpio_stress_all.2341678947
Directory /workspace/26.gpio_stress_all/latest

Test location /workspace/coverage/default/27.gpio_alert_test.390135467
Short name T201
Test name
Test status
Simulation time 16725054 ps
CPU time 0.59 seconds
Started Apr 18 12:31:07 PM PDT 24
Finished Apr 18 12:31:15 PM PDT 24
Peak memory 193780 kb
Host smart-345f244e-a404-4a37-9c39-45a9c56d538e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=390135467 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_alert_test.390135467
Directory /workspace/27.gpio_alert_test/latest

Test location /workspace/coverage/default/27.gpio_dout_din_regs_random_rw.2504430296
Short name T463
Test name
Test status
Simulation time 40412627 ps
CPU time 0.82 seconds
Started Apr 18 12:31:07 PM PDT 24
Finished Apr 18 12:31:16 PM PDT 24
Peak memory 194164 kb
Host smart-c81e8c58-b8aa-4390-89ec-0aa45ecefeb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2504430296 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_dout_din_regs_random_rw.2504430296
Directory /workspace/27.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/27.gpio_filter_stress.2377877693
Short name T323
Test name
Test status
Simulation time 226694273 ps
CPU time 4.04 seconds
Started Apr 18 12:31:14 PM PDT 24
Finished Apr 18 12:31:23 PM PDT 24
Peak memory 196004 kb
Host smart-bfbd7698-7adb-413e-af7a-c6edca305720
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2377877693 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_filter_stre
ss.2377877693
Directory /workspace/27.gpio_filter_stress/latest

Test location /workspace/coverage/default/27.gpio_full_random.193924555
Short name T242
Test name
Test status
Simulation time 201764050 ps
CPU time 0.83 seconds
Started Apr 18 12:31:09 PM PDT 24
Finished Apr 18 12:31:17 PM PDT 24
Peak memory 195976 kb
Host smart-4ed22882-5c5d-4d5d-b6fa-529bd9581d8e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=193924555 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_full_random.193924555
Directory /workspace/27.gpio_full_random/latest

Test location /workspace/coverage/default/27.gpio_intr_rand_pgm.3399099672
Short name T576
Test name
Test status
Simulation time 126229198 ps
CPU time 1.07 seconds
Started Apr 18 12:31:20 PM PDT 24
Finished Apr 18 12:31:33 PM PDT 24
Peak memory 196668 kb
Host smart-876d130e-3943-496c-9645-50e753f4fff0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3399099672 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_intr_rand_pgm.3399099672
Directory /workspace/27.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/27.gpio_intr_with_filter_rand_intr_event.1524824054
Short name T135
Test name
Test status
Simulation time 119638766 ps
CPU time 2.39 seconds
Started Apr 18 12:31:16 PM PDT 24
Finished Apr 18 12:31:22 PM PDT 24
Peak memory 198032 kb
Host smart-78f14d18-6d5b-4e06-bb3a-611954582dae
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1524824054 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 27.gpio_intr_with_filter_rand_intr_event.1524824054
Directory /workspace/27.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/27.gpio_rand_intr_trigger.2522127744
Short name T708
Test name
Test status
Simulation time 198219044 ps
CPU time 1.94 seconds
Started Apr 18 12:31:10 PM PDT 24
Finished Apr 18 12:31:18 PM PDT 24
Peak memory 195932 kb
Host smart-7155a6e5-61b1-4e2f-a98b-0b3caa1972b5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2522127744 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_rand_intr_trigger
.2522127744
Directory /workspace/27.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/27.gpio_random_dout_din.4136765040
Short name T694
Test name
Test status
Simulation time 62526745 ps
CPU time 1.21 seconds
Started Apr 18 12:31:20 PM PDT 24
Finished Apr 18 12:31:24 PM PDT 24
Peak memory 197004 kb
Host smart-aef952db-609d-4d05-9afe-a8461e343d91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4136765040 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_random_dout_din.4136765040
Directory /workspace/27.gpio_random_dout_din/latest

Test location /workspace/coverage/default/27.gpio_random_dout_din_no_pullup_pulldown.3162980249
Short name T233
Test name
Test status
Simulation time 476109321 ps
CPU time 1.11 seconds
Started Apr 18 12:31:20 PM PDT 24
Finished Apr 18 12:31:24 PM PDT 24
Peak memory 196736 kb
Host smart-4445dad3-3859-4fda-a8ce-1d307699d600
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3162980249 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_random_dout_din_no_pullu
p_pulldown.3162980249
Directory /workspace/27.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/27.gpio_random_long_reg_writes_reg_reads.1507027334
Short name T469
Test name
Test status
Simulation time 690864442 ps
CPU time 3.81 seconds
Started Apr 18 12:31:03 PM PDT 24
Finished Apr 18 12:31:12 PM PDT 24
Peak memory 197900 kb
Host smart-78c0851a-6739-4c48-9e92-1a4ec8fd93d3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1507027334 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_ra
ndom_long_reg_writes_reg_reads.1507027334
Directory /workspace/27.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/27.gpio_smoke.1994598815
Short name T453
Test name
Test status
Simulation time 74474689 ps
CPU time 1.17 seconds
Started Apr 18 12:31:09 PM PDT 24
Finished Apr 18 12:31:17 PM PDT 24
Peak memory 195748 kb
Host smart-3baeb56b-fe78-4c2a-924d-81de56e14e2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1994598815 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_smoke.1994598815
Directory /workspace/27.gpio_smoke/latest

Test location /workspace/coverage/default/27.gpio_smoke_no_pullup_pulldown.497925679
Short name T588
Test name
Test status
Simulation time 106937817 ps
CPU time 0.98 seconds
Started Apr 18 12:31:44 PM PDT 24
Finished Apr 18 12:31:46 PM PDT 24
Peak memory 195416 kb
Host smart-f8ffccc0-5cf9-4433-8464-fcb7c8dc9992
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=497925679 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_no_pullup_pulldown.497925679
Directory /workspace/27.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/27.gpio_stress_all.534477993
Short name T698
Test name
Test status
Simulation time 5856375213 ps
CPU time 150.16 seconds
Started Apr 18 12:31:04 PM PDT 24
Finished Apr 18 12:33:40 PM PDT 24
Peak memory 198244 kb
Host smart-a131eb28-76fd-4eb0-af43-b15f2fd81a89
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=534477993 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.g
pio_stress_all.534477993
Directory /workspace/27.gpio_stress_all/latest

Test location /workspace/coverage/default/28.gpio_alert_test.2714529933
Short name T384
Test name
Test status
Simulation time 15327543 ps
CPU time 0.61 seconds
Started Apr 18 12:31:04 PM PDT 24
Finished Apr 18 12:31:11 PM PDT 24
Peak memory 193824 kb
Host smart-65f7b753-c001-4347-a7fa-480716cead4a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2714529933 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_alert_test.2714529933
Directory /workspace/28.gpio_alert_test/latest

Test location /workspace/coverage/default/28.gpio_dout_din_regs_random_rw.4027297708
Short name T11
Test name
Test status
Simulation time 15001118 ps
CPU time 0.61 seconds
Started Apr 18 12:31:12 PM PDT 24
Finished Apr 18 12:31:18 PM PDT 24
Peak memory 194056 kb
Host smart-a54fa0e1-c0f0-4c23-87da-e2515e90f7b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4027297708 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_dout_din_regs_random_rw.4027297708
Directory /workspace/28.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/28.gpio_filter_stress.694681867
Short name T506
Test name
Test status
Simulation time 500950340 ps
CPU time 23.28 seconds
Started Apr 18 12:31:02 PM PDT 24
Finished Apr 18 12:31:32 PM PDT 24
Peak memory 196860 kb
Host smart-088997f9-0b3f-4a24-ab94-e416e1506507
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=694681867 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_filter_stres
s.694681867
Directory /workspace/28.gpio_filter_stress/latest

Test location /workspace/coverage/default/28.gpio_full_random.703828894
Short name T64
Test name
Test status
Simulation time 30220026 ps
CPU time 0.68 seconds
Started Apr 18 12:31:05 PM PDT 24
Finished Apr 18 12:31:11 PM PDT 24
Peak memory 194524 kb
Host smart-c8c0affd-c352-40f6-b3bc-8a1c60adb479
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=703828894 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_full_random.703828894
Directory /workspace/28.gpio_full_random/latest

Test location /workspace/coverage/default/28.gpio_intr_rand_pgm.2754997770
Short name T495
Test name
Test status
Simulation time 94094121 ps
CPU time 1.28 seconds
Started Apr 18 12:31:07 PM PDT 24
Finished Apr 18 12:31:16 PM PDT 24
Peak memory 196856 kb
Host smart-e681af4e-f060-46bf-a0c2-775be9fefec4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2754997770 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_intr_rand_pgm.2754997770
Directory /workspace/28.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/28.gpio_intr_with_filter_rand_intr_event.4112655271
Short name T412
Test name
Test status
Simulation time 261360592 ps
CPU time 2.65 seconds
Started Apr 18 12:31:20 PM PDT 24
Finished Apr 18 12:31:26 PM PDT 24
Peak memory 198108 kb
Host smart-d513bd98-6a2a-4499-b6e7-fb44533181b0
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4112655271 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 28.gpio_intr_with_filter_rand_intr_event.4112655271
Directory /workspace/28.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/28.gpio_rand_intr_trigger.2720775609
Short name T640
Test name
Test status
Simulation time 53892871 ps
CPU time 0.84 seconds
Started Apr 18 12:31:05 PM PDT 24
Finished Apr 18 12:31:11 PM PDT 24
Peak memory 195072 kb
Host smart-9fa5c497-2222-4bfe-8818-392c5f6ab5dc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2720775609 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_rand_intr_trigger
.2720775609
Directory /workspace/28.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/28.gpio_random_dout_din.1661674555
Short name T365
Test name
Test status
Simulation time 109368674 ps
CPU time 0.77 seconds
Started Apr 18 12:31:04 PM PDT 24
Finished Apr 18 12:31:10 PM PDT 24
Peak memory 195296 kb
Host smart-f2129808-eb58-4566-9164-f70f9d6b92e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1661674555 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_random_dout_din.1661674555
Directory /workspace/28.gpio_random_dout_din/latest

Test location /workspace/coverage/default/28.gpio_random_dout_din_no_pullup_pulldown.1007595483
Short name T591
Test name
Test status
Simulation time 566974683 ps
CPU time 1.15 seconds
Started Apr 18 12:31:04 PM PDT 24
Finished Apr 18 12:31:11 PM PDT 24
Peak memory 196488 kb
Host smart-5acd3fcd-9308-4bc2-8ceb-3ae7185cdf2f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1007595483 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_random_dout_din_no_pullu
p_pulldown.1007595483
Directory /workspace/28.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/28.gpio_random_long_reg_writes_reg_reads.2842838447
Short name T425
Test name
Test status
Simulation time 637940985 ps
CPU time 2.02 seconds
Started Apr 18 12:31:19 PM PDT 24
Finished Apr 18 12:31:24 PM PDT 24
Peak memory 197848 kb
Host smart-3a0c0faa-8b71-4dc5-b122-4d22f1391dbb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2842838447 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_ra
ndom_long_reg_writes_reg_reads.2842838447
Directory /workspace/28.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/28.gpio_smoke.241229850
Short name T13
Test name
Test status
Simulation time 92093796 ps
CPU time 1.38 seconds
Started Apr 18 12:31:22 PM PDT 24
Finished Apr 18 12:31:26 PM PDT 24
Peak memory 196756 kb
Host smart-9d7f9b26-65b4-4387-91ea-806c1722c4a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=241229850 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_smoke.241229850
Directory /workspace/28.gpio_smoke/latest

Test location /workspace/coverage/default/28.gpio_smoke_no_pullup_pulldown.1736238072
Short name T709
Test name
Test status
Simulation time 136396426 ps
CPU time 0.94 seconds
Started Apr 18 12:31:17 PM PDT 24
Finished Apr 18 12:31:22 PM PDT 24
Peak memory 195596 kb
Host smart-0d980a96-1e63-4e9e-b913-b053da67a9e1
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1736238072 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_no_pullup_pulldown.1736238072
Directory /workspace/28.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/28.gpio_stress_all.4104018053
Short name T375
Test name
Test status
Simulation time 12676826140 ps
CPU time 169.46 seconds
Started Apr 18 12:31:14 PM PDT 24
Finished Apr 18 12:34:08 PM PDT 24
Peak memory 198160 kb
Host smart-d75ae51d-105c-4b4e-ae3a-b7753475b8eb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4104018053 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.
gpio_stress_all.4104018053
Directory /workspace/28.gpio_stress_all/latest

Test location /workspace/coverage/default/29.gpio_alert_test.863721568
Short name T599
Test name
Test status
Simulation time 18200109 ps
CPU time 0.56 seconds
Started Apr 18 12:31:16 PM PDT 24
Finished Apr 18 12:31:21 PM PDT 24
Peak memory 193948 kb
Host smart-0ca20718-6c3d-42a4-ab41-2c116ba125eb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=863721568 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_alert_test.863721568
Directory /workspace/29.gpio_alert_test/latest

Test location /workspace/coverage/default/29.gpio_dout_din_regs_random_rw.1733923900
Short name T115
Test name
Test status
Simulation time 100120833 ps
CPU time 0.89 seconds
Started Apr 18 12:31:19 PM PDT 24
Finished Apr 18 12:31:23 PM PDT 24
Peak memory 195816 kb
Host smart-4fa8f217-0a61-474f-9586-0bbf5fbf1c15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1733923900 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_dout_din_regs_random_rw.1733923900
Directory /workspace/29.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/29.gpio_filter_stress.4087705578
Short name T367
Test name
Test status
Simulation time 3178916447 ps
CPU time 26.04 seconds
Started Apr 18 12:31:10 PM PDT 24
Finished Apr 18 12:31:42 PM PDT 24
Peak memory 197724 kb
Host smart-60563042-79bb-4158-81ee-8b0f5ff65dd9
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4087705578 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_filter_stre
ss.4087705578
Directory /workspace/29.gpio_filter_stress/latest

Test location /workspace/coverage/default/29.gpio_full_random.582142109
Short name T406
Test name
Test status
Simulation time 199677638 ps
CPU time 0.77 seconds
Started Apr 18 12:31:06 PM PDT 24
Finished Apr 18 12:31:13 PM PDT 24
Peak memory 195920 kb
Host smart-cba91196-7e94-4a97-89b4-79efa741f40b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=582142109 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_full_random.582142109
Directory /workspace/29.gpio_full_random/latest

Test location /workspace/coverage/default/29.gpio_intr_rand_pgm.2146008258
Short name T675
Test name
Test status
Simulation time 93757472 ps
CPU time 0.95 seconds
Started Apr 18 12:31:16 PM PDT 24
Finished Apr 18 12:31:21 PM PDT 24
Peak memory 195900 kb
Host smart-1881c528-14fd-4306-a8a3-5045e55252a3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2146008258 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_intr_rand_pgm.2146008258
Directory /workspace/29.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/29.gpio_intr_with_filter_rand_intr_event.2945691958
Short name T429
Test name
Test status
Simulation time 74654451 ps
CPU time 2.74 seconds
Started Apr 18 12:31:22 PM PDT 24
Finished Apr 18 12:31:27 PM PDT 24
Peak memory 197992 kb
Host smart-1ca03499-a49e-40b2-835e-cc54df078e52
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2945691958 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 29.gpio_intr_with_filter_rand_intr_event.2945691958
Directory /workspace/29.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/29.gpio_rand_intr_trigger.684635063
Short name T247
Test name
Test status
Simulation time 427419582 ps
CPU time 2.43 seconds
Started Apr 18 12:31:06 PM PDT 24
Finished Apr 18 12:31:15 PM PDT 24
Peak memory 198000 kb
Host smart-44f023ed-3738-4877-94f5-87625d8053a3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=684635063 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_rand_intr_trigger.
684635063
Directory /workspace/29.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/29.gpio_random_dout_din.1985984630
Short name T344
Test name
Test status
Simulation time 46078513 ps
CPU time 0.66 seconds
Started Apr 18 12:31:20 PM PDT 24
Finished Apr 18 12:31:24 PM PDT 24
Peak memory 194908 kb
Host smart-b1e46f75-4c12-4c65-95e0-1cc5933485b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1985984630 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_random_dout_din.1985984630
Directory /workspace/29.gpio_random_dout_din/latest

Test location /workspace/coverage/default/29.gpio_random_dout_din_no_pullup_pulldown.3708935500
Short name T484
Test name
Test status
Simulation time 130422533 ps
CPU time 0.84 seconds
Started Apr 18 12:31:11 PM PDT 24
Finished Apr 18 12:31:18 PM PDT 24
Peak memory 196740 kb
Host smart-e0911812-ef9b-4641-b004-aec667800d17
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3708935500 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_random_dout_din_no_pullu
p_pulldown.3708935500
Directory /workspace/29.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/29.gpio_random_long_reg_writes_reg_reads.1336323653
Short name T574
Test name
Test status
Simulation time 86750085 ps
CPU time 3.92 seconds
Started Apr 18 12:31:31 PM PDT 24
Finished Apr 18 12:31:36 PM PDT 24
Peak memory 197604 kb
Host smart-1686d486-0596-4d53-af67-0218e1aadb9a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1336323653 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_ra
ndom_long_reg_writes_reg_reads.1336323653
Directory /workspace/29.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/29.gpio_smoke.1408473944
Short name T485
Test name
Test status
Simulation time 32067590 ps
CPU time 0.8 seconds
Started Apr 18 12:31:17 PM PDT 24
Finished Apr 18 12:31:21 PM PDT 24
Peak memory 195212 kb
Host smart-7006e9d7-4ac5-427c-8917-83d099eceb03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1408473944 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_smoke.1408473944
Directory /workspace/29.gpio_smoke/latest

Test location /workspace/coverage/default/29.gpio_smoke_no_pullup_pulldown.2306897890
Short name T672
Test name
Test status
Simulation time 54870699 ps
CPU time 0.97 seconds
Started Apr 18 12:31:10 PM PDT 24
Finished Apr 18 12:31:17 PM PDT 24
Peak memory 196420 kb
Host smart-dcc2cd56-1a4f-4950-b5bd-41a9c2908381
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2306897890 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_no_pullup_pulldown.2306897890
Directory /workspace/29.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/29.gpio_stress_all.2458542068
Short name T659
Test name
Test status
Simulation time 18858029446 ps
CPU time 212.86 seconds
Started Apr 18 12:31:13 PM PDT 24
Finished Apr 18 12:34:51 PM PDT 24
Peak memory 198232 kb
Host smart-3e20cab9-cefe-4712-a987-6a6b0441959c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2458542068 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.
gpio_stress_all.2458542068
Directory /workspace/29.gpio_stress_all/latest

Test location /workspace/coverage/default/3.gpio_alert_test.2544412905
Short name T408
Test name
Test status
Simulation time 13459862 ps
CPU time 0.57 seconds
Started Apr 18 12:31:56 PM PDT 24
Finished Apr 18 12:31:58 PM PDT 24
Peak memory 194492 kb
Host smart-a3a43fad-706e-420f-a4c9-8e20d85ca001
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2544412905 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_alert_test.2544412905
Directory /workspace/3.gpio_alert_test/latest

Test location /workspace/coverage/default/3.gpio_dout_din_regs_random_rw.1816268850
Short name T490
Test name
Test status
Simulation time 107590192 ps
CPU time 0.84 seconds
Started Apr 18 12:30:35 PM PDT 24
Finished Apr 18 12:30:36 PM PDT 24
Peak memory 195400 kb
Host smart-400dd34e-4bfe-4d1f-9f38-f5cb397e6019
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1816268850 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_dout_din_regs_random_rw.1816268850
Directory /workspace/3.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/3.gpio_filter_stress.1290030472
Short name T194
Test name
Test status
Simulation time 4190178029 ps
CPU time 15.69 seconds
Started Apr 18 12:30:39 PM PDT 24
Finished Apr 18 12:30:56 PM PDT 24
Peak memory 198072 kb
Host smart-cf7f8973-96fa-478b-b882-0e92e691abc3
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1290030472 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_filter_stres
s.1290030472
Directory /workspace/3.gpio_filter_stress/latest

Test location /workspace/coverage/default/3.gpio_full_random.3450531518
Short name T293
Test name
Test status
Simulation time 37192229 ps
CPU time 0.7 seconds
Started Apr 18 12:30:40 PM PDT 24
Finished Apr 18 12:30:42 PM PDT 24
Peak memory 194728 kb
Host smart-a19e5f6d-be1c-4ba6-93c3-9bb93a4e1b49
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3450531518 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_full_random.3450531518
Directory /workspace/3.gpio_full_random/latest

Test location /workspace/coverage/default/3.gpio_intr_rand_pgm.2284611144
Short name T641
Test name
Test status
Simulation time 150730528 ps
CPU time 0.81 seconds
Started Apr 18 12:30:41 PM PDT 24
Finished Apr 18 12:30:42 PM PDT 24
Peak memory 196280 kb
Host smart-ba72613d-4645-4bf6-8cd4-0f50e0315d7b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2284611144 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_intr_rand_pgm.2284611144
Directory /workspace/3.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/3.gpio_intr_with_filter_rand_intr_event.2434317792
Short name T148
Test name
Test status
Simulation time 43505801 ps
CPU time 1.04 seconds
Started Apr 18 12:30:30 PM PDT 24
Finished Apr 18 12:30:32 PM PDT 24
Peak memory 196208 kb
Host smart-17a030b7-ab8b-4b56-90df-1c0b10394045
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2434317792 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 3.gpio_intr_with_filter_rand_intr_event.2434317792
Directory /workspace/3.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/3.gpio_rand_intr_trigger.1122954747
Short name T632
Test name
Test status
Simulation time 101141622 ps
CPU time 0.95 seconds
Started Apr 18 12:30:46 PM PDT 24
Finished Apr 18 12:30:48 PM PDT 24
Peak memory 194380 kb
Host smart-5bcefc7e-765a-495d-98b7-1fa69537fbf6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1122954747 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_rand_intr_trigger.
1122954747
Directory /workspace/3.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/3.gpio_random_dout_din.957021126
Short name T405
Test name
Test status
Simulation time 50060523 ps
CPU time 1.04 seconds
Started Apr 18 12:30:41 PM PDT 24
Finished Apr 18 12:30:43 PM PDT 24
Peak memory 195892 kb
Host smart-c3343a02-31aa-42a3-a7e2-012e5ff7d755
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=957021126 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_random_dout_din.957021126
Directory /workspace/3.gpio_random_dout_din/latest

Test location /workspace/coverage/default/3.gpio_random_dout_din_no_pullup_pulldown.516809472
Short name T464
Test name
Test status
Simulation time 162179308 ps
CPU time 0.99 seconds
Started Apr 18 12:30:38 PM PDT 24
Finished Apr 18 12:30:40 PM PDT 24
Peak memory 196652 kb
Host smart-d89999eb-9cf2-4d59-9963-5148f3be178e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=516809472 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_random_dout_din_no_pullup_
pulldown.516809472
Directory /workspace/3.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/3.gpio_random_long_reg_writes_reg_reads.2823599431
Short name T204
Test name
Test status
Simulation time 94857207 ps
CPU time 1.94 seconds
Started Apr 18 12:30:28 PM PDT 24
Finished Apr 18 12:30:31 PM PDT 24
Peak memory 198004 kb
Host smart-9ea78716-aa50-49c4-87df-0b3eefb55f12
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2823599431 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_ran
dom_long_reg_writes_reg_reads.2823599431
Directory /workspace/3.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/3.gpio_smoke.4275636186
Short name T639
Test name
Test status
Simulation time 42165610 ps
CPU time 0.9 seconds
Started Apr 18 12:30:33 PM PDT 24
Finished Apr 18 12:30:35 PM PDT 24
Peak memory 197056 kb
Host smart-d35ef8b9-2f79-4814-9dfe-539df50d2d0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4275636186 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_smoke.4275636186
Directory /workspace/3.gpio_smoke/latest

Test location /workspace/coverage/default/3.gpio_smoke_no_pullup_pulldown.4020121356
Short name T158
Test name
Test status
Simulation time 33796907 ps
CPU time 1 seconds
Started Apr 18 12:30:44 PM PDT 24
Finished Apr 18 12:30:46 PM PDT 24
Peak memory 196168 kb
Host smart-417c69f8-bb87-4d0e-934f-cfb1f35545d4
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4020121356 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_no_pullup_pulldown.4020121356
Directory /workspace/3.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/3.gpio_stress_all.2753652260
Short name T6
Test name
Test status
Simulation time 29283747846 ps
CPU time 81.51 seconds
Started Apr 18 12:30:25 PM PDT 24
Finished Apr 18 12:31:49 PM PDT 24
Peak memory 198024 kb
Host smart-1a92f6c3-b95e-4192-9023-5a78cfdbb1ab
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2753652260 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.g
pio_stress_all.2753652260
Directory /workspace/3.gpio_stress_all/latest

Test location /workspace/coverage/default/30.gpio_alert_test.860454992
Short name T391
Test name
Test status
Simulation time 35808917 ps
CPU time 0.56 seconds
Started Apr 18 12:31:04 PM PDT 24
Finished Apr 18 12:31:09 PM PDT 24
Peak memory 193816 kb
Host smart-e60ef20b-f104-4fce-a4cf-9b79e3f47c00
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=860454992 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_alert_test.860454992
Directory /workspace/30.gpio_alert_test/latest

Test location /workspace/coverage/default/30.gpio_dout_din_regs_random_rw.3306865686
Short name T693
Test name
Test status
Simulation time 22412375 ps
CPU time 0.65 seconds
Started Apr 18 12:31:13 PM PDT 24
Finished Apr 18 12:31:19 PM PDT 24
Peak memory 195256 kb
Host smart-c402c372-bcec-476b-9594-afc2bc8a99e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3306865686 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_dout_din_regs_random_rw.3306865686
Directory /workspace/30.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/30.gpio_filter_stress.2490212838
Short name T305
Test name
Test status
Simulation time 3805956620 ps
CPU time 12.11 seconds
Started Apr 18 12:31:43 PM PDT 24
Finished Apr 18 12:31:56 PM PDT 24
Peak memory 196724 kb
Host smart-d8011e9e-4aa0-4ff1-afd2-52eca4808be3
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2490212838 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_filter_stre
ss.2490212838
Directory /workspace/30.gpio_filter_stress/latest

Test location /workspace/coverage/default/30.gpio_full_random.3995845393
Short name T544
Test name
Test status
Simulation time 40005341 ps
CPU time 0.69 seconds
Started Apr 18 12:31:20 PM PDT 24
Finished Apr 18 12:31:24 PM PDT 24
Peak memory 194808 kb
Host smart-795058a9-c257-452c-80e5-1478696635f7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3995845393 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_full_random.3995845393
Directory /workspace/30.gpio_full_random/latest

Test location /workspace/coverage/default/30.gpio_intr_rand_pgm.1495392170
Short name T211
Test name
Test status
Simulation time 50922221 ps
CPU time 1.29 seconds
Started Apr 18 12:31:33 PM PDT 24
Finished Apr 18 12:31:35 PM PDT 24
Peak memory 195788 kb
Host smart-bee160c0-8f99-415b-8cbf-f5a16d276ecf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1495392170 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_intr_rand_pgm.1495392170
Directory /workspace/30.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/30.gpio_intr_with_filter_rand_intr_event.1832094974
Short name T165
Test name
Test status
Simulation time 23971579 ps
CPU time 1.1 seconds
Started Apr 18 12:31:04 PM PDT 24
Finished Apr 18 12:31:11 PM PDT 24
Peak memory 196524 kb
Host smart-96628a76-91c5-47ac-a921-05016c7a47f9
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1832094974 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 30.gpio_intr_with_filter_rand_intr_event.1832094974
Directory /workspace/30.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/30.gpio_rand_intr_trigger.2964212613
Short name T420
Test name
Test status
Simulation time 172332222 ps
CPU time 1.66 seconds
Started Apr 18 12:31:26 PM PDT 24
Finished Apr 18 12:31:29 PM PDT 24
Peak memory 196856 kb
Host smart-666b6594-ee8c-4a4c-8267-8831ba8308c2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2964212613 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_rand_intr_trigger
.2964212613
Directory /workspace/30.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/30.gpio_random_dout_din.171380069
Short name T520
Test name
Test status
Simulation time 159910943 ps
CPU time 0.67 seconds
Started Apr 18 12:31:17 PM PDT 24
Finished Apr 18 12:31:21 PM PDT 24
Peak memory 194232 kb
Host smart-74ea2504-5b0d-4593-b9aa-2c955303b05e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=171380069 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_random_dout_din.171380069
Directory /workspace/30.gpio_random_dout_din/latest

Test location /workspace/coverage/default/30.gpio_random_dout_din_no_pullup_pulldown.3821314933
Short name T177
Test name
Test status
Simulation time 28980601 ps
CPU time 1.13 seconds
Started Apr 18 12:31:22 PM PDT 24
Finished Apr 18 12:31:25 PM PDT 24
Peak memory 195996 kb
Host smart-a2d94127-27c8-499a-93c7-3baf1a099df7
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3821314933 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_random_dout_din_no_pullu
p_pulldown.3821314933
Directory /workspace/30.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/30.gpio_random_long_reg_writes_reg_reads.8054068
Short name T647
Test name
Test status
Simulation time 1048125889 ps
CPU time 5.95 seconds
Started Apr 18 12:31:30 PM PDT 24
Finished Apr 18 12:31:36 PM PDT 24
Peak memory 197984 kb
Host smart-8a758301-bf2c-4376-8a16-e90c78558486
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8054068 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_wr
ites_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_rando
m_long_reg_writes_reg_reads.8054068
Directory /workspace/30.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/30.gpio_smoke.2312678151
Short name T278
Test name
Test status
Simulation time 96408152 ps
CPU time 1.22 seconds
Started Apr 18 12:31:14 PM PDT 24
Finished Apr 18 12:31:20 PM PDT 24
Peak memory 195472 kb
Host smart-d9536bec-4af7-4a85-bba2-11c0f0d675d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2312678151 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_smoke.2312678151
Directory /workspace/30.gpio_smoke/latest

Test location /workspace/coverage/default/30.gpio_smoke_no_pullup_pulldown.317009766
Short name T164
Test name
Test status
Simulation time 33010909 ps
CPU time 0.96 seconds
Started Apr 18 12:31:06 PM PDT 24
Finished Apr 18 12:31:13 PM PDT 24
Peak memory 196448 kb
Host smart-5098a512-f96a-49bc-89be-5073e9287eda
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=317009766 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_no_pullup_pulldown.317009766
Directory /workspace/30.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/30.gpio_stress_all.3560828217
Short name T196
Test name
Test status
Simulation time 5696371804 ps
CPU time 37.79 seconds
Started Apr 18 12:31:30 PM PDT 24
Finished Apr 18 12:32:09 PM PDT 24
Peak memory 198032 kb
Host smart-5ab1bab9-7fee-4c32-8324-13d0c82d6e04
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3560828217 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.
gpio_stress_all.3560828217
Directory /workspace/30.gpio_stress_all/latest

Test location /workspace/coverage/default/30.gpio_stress_all_with_rand_reset.4282745535
Short name T711
Test name
Test status
Simulation time 205359970224 ps
CPU time 1516.59 seconds
Started Apr 18 12:31:17 PM PDT 24
Finished Apr 18 12:56:37 PM PDT 24
Peak memory 198100 kb
Host smart-bbff3a59-ff05-45f6-b523-2d9445401305
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=4282745535 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_stress_all_with_rand_reset.4282745535
Directory /workspace/30.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.gpio_alert_test.1062649469
Short name T208
Test name
Test status
Simulation time 27528007 ps
CPU time 0.55 seconds
Started Apr 18 12:31:22 PM PDT 24
Finished Apr 18 12:31:25 PM PDT 24
Peak memory 194044 kb
Host smart-10fc17e7-e0a3-4e8a-92f7-c5fb72bbb435
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1062649469 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_alert_test.1062649469
Directory /workspace/31.gpio_alert_test/latest

Test location /workspace/coverage/default/31.gpio_dout_din_regs_random_rw.2948572435
Short name T102
Test name
Test status
Simulation time 26472374 ps
CPU time 0.79 seconds
Started Apr 18 12:31:24 PM PDT 24
Finished Apr 18 12:31:27 PM PDT 24
Peak memory 195932 kb
Host smart-4b95e1fd-beeb-43c7-9e5b-a81ef8e3312a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2948572435 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_dout_din_regs_random_rw.2948572435
Directory /workspace/31.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/31.gpio_filter_stress.883029509
Short name T123
Test name
Test status
Simulation time 657704613 ps
CPU time 19.02 seconds
Started Apr 18 12:31:32 PM PDT 24
Finished Apr 18 12:31:51 PM PDT 24
Peak memory 196908 kb
Host smart-d884725f-b924-4bfa-880a-0d5bf6ebc10a
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=883029509 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_filter_stres
s.883029509
Directory /workspace/31.gpio_filter_stress/latest

Test location /workspace/coverage/default/31.gpio_full_random.178869684
Short name T20
Test name
Test status
Simulation time 127160148 ps
CPU time 0.89 seconds
Started Apr 18 12:31:22 PM PDT 24
Finished Apr 18 12:31:26 PM PDT 24
Peak memory 196736 kb
Host smart-486c82f0-b5aa-41ae-8d6b-5c586e0b9643
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=178869684 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_full_random.178869684
Directory /workspace/31.gpio_full_random/latest

Test location /workspace/coverage/default/31.gpio_intr_rand_pgm.148627839
Short name T219
Test name
Test status
Simulation time 50501602 ps
CPU time 1.3 seconds
Started Apr 18 12:31:29 PM PDT 24
Finished Apr 18 12:31:32 PM PDT 24
Peak memory 196984 kb
Host smart-39cc2248-2c86-4e40-9e23-39ead349082a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=148627839 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_intr_rand_pgm.148627839
Directory /workspace/31.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/31.gpio_intr_with_filter_rand_intr_event.2136926723
Short name T655
Test name
Test status
Simulation time 114283097 ps
CPU time 1.82 seconds
Started Apr 18 12:31:21 PM PDT 24
Finished Apr 18 12:31:26 PM PDT 24
Peak memory 198084 kb
Host smart-3e51bd72-a3d6-4e2d-a999-bc673946bf0b
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2136926723 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 31.gpio_intr_with_filter_rand_intr_event.2136926723
Directory /workspace/31.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/31.gpio_rand_intr_trigger.2372985781
Short name T428
Test name
Test status
Simulation time 598298414 ps
CPU time 2.94 seconds
Started Apr 18 12:31:47 PM PDT 24
Finished Apr 18 12:31:50 PM PDT 24
Peak memory 198176 kb
Host smart-6361b604-5311-4d04-812b-b2862ccf2da0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2372985781 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_rand_intr_trigger
.2372985781
Directory /workspace/31.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/31.gpio_random_dout_din.1896786041
Short name T222
Test name
Test status
Simulation time 56861025 ps
CPU time 1.16 seconds
Started Apr 18 12:31:29 PM PDT 24
Finished Apr 18 12:31:31 PM PDT 24
Peak memory 197980 kb
Host smart-d03cccd2-e96e-4067-9c9f-218f0c172716
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1896786041 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_random_dout_din.1896786041
Directory /workspace/31.gpio_random_dout_din/latest

Test location /workspace/coverage/default/31.gpio_random_dout_din_no_pullup_pulldown.1260521731
Short name T118
Test name
Test status
Simulation time 71495442 ps
CPU time 1.25 seconds
Started Apr 18 12:31:22 PM PDT 24
Finished Apr 18 12:31:25 PM PDT 24
Peak memory 198124 kb
Host smart-b19a57b8-e3d3-4391-b281-81f8a7381b56
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1260521731 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_random_dout_din_no_pullu
p_pulldown.1260521731
Directory /workspace/31.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/31.gpio_smoke.2712756388
Short name T195
Test name
Test status
Simulation time 40732857 ps
CPU time 0.85 seconds
Started Apr 18 12:31:19 PM PDT 24
Finished Apr 18 12:31:23 PM PDT 24
Peak memory 196484 kb
Host smart-696f630a-d260-4ecb-9060-a346d673787f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2712756388 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_smoke.2712756388
Directory /workspace/31.gpio_smoke/latest

Test location /workspace/coverage/default/31.gpio_smoke_no_pullup_pulldown.3132620770
Short name T594
Test name
Test status
Simulation time 84049017 ps
CPU time 0.75 seconds
Started Apr 18 12:31:03 PM PDT 24
Finished Apr 18 12:31:10 PM PDT 24
Peak memory 195144 kb
Host smart-46a540f3-e804-4293-a842-286359b22c14
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3132620770 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_no_pullup_pulldown.3132620770
Directory /workspace/31.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/31.gpio_stress_all.781114718
Short name T276
Test name
Test status
Simulation time 26628605456 ps
CPU time 170.23 seconds
Started Apr 18 12:31:24 PM PDT 24
Finished Apr 18 12:34:16 PM PDT 24
Peak memory 198084 kb
Host smart-a4c27e66-654e-48c6-a391-e381f00c698b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=781114718 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.g
pio_stress_all.781114718
Directory /workspace/31.gpio_stress_all/latest

Test location /workspace/coverage/default/32.gpio_alert_test.680597735
Short name T424
Test name
Test status
Simulation time 11384393 ps
CPU time 0.54 seconds
Started Apr 18 12:31:56 PM PDT 24
Finished Apr 18 12:32:09 PM PDT 24
Peak memory 194512 kb
Host smart-402cb216-d104-4a6c-aafa-77a17b3e7422
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=680597735 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_alert_test.680597735
Directory /workspace/32.gpio_alert_test/latest

Test location /workspace/coverage/default/32.gpio_dout_din_regs_random_rw.3058528388
Short name T409
Test name
Test status
Simulation time 99922791 ps
CPU time 0.84 seconds
Started Apr 18 12:31:25 PM PDT 24
Finished Apr 18 12:31:27 PM PDT 24
Peak memory 196512 kb
Host smart-71881685-3b80-42da-8e5c-1fb08c398de9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3058528388 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_dout_din_regs_random_rw.3058528388
Directory /workspace/32.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/32.gpio_filter_stress.2899025694
Short name T209
Test name
Test status
Simulation time 4212845419 ps
CPU time 11.16 seconds
Started Apr 18 12:31:34 PM PDT 24
Finished Apr 18 12:31:46 PM PDT 24
Peak memory 196964 kb
Host smart-20bc54eb-541f-4437-98eb-de54c2ca757a
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2899025694 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_filter_stre
ss.2899025694
Directory /workspace/32.gpio_filter_stress/latest

Test location /workspace/coverage/default/32.gpio_full_random.3634296861
Short name T399
Test name
Test status
Simulation time 171419752 ps
CPU time 0.79 seconds
Started Apr 18 12:31:17 PM PDT 24
Finished Apr 18 12:31:22 PM PDT 24
Peak memory 195876 kb
Host smart-db945a3f-d892-4830-8085-7a9f68064713
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3634296861 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_full_random.3634296861
Directory /workspace/32.gpio_full_random/latest

Test location /workspace/coverage/default/32.gpio_intr_rand_pgm.852743351
Short name T456
Test name
Test status
Simulation time 37807560 ps
CPU time 1.02 seconds
Started Apr 18 12:31:26 PM PDT 24
Finished Apr 18 12:31:28 PM PDT 24
Peak memory 196492 kb
Host smart-df8d0950-a5a5-4a57-a4fe-cdab7a4d909d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=852743351 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_intr_rand_pgm.852743351
Directory /workspace/32.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/32.gpio_intr_with_filter_rand_intr_event.3685917556
Short name T471
Test name
Test status
Simulation time 162372433 ps
CPU time 1.74 seconds
Started Apr 18 12:31:36 PM PDT 24
Finished Apr 18 12:31:38 PM PDT 24
Peak memory 197192 kb
Host smart-01d48f82-3e79-4f17-a9b2-8ff86109ef90
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3685917556 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 32.gpio_intr_with_filter_rand_intr_event.3685917556
Directory /workspace/32.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/32.gpio_rand_intr_trigger.2526842273
Short name T29
Test name
Test status
Simulation time 88838201 ps
CPU time 1.79 seconds
Started Apr 18 12:31:25 PM PDT 24
Finished Apr 18 12:31:28 PM PDT 24
Peak memory 195712 kb
Host smart-a0c9e54e-0add-4d59-a731-73c2f22d555a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2526842273 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_rand_intr_trigger
.2526842273
Directory /workspace/32.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/32.gpio_random_dout_din.786486343
Short name T486
Test name
Test status
Simulation time 46144947 ps
CPU time 0.68 seconds
Started Apr 18 12:31:14 PM PDT 24
Finished Apr 18 12:31:19 PM PDT 24
Peak memory 195316 kb
Host smart-f6f518cf-fc78-45b8-99cb-9df1e72767e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=786486343 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_random_dout_din.786486343
Directory /workspace/32.gpio_random_dout_din/latest

Test location /workspace/coverage/default/32.gpio_random_dout_din_no_pullup_pulldown.2683126733
Short name T567
Test name
Test status
Simulation time 858428070 ps
CPU time 1.25 seconds
Started Apr 18 12:31:16 PM PDT 24
Finished Apr 18 12:31:22 PM PDT 24
Peak memory 196888 kb
Host smart-a348bb18-93d6-45e2-ad69-053540ea6b45
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2683126733 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_random_dout_din_no_pullu
p_pulldown.2683126733
Directory /workspace/32.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/32.gpio_random_long_reg_writes_reg_reads.1603131105
Short name T188
Test name
Test status
Simulation time 160650701 ps
CPU time 1.07 seconds
Started Apr 18 12:31:38 PM PDT 24
Finished Apr 18 12:31:40 PM PDT 24
Peak memory 196196 kb
Host smart-facc6811-40a4-4af2-afef-072fdfe3c64b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1603131105 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_ra
ndom_long_reg_writes_reg_reads.1603131105
Directory /workspace/32.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/32.gpio_smoke.1941045560
Short name T262
Test name
Test status
Simulation time 46772992 ps
CPU time 0.93 seconds
Started Apr 18 12:31:23 PM PDT 24
Finished Apr 18 12:31:26 PM PDT 24
Peak memory 195696 kb
Host smart-28ad7aec-f099-494e-b8c9-451baaffec5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1941045560 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_smoke.1941045560
Directory /workspace/32.gpio_smoke/latest

Test location /workspace/coverage/default/32.gpio_smoke_no_pullup_pulldown.3398351109
Short name T223
Test name
Test status
Simulation time 80558564 ps
CPU time 0.69 seconds
Started Apr 18 12:31:15 PM PDT 24
Finished Apr 18 12:31:20 PM PDT 24
Peak memory 195184 kb
Host smart-7cf031e5-c9d0-47a7-80b4-6d07a5c67eee
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3398351109 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_no_pullup_pulldown.3398351109
Directory /workspace/32.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/32.gpio_stress_all.3825671729
Short name T1
Test name
Test status
Simulation time 5689602739 ps
CPU time 61.56 seconds
Started Apr 18 12:31:29 PM PDT 24
Finished Apr 18 12:32:31 PM PDT 24
Peak memory 198116 kb
Host smart-891d111f-8745-47e8-b506-d43e5530d6d2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3825671729 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.
gpio_stress_all.3825671729
Directory /workspace/32.gpio_stress_all/latest

Test location /workspace/coverage/default/33.gpio_alert_test.4281511541
Short name T601
Test name
Test status
Simulation time 14934139 ps
CPU time 0.59 seconds
Started Apr 18 12:31:28 PM PDT 24
Finished Apr 18 12:31:29 PM PDT 24
Peak memory 194024 kb
Host smart-cc40105e-5c3a-4358-94d2-5375be0cae89
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4281511541 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_alert_test.4281511541
Directory /workspace/33.gpio_alert_test/latest

Test location /workspace/coverage/default/33.gpio_dout_din_regs_random_rw.4152447592
Short name T271
Test name
Test status
Simulation time 41800512 ps
CPU time 0.72 seconds
Started Apr 18 12:31:37 PM PDT 24
Finished Apr 18 12:31:39 PM PDT 24
Peak memory 194144 kb
Host smart-53fab42d-27dc-4217-af06-02f7aa9719cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4152447592 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_dout_din_regs_random_rw.4152447592
Directory /workspace/33.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/33.gpio_filter_stress.3750017526
Short name T210
Test name
Test status
Simulation time 4539260549 ps
CPU time 13.57 seconds
Started Apr 18 12:31:33 PM PDT 24
Finished Apr 18 12:31:47 PM PDT 24
Peak memory 196780 kb
Host smart-d1fd4ad8-9f29-49e4-a42c-42d665cfb9b0
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3750017526 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_filter_stre
ss.3750017526
Directory /workspace/33.gpio_filter_stress/latest

Test location /workspace/coverage/default/33.gpio_full_random.4191305540
Short name T146
Test name
Test status
Simulation time 79141151 ps
CPU time 0.73 seconds
Started Apr 18 12:31:36 PM PDT 24
Finished Apr 18 12:31:38 PM PDT 24
Peak memory 195816 kb
Host smart-b0aee3a6-30f4-471f-be1d-9356a2c0dad3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4191305540 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_full_random.4191305540
Directory /workspace/33.gpio_full_random/latest

Test location /workspace/coverage/default/33.gpio_intr_rand_pgm.1228917802
Short name T491
Test name
Test status
Simulation time 427870704 ps
CPU time 1.42 seconds
Started Apr 18 12:31:33 PM PDT 24
Finished Apr 18 12:31:35 PM PDT 24
Peak memory 195740 kb
Host smart-a1eda877-54dd-45d3-aa0b-2689569d91d6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1228917802 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_intr_rand_pgm.1228917802
Directory /workspace/33.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/33.gpio_intr_with_filter_rand_intr_event.1920771777
Short name T623
Test name
Test status
Simulation time 113202281 ps
CPU time 3.53 seconds
Started Apr 18 12:31:26 PM PDT 24
Finished Apr 18 12:31:31 PM PDT 24
Peak memory 197992 kb
Host smart-55d72e84-354d-4010-8245-05d676baf335
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1920771777 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 33.gpio_intr_with_filter_rand_intr_event.1920771777
Directory /workspace/33.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/33.gpio_rand_intr_trigger.3415733522
Short name T501
Test name
Test status
Simulation time 57069005 ps
CPU time 1.27 seconds
Started Apr 18 12:31:26 PM PDT 24
Finished Apr 18 12:31:29 PM PDT 24
Peak memory 196932 kb
Host smart-03fe7bfe-f66b-4878-b692-094bcff0b121
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3415733522 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_rand_intr_trigger
.3415733522
Directory /workspace/33.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/33.gpio_random_dout_din.56423881
Short name T346
Test name
Test status
Simulation time 157025689 ps
CPU time 1.06 seconds
Started Apr 18 12:31:27 PM PDT 24
Finished Apr 18 12:31:29 PM PDT 24
Peak memory 195896 kb
Host smart-640176cc-790a-4cee-9150-497ddb06b2ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=56423881 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_random_dout_din.56423881
Directory /workspace/33.gpio_random_dout_din/latest

Test location /workspace/coverage/default/33.gpio_random_dout_din_no_pullup_pulldown.689431572
Short name T368
Test name
Test status
Simulation time 29796725 ps
CPU time 1.17 seconds
Started Apr 18 12:31:27 PM PDT 24
Finished Apr 18 12:31:29 PM PDT 24
Peak memory 196032 kb
Host smart-6e195406-2ad9-4663-9365-6987ec889b25
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=689431572 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_random_dout_din_no_pullup
_pulldown.689431572
Directory /workspace/33.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/33.gpio_random_long_reg_writes_reg_reads.4105295287
Short name T336
Test name
Test status
Simulation time 521295517 ps
CPU time 1.94 seconds
Started Apr 18 12:31:37 PM PDT 24
Finished Apr 18 12:31:40 PM PDT 24
Peak memory 198012 kb
Host smart-38dfab9c-b89c-4b3e-a7b8-f34e74f3469f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4105295287 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_ra
ndom_long_reg_writes_reg_reads.4105295287
Directory /workspace/33.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/33.gpio_smoke.3677574557
Short name T272
Test name
Test status
Simulation time 244964832 ps
CPU time 1.2 seconds
Started Apr 18 12:31:17 PM PDT 24
Finished Apr 18 12:31:22 PM PDT 24
Peak memory 197068 kb
Host smart-2efcacf5-51bc-44dc-a1da-e2fe444ad820
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3677574557 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_smoke.3677574557
Directory /workspace/33.gpio_smoke/latest

Test location /workspace/coverage/default/33.gpio_smoke_no_pullup_pulldown.3828503853
Short name T542
Test name
Test status
Simulation time 44113149 ps
CPU time 1.02 seconds
Started Apr 18 12:31:43 PM PDT 24
Finished Apr 18 12:31:46 PM PDT 24
Peak memory 195760 kb
Host smart-28268fcb-09f7-46d6-a86b-25e7381d5379
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3828503853 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_no_pullup_pulldown.3828503853
Directory /workspace/33.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/33.gpio_stress_all.1052583837
Short name T7
Test name
Test status
Simulation time 40496823703 ps
CPU time 120.96 seconds
Started Apr 18 12:31:42 PM PDT 24
Finished Apr 18 12:33:44 PM PDT 24
Peak memory 198064 kb
Host smart-a586d75a-32b0-483e-9e56-8e55b545cd83
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1052583837 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.
gpio_stress_all.1052583837
Directory /workspace/33.gpio_stress_all/latest

Test location /workspace/coverage/default/33.gpio_stress_all_with_rand_reset.10027156
Short name T72
Test name
Test status
Simulation time 395306638090 ps
CPU time 1364.86 seconds
Started Apr 18 12:31:33 PM PDT 24
Finished Apr 18 12:54:19 PM PDT 24
Peak memory 198184 kb
Host smart-ff9d15d0-e49a-4d34-aa83-5787706c6c78
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=10027156 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_stress_all_with_rand_reset.10027156
Directory /workspace/33.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.gpio_alert_test.2999633713
Short name T629
Test name
Test status
Simulation time 13449718 ps
CPU time 0.59 seconds
Started Apr 18 12:31:52 PM PDT 24
Finished Apr 18 12:31:53 PM PDT 24
Peak memory 194520 kb
Host smart-7e189291-646f-4689-bac4-a206e04f5438
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2999633713 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_alert_test.2999633713
Directory /workspace/34.gpio_alert_test/latest

Test location /workspace/coverage/default/34.gpio_dout_din_regs_random_rw.3370267525
Short name T687
Test name
Test status
Simulation time 26580681 ps
CPU time 0.59 seconds
Started Apr 18 12:31:41 PM PDT 24
Finished Apr 18 12:31:42 PM PDT 24
Peak memory 194564 kb
Host smart-4817db9e-9d8c-4161-9428-a01154b53de3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3370267525 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_dout_din_regs_random_rw.3370267525
Directory /workspace/34.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/34.gpio_filter_stress.2163524837
Short name T407
Test name
Test status
Simulation time 1501465562 ps
CPU time 25.03 seconds
Started Apr 18 12:31:32 PM PDT 24
Finished Apr 18 12:31:58 PM PDT 24
Peak memory 196984 kb
Host smart-1697e0e0-ac9c-4e0b-bd7d-ec1b1c6e9106
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2163524837 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_filter_stre
ss.2163524837
Directory /workspace/34.gpio_filter_stress/latest

Test location /workspace/coverage/default/34.gpio_full_random.1865826309
Short name T34
Test name
Test status
Simulation time 45210480 ps
CPU time 0.82 seconds
Started Apr 18 12:31:38 PM PDT 24
Finished Apr 18 12:31:40 PM PDT 24
Peak memory 195844 kb
Host smart-9cac438f-d384-4be1-8274-7aac2be586b7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1865826309 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_full_random.1865826309
Directory /workspace/34.gpio_full_random/latest

Test location /workspace/coverage/default/34.gpio_intr_rand_pgm.652560320
Short name T21
Test name
Test status
Simulation time 252224425 ps
CPU time 1.06 seconds
Started Apr 18 12:31:37 PM PDT 24
Finished Apr 18 12:31:39 PM PDT 24
Peak memory 196592 kb
Host smart-f8a81b5c-7fe2-469e-9796-6d35f0b35fcb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=652560320 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_intr_rand_pgm.652560320
Directory /workspace/34.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/34.gpio_intr_with_filter_rand_intr_event.3649603036
Short name T514
Test name
Test status
Simulation time 188259625 ps
CPU time 2.15 seconds
Started Apr 18 12:31:52 PM PDT 24
Finished Apr 18 12:31:56 PM PDT 24
Peak memory 197844 kb
Host smart-3cfbc339-9050-4404-bb91-28b5ce4743ac
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3649603036 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 34.gpio_intr_with_filter_rand_intr_event.3649603036
Directory /workspace/34.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/34.gpio_rand_intr_trigger.1748266961
Short name T161
Test name
Test status
Simulation time 1030531267 ps
CPU time 2.84 seconds
Started Apr 18 12:31:48 PM PDT 24
Finished Apr 18 12:31:51 PM PDT 24
Peak memory 196504 kb
Host smart-c69640f8-a196-4155-bf90-e833e62c1e10
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1748266961 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_rand_intr_trigger
.1748266961
Directory /workspace/34.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/34.gpio_random_dout_din.653901115
Short name T169
Test name
Test status
Simulation time 34449777 ps
CPU time 0.8 seconds
Started Apr 18 12:31:37 PM PDT 24
Finished Apr 18 12:31:39 PM PDT 24
Peak memory 195356 kb
Host smart-cd66b7a5-f88d-4237-a399-edae699ae53c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=653901115 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_random_dout_din.653901115
Directory /workspace/34.gpio_random_dout_din/latest

Test location /workspace/coverage/default/34.gpio_random_dout_din_no_pullup_pulldown.1216314516
Short name T352
Test name
Test status
Simulation time 431110003 ps
CPU time 1.2 seconds
Started Apr 18 12:31:28 PM PDT 24
Finished Apr 18 12:31:30 PM PDT 24
Peak memory 197132 kb
Host smart-f5011ea2-fa31-4c2b-a721-625b99766877
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1216314516 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_random_dout_din_no_pullu
p_pulldown.1216314516
Directory /workspace/34.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/34.gpio_random_long_reg_writes_reg_reads.3333600499
Short name T577
Test name
Test status
Simulation time 1118811320 ps
CPU time 4.69 seconds
Started Apr 18 12:31:28 PM PDT 24
Finished Apr 18 12:31:33 PM PDT 24
Peak memory 197936 kb
Host smart-d6088149-0de1-45f0-bc23-e00bcef6432b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3333600499 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_ra
ndom_long_reg_writes_reg_reads.3333600499
Directory /workspace/34.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/34.gpio_smoke.1940548468
Short name T315
Test name
Test status
Simulation time 366043360 ps
CPU time 1.4 seconds
Started Apr 18 12:31:20 PM PDT 24
Finished Apr 18 12:31:25 PM PDT 24
Peak memory 196820 kb
Host smart-ee1462b5-173c-4d9c-8f62-dac2c8d5b722
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1940548468 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_smoke.1940548468
Directory /workspace/34.gpio_smoke/latest

Test location /workspace/coverage/default/34.gpio_smoke_no_pullup_pulldown.519432145
Short name T562
Test name
Test status
Simulation time 183437074 ps
CPU time 0.95 seconds
Started Apr 18 12:31:41 PM PDT 24
Finished Apr 18 12:31:43 PM PDT 24
Peak memory 197100 kb
Host smart-41c5b656-dfbe-454b-9ee9-131d6c2ffb23
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=519432145 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_no_pullup_pulldown.519432145
Directory /workspace/34.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/34.gpio_stress_all.1569888929
Short name T555
Test name
Test status
Simulation time 10482733861 ps
CPU time 29.54 seconds
Started Apr 18 12:31:39 PM PDT 24
Finished Apr 18 12:32:10 PM PDT 24
Peak memory 198068 kb
Host smart-10cfa414-aa78-4eff-8e9b-e5193e7db848
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1569888929 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.
gpio_stress_all.1569888929
Directory /workspace/34.gpio_stress_all/latest

Test location /workspace/coverage/default/34.gpio_stress_all_with_rand_reset.40978644
Short name T37
Test name
Test status
Simulation time 120561039963 ps
CPU time 1234.33 seconds
Started Apr 18 12:31:47 PM PDT 24
Finished Apr 18 12:52:22 PM PDT 24
Peak memory 198104 kb
Host smart-77abc258-e343-4e9f-8daa-00935518966e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=40978644 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_stress_all_with_rand_reset.40978644
Directory /workspace/34.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.gpio_alert_test.1656323261
Short name T12
Test name
Test status
Simulation time 14840310 ps
CPU time 0.56 seconds
Started Apr 18 12:31:52 PM PDT 24
Finished Apr 18 12:31:54 PM PDT 24
Peak memory 194520 kb
Host smart-40c6437e-453c-4bde-b554-51b2fd94d4aa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1656323261 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_alert_test.1656323261
Directory /workspace/35.gpio_alert_test/latest

Test location /workspace/coverage/default/35.gpio_dout_din_regs_random_rw.4231074537
Short name T345
Test name
Test status
Simulation time 69357932 ps
CPU time 0.61 seconds
Started Apr 18 12:31:36 PM PDT 24
Finished Apr 18 12:31:37 PM PDT 24
Peak memory 193828 kb
Host smart-d6221775-6c1d-457c-bc01-581510d50267
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4231074537 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_dout_din_regs_random_rw.4231074537
Directory /workspace/35.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/35.gpio_filter_stress.3495981733
Short name T275
Test name
Test status
Simulation time 279127335 ps
CPU time 5.56 seconds
Started Apr 18 12:31:47 PM PDT 24
Finished Apr 18 12:31:53 PM PDT 24
Peak memory 197912 kb
Host smart-71af7b4b-c7da-48e9-94d8-ca7ee76c83e6
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3495981733 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_filter_stre
ss.3495981733
Directory /workspace/35.gpio_filter_stress/latest

Test location /workspace/coverage/default/35.gpio_full_random.3197028993
Short name T478
Test name
Test status
Simulation time 41845605 ps
CPU time 0.78 seconds
Started Apr 18 12:31:46 PM PDT 24
Finished Apr 18 12:31:47 PM PDT 24
Peak memory 196656 kb
Host smart-1f089d5a-6237-47a0-8fb6-bf40af975e90
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3197028993 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_full_random.3197028993
Directory /workspace/35.gpio_full_random/latest

Test location /workspace/coverage/default/35.gpio_intr_rand_pgm.1702949068
Short name T492
Test name
Test status
Simulation time 113353817 ps
CPU time 0.96 seconds
Started Apr 18 12:31:52 PM PDT 24
Finished Apr 18 12:31:54 PM PDT 24
Peak memory 196016 kb
Host smart-16927abf-4441-4063-86c0-76d8f5eeea4f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1702949068 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_intr_rand_pgm.1702949068
Directory /workspace/35.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/35.gpio_intr_with_filter_rand_intr_event.1630124163
Short name T224
Test name
Test status
Simulation time 446994063 ps
CPU time 2.94 seconds
Started Apr 18 12:31:46 PM PDT 24
Finished Apr 18 12:31:50 PM PDT 24
Peak memory 197936 kb
Host smart-b8bf45fe-d621-4450-a09c-58152bd3464e
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1630124163 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 35.gpio_intr_with_filter_rand_intr_event.1630124163
Directory /workspace/35.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/35.gpio_rand_intr_trigger.2914390700
Short name T691
Test name
Test status
Simulation time 190291723 ps
CPU time 3.43 seconds
Started Apr 18 12:31:56 PM PDT 24
Finished Apr 18 12:32:02 PM PDT 24
Peak memory 197152 kb
Host smart-7e6c148c-4ce7-42cd-b8ad-f2d3eb62bb4e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2914390700 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_rand_intr_trigger
.2914390700
Directory /workspace/35.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/35.gpio_random_dout_din.1135933148
Short name T67
Test name
Test status
Simulation time 152605140 ps
CPU time 0.94 seconds
Started Apr 18 12:32:06 PM PDT 24
Finished Apr 18 12:32:08 PM PDT 24
Peak memory 196788 kb
Host smart-bc671a02-3070-49f8-a10a-e133d987e3a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1135933148 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_random_dout_din.1135933148
Directory /workspace/35.gpio_random_dout_din/latest

Test location /workspace/coverage/default/35.gpio_random_dout_din_no_pullup_pulldown.1832219967
Short name T607
Test name
Test status
Simulation time 36953509 ps
CPU time 1.38 seconds
Started Apr 18 12:31:41 PM PDT 24
Finished Apr 18 12:31:43 PM PDT 24
Peak memory 195784 kb
Host smart-e1bdb5f4-386d-4ce5-bf73-3eb2138ea089
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1832219967 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_random_dout_din_no_pullu
p_pulldown.1832219967
Directory /workspace/35.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/35.gpio_random_long_reg_writes_reg_reads.855336334
Short name T715
Test name
Test status
Simulation time 183774278 ps
CPU time 2.15 seconds
Started Apr 18 12:31:31 PM PDT 24
Finished Apr 18 12:31:34 PM PDT 24
Peak memory 197960 kb
Host smart-d58c7311-b324-45f8-aed6-e4b452eb462c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=855336334 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_ran
dom_long_reg_writes_reg_reads.855336334
Directory /workspace/35.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/35.gpio_smoke.981728218
Short name T348
Test name
Test status
Simulation time 99722458 ps
CPU time 0.97 seconds
Started Apr 18 12:31:44 PM PDT 24
Finished Apr 18 12:31:46 PM PDT 24
Peak memory 195644 kb
Host smart-40b12cd0-6eea-4a1f-9024-25db95aa7672
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=981728218 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_smoke.981728218
Directory /workspace/35.gpio_smoke/latest

Test location /workspace/coverage/default/35.gpio_smoke_no_pullup_pulldown.4013897661
Short name T509
Test name
Test status
Simulation time 76705601 ps
CPU time 0.93 seconds
Started Apr 18 12:31:33 PM PDT 24
Finished Apr 18 12:31:34 PM PDT 24
Peak memory 195200 kb
Host smart-ca1db3c2-3274-4991-b609-29905e9757bd
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4013897661 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_no_pullup_pulldown.4013897661
Directory /workspace/35.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/35.gpio_stress_all.1268022320
Short name T700
Test name
Test status
Simulation time 5399467537 ps
CPU time 58.02 seconds
Started Apr 18 12:31:42 PM PDT 24
Finished Apr 18 12:32:40 PM PDT 24
Peak memory 198060 kb
Host smart-01ee1d40-9d00-40f3-b247-aa39739b8aef
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1268022320 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.
gpio_stress_all.1268022320
Directory /workspace/35.gpio_stress_all/latest

Test location /workspace/coverage/default/36.gpio_alert_test.581169259
Short name T557
Test name
Test status
Simulation time 46010856 ps
CPU time 0.58 seconds
Started Apr 18 12:31:41 PM PDT 24
Finished Apr 18 12:31:42 PM PDT 24
Peak memory 194012 kb
Host smart-6cbc7601-81ee-4f8d-9e5b-db49f71635be
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=581169259 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_alert_test.581169259
Directory /workspace/36.gpio_alert_test/latest

Test location /workspace/coverage/default/36.gpio_dout_din_regs_random_rw.833478470
Short name T658
Test name
Test status
Simulation time 25927220 ps
CPU time 0.69 seconds
Started Apr 18 12:31:42 PM PDT 24
Finished Apr 18 12:31:43 PM PDT 24
Peak memory 195228 kb
Host smart-2ab58286-c9ef-4197-805e-3bd10bee2b21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=833478470 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_dout_din_regs_random_rw.833478470
Directory /workspace/36.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/36.gpio_filter_stress.1061399248
Short name T297
Test name
Test status
Simulation time 123365112 ps
CPU time 5.87 seconds
Started Apr 18 12:31:40 PM PDT 24
Finished Apr 18 12:31:47 PM PDT 24
Peak memory 196784 kb
Host smart-e9d57980-3257-4a3f-b56e-d72028428ad9
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1061399248 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_filter_stre
ss.1061399248
Directory /workspace/36.gpio_filter_stress/latest

Test location /workspace/coverage/default/36.gpio_full_random.3497959260
Short name T625
Test name
Test status
Simulation time 142813377 ps
CPU time 0.94 seconds
Started Apr 18 12:31:35 PM PDT 24
Finished Apr 18 12:31:37 PM PDT 24
Peak memory 196956 kb
Host smart-7cff47d3-8c61-47da-a1c4-0ce02c1da94b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3497959260 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_full_random.3497959260
Directory /workspace/36.gpio_full_random/latest

Test location /workspace/coverage/default/36.gpio_intr_rand_pgm.3179326340
Short name T394
Test name
Test status
Simulation time 37909439 ps
CPU time 1.05 seconds
Started Apr 18 12:31:57 PM PDT 24
Finished Apr 18 12:32:01 PM PDT 24
Peak memory 195748 kb
Host smart-72dccd6d-56f6-4aa5-bec9-ad17f1f54dec
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3179326340 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_intr_rand_pgm.3179326340
Directory /workspace/36.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/36.gpio_intr_with_filter_rand_intr_event.1441933446
Short name T270
Test name
Test status
Simulation time 132730350 ps
CPU time 1.58 seconds
Started Apr 18 12:31:40 PM PDT 24
Finished Apr 18 12:31:43 PM PDT 24
Peak memory 196876 kb
Host smart-40a764db-4a31-46bc-b63a-b0cae5daba4b
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1441933446 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 36.gpio_intr_with_filter_rand_intr_event.1441933446
Directory /workspace/36.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/36.gpio_rand_intr_trigger.1784876387
Short name T590
Test name
Test status
Simulation time 83606291 ps
CPU time 1.92 seconds
Started Apr 18 12:31:43 PM PDT 24
Finished Apr 18 12:31:46 PM PDT 24
Peak memory 195912 kb
Host smart-00e8644e-d0e6-4af2-a064-db003c8ca75f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1784876387 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_rand_intr_trigger
.1784876387
Directory /workspace/36.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/36.gpio_random_dout_din.3296024003
Short name T704
Test name
Test status
Simulation time 54018967 ps
CPU time 1.26 seconds
Started Apr 18 12:31:48 PM PDT 24
Finished Apr 18 12:31:50 PM PDT 24
Peak memory 196444 kb
Host smart-827e1da8-b4f4-4407-a78f-53075ea81369
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3296024003 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_random_dout_din.3296024003
Directory /workspace/36.gpio_random_dout_din/latest

Test location /workspace/coverage/default/36.gpio_random_dout_din_no_pullup_pulldown.707145129
Short name T467
Test name
Test status
Simulation time 205587261 ps
CPU time 1.18 seconds
Started Apr 18 12:31:51 PM PDT 24
Finished Apr 18 12:31:53 PM PDT 24
Peak memory 196732 kb
Host smart-397a94b1-aab2-4756-a835-2c7b9cb34004
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=707145129 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_random_dout_din_no_pullup
_pulldown.707145129
Directory /workspace/36.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/36.gpio_random_long_reg_writes_reg_reads.2701888081
Short name T558
Test name
Test status
Simulation time 636099756 ps
CPU time 2.52 seconds
Started Apr 18 12:31:37 PM PDT 24
Finished Apr 18 12:31:40 PM PDT 24
Peak memory 197876 kb
Host smart-e8cb3685-dce4-47e0-a279-7ed166a5c9f9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2701888081 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_ra
ndom_long_reg_writes_reg_reads.2701888081
Directory /workspace/36.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/36.gpio_smoke.4272709975
Short name T668
Test name
Test status
Simulation time 151501907 ps
CPU time 1.17 seconds
Started Apr 18 12:31:46 PM PDT 24
Finished Apr 18 12:31:48 PM PDT 24
Peak memory 196576 kb
Host smart-efa0f148-b878-4989-8ee5-fa6abb7a3d28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4272709975 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_smoke.4272709975
Directory /workspace/36.gpio_smoke/latest

Test location /workspace/coverage/default/36.gpio_smoke_no_pullup_pulldown.1559206563
Short name T295
Test name
Test status
Simulation time 57906683 ps
CPU time 1.23 seconds
Started Apr 18 12:31:38 PM PDT 24
Finished Apr 18 12:31:40 PM PDT 24
Peak memory 196344 kb
Host smart-546ee228-f358-4e38-9be3-5ddd46a913c7
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1559206563 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_no_pullup_pulldown.1559206563
Directory /workspace/36.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/36.gpio_stress_all.1339721899
Short name T602
Test name
Test status
Simulation time 6996048222 ps
CPU time 170.79 seconds
Started Apr 18 12:31:43 PM PDT 24
Finished Apr 18 12:34:35 PM PDT 24
Peak memory 198100 kb
Host smart-8a4f869c-28f0-4c80-977a-20684af408c9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1339721899 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.
gpio_stress_all.1339721899
Directory /workspace/36.gpio_stress_all/latest

Test location /workspace/coverage/default/37.gpio_alert_test.2062555785
Short name T543
Test name
Test status
Simulation time 27619081 ps
CPU time 0.58 seconds
Started Apr 18 12:31:47 PM PDT 24
Finished Apr 18 12:31:48 PM PDT 24
Peak memory 193832 kb
Host smart-5d3efb94-c636-4c43-82e1-ed53585c0998
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2062555785 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_alert_test.2062555785
Directory /workspace/37.gpio_alert_test/latest

Test location /workspace/coverage/default/37.gpio_dout_din_regs_random_rw.2168099348
Short name T522
Test name
Test status
Simulation time 31750739 ps
CPU time 0.77 seconds
Started Apr 18 12:31:47 PM PDT 24
Finished Apr 18 12:31:48 PM PDT 24
Peak memory 196064 kb
Host smart-aaa2fb50-ab72-4242-8d40-06ae7add7cd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2168099348 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_dout_din_regs_random_rw.2168099348
Directory /workspace/37.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/37.gpio_filter_stress.439126827
Short name T199
Test name
Test status
Simulation time 6166591171 ps
CPU time 10.83 seconds
Started Apr 18 12:31:50 PM PDT 24
Finished Apr 18 12:32:02 PM PDT 24
Peak memory 196544 kb
Host smart-204bad80-2536-4ac1-9b2b-c0709fdc7921
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=439126827 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_filter_stres
s.439126827
Directory /workspace/37.gpio_filter_stress/latest

Test location /workspace/coverage/default/37.gpio_full_random.3434303701
Short name T216
Test name
Test status
Simulation time 183468773 ps
CPU time 0.74 seconds
Started Apr 18 12:31:56 PM PDT 24
Finished Apr 18 12:32:00 PM PDT 24
Peak memory 195748 kb
Host smart-e101c76b-2e09-4880-ba56-99443db43722
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3434303701 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_full_random.3434303701
Directory /workspace/37.gpio_full_random/latest

Test location /workspace/coverage/default/37.gpio_intr_rand_pgm.3545889351
Short name T116
Test name
Test status
Simulation time 259649969 ps
CPU time 1.16 seconds
Started Apr 18 12:31:53 PM PDT 24
Finished Apr 18 12:31:55 PM PDT 24
Peak memory 196104 kb
Host smart-afdd528a-be70-4a03-9a0c-cd8dfc71a5b7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3545889351 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_intr_rand_pgm.3545889351
Directory /workspace/37.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/37.gpio_intr_with_filter_rand_intr_event.3081791043
Short name T689
Test name
Test status
Simulation time 315094072 ps
CPU time 3.21 seconds
Started Apr 18 12:31:44 PM PDT 24
Finished Apr 18 12:31:48 PM PDT 24
Peak memory 198136 kb
Host smart-1a30909e-13dd-460a-97fb-4e6a21a3e541
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3081791043 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 37.gpio_intr_with_filter_rand_intr_event.3081791043
Directory /workspace/37.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/37.gpio_rand_intr_trigger.3051297275
Short name T503
Test name
Test status
Simulation time 238278003 ps
CPU time 2.02 seconds
Started Apr 18 12:31:51 PM PDT 24
Finished Apr 18 12:31:54 PM PDT 24
Peak memory 196012 kb
Host smart-64157bc8-731c-4f0e-a498-b0e173d67139
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3051297275 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_rand_intr_trigger
.3051297275
Directory /workspace/37.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/37.gpio_random_dout_din.2279519982
Short name T264
Test name
Test status
Simulation time 479698424 ps
CPU time 1.27 seconds
Started Apr 18 12:31:56 PM PDT 24
Finished Apr 18 12:32:00 PM PDT 24
Peak memory 197116 kb
Host smart-be325ba7-4260-4b04-8bcb-e45506dde4bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2279519982 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_random_dout_din.2279519982
Directory /workspace/37.gpio_random_dout_din/latest

Test location /workspace/coverage/default/37.gpio_random_dout_din_no_pullup_pulldown.113612766
Short name T548
Test name
Test status
Simulation time 117303690 ps
CPU time 1.24 seconds
Started Apr 18 12:31:51 PM PDT 24
Finished Apr 18 12:31:53 PM PDT 24
Peak memory 198056 kb
Host smart-f682452d-9c41-4a19-a468-6c3064abd4a2
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113612766 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_random_dout_din_no_pullup
_pulldown.113612766
Directory /workspace/37.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/37.gpio_random_long_reg_writes_reg_reads.3566599486
Short name T306
Test name
Test status
Simulation time 1287617973 ps
CPU time 5.31 seconds
Started Apr 18 12:31:58 PM PDT 24
Finished Apr 18 12:32:07 PM PDT 24
Peak memory 197912 kb
Host smart-df909838-8138-45c8-ba1f-cd116c695f90
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3566599486 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_ra
ndom_long_reg_writes_reg_reads.3566599486
Directory /workspace/37.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/37.gpio_smoke.604196308
Short name T578
Test name
Test status
Simulation time 53289448 ps
CPU time 1.24 seconds
Started Apr 18 12:31:53 PM PDT 24
Finished Apr 18 12:31:56 PM PDT 24
Peak memory 195748 kb
Host smart-26a019ef-99b3-49cf-b5f6-c7af18b3d5a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=604196308 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_smoke.604196308
Directory /workspace/37.gpio_smoke/latest

Test location /workspace/coverage/default/37.gpio_smoke_no_pullup_pulldown.375530774
Short name T312
Test name
Test status
Simulation time 36118574 ps
CPU time 1.07 seconds
Started Apr 18 12:31:43 PM PDT 24
Finished Apr 18 12:31:45 PM PDT 24
Peak memory 196444 kb
Host smart-1099f238-0b1c-4f45-bfc1-8205373ae0e3
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=375530774 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_no_pullup_pulldown.375530774
Directory /workspace/37.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/37.gpio_stress_all.2324133113
Short name T107
Test name
Test status
Simulation time 35218295080 ps
CPU time 137.85 seconds
Started Apr 18 12:31:50 PM PDT 24
Finished Apr 18 12:34:09 PM PDT 24
Peak memory 198180 kb
Host smart-d02e1a91-e48e-4778-9713-f227abd5014e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2324133113 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.
gpio_stress_all.2324133113
Directory /workspace/37.gpio_stress_all/latest

Test location /workspace/coverage/default/38.gpio_alert_test.1710086660
Short name T248
Test name
Test status
Simulation time 12680520 ps
CPU time 0.57 seconds
Started Apr 18 12:31:51 PM PDT 24
Finished Apr 18 12:31:52 PM PDT 24
Peak memory 194852 kb
Host smart-b134a45b-c7a0-480b-bad4-3c6e5c1084ea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1710086660 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_alert_test.1710086660
Directory /workspace/38.gpio_alert_test/latest

Test location /workspace/coverage/default/38.gpio_dout_din_regs_random_rw.2760501773
Short name T159
Test name
Test status
Simulation time 50468095 ps
CPU time 0.98 seconds
Started Apr 18 12:31:56 PM PDT 24
Finished Apr 18 12:31:59 PM PDT 24
Peak memory 195608 kb
Host smart-38920457-0562-4151-a677-04d29815f1de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2760501773 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_dout_din_regs_random_rw.2760501773
Directory /workspace/38.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/38.gpio_filter_stress.4187665155
Short name T341
Test name
Test status
Simulation time 2408728229 ps
CPU time 21.59 seconds
Started Apr 18 12:31:57 PM PDT 24
Finished Apr 18 12:32:21 PM PDT 24
Peak memory 196860 kb
Host smart-2a64f5d9-5395-41b0-8730-d1a7d848fb2e
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4187665155 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_filter_stre
ss.4187665155
Directory /workspace/38.gpio_filter_stress/latest

Test location /workspace/coverage/default/38.gpio_full_random.2855230329
Short name T339
Test name
Test status
Simulation time 51543842 ps
CPU time 0.79 seconds
Started Apr 18 12:31:48 PM PDT 24
Finished Apr 18 12:31:49 PM PDT 24
Peak memory 195780 kb
Host smart-76363411-716b-4c5d-8354-f5c7b19a047f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2855230329 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_full_random.2855230329
Directory /workspace/38.gpio_full_random/latest

Test location /workspace/coverage/default/38.gpio_intr_rand_pgm.1848270405
Short name T644
Test name
Test status
Simulation time 213255803 ps
CPU time 1.31 seconds
Started Apr 18 12:31:55 PM PDT 24
Finished Apr 18 12:31:59 PM PDT 24
Peak memory 197972 kb
Host smart-bfd36e60-3dd9-41b9-9c98-5356b7110f15
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1848270405 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_intr_rand_pgm.1848270405
Directory /workspace/38.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/38.gpio_intr_with_filter_rand_intr_event.3974912259
Short name T244
Test name
Test status
Simulation time 166004513 ps
CPU time 1.86 seconds
Started Apr 18 12:31:47 PM PDT 24
Finished Apr 18 12:31:50 PM PDT 24
Peak memory 197956 kb
Host smart-88807d23-c25d-425a-b043-4238eb27821f
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3974912259 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 38.gpio_intr_with_filter_rand_intr_event.3974912259
Directory /workspace/38.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/38.gpio_rand_intr_trigger.2495275624
Short name T714
Test name
Test status
Simulation time 120206026 ps
CPU time 3.58 seconds
Started Apr 18 12:31:43 PM PDT 24
Finished Apr 18 12:31:48 PM PDT 24
Peak memory 198000 kb
Host smart-618f82e9-d249-424d-8475-f8228ae6a05d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2495275624 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_rand_intr_trigger
.2495275624
Directory /workspace/38.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/38.gpio_random_dout_din.3392423469
Short name T149
Test name
Test status
Simulation time 114167919 ps
CPU time 1.31 seconds
Started Apr 18 12:31:44 PM PDT 24
Finished Apr 18 12:31:47 PM PDT 24
Peak memory 196464 kb
Host smart-48629b28-2e45-48e3-812b-90b6ff2cc928
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3392423469 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_random_dout_din.3392423469
Directory /workspace/38.gpio_random_dout_din/latest

Test location /workspace/coverage/default/38.gpio_random_dout_din_no_pullup_pulldown.2229389439
Short name T481
Test name
Test status
Simulation time 173870783 ps
CPU time 1.14 seconds
Started Apr 18 12:31:53 PM PDT 24
Finished Apr 18 12:31:55 PM PDT 24
Peak memory 196428 kb
Host smart-7173e9b9-d173-4afc-a648-415a29d2485b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2229389439 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_random_dout_din_no_pullu
p_pulldown.2229389439
Directory /workspace/38.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/38.gpio_random_long_reg_writes_reg_reads.3111639392
Short name T605
Test name
Test status
Simulation time 891572847 ps
CPU time 2.9 seconds
Started Apr 18 12:31:46 PM PDT 24
Finished Apr 18 12:31:50 PM PDT 24
Peak memory 197980 kb
Host smart-8f07c316-fbc8-44bb-87fb-3ac859593b50
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3111639392 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_ra
ndom_long_reg_writes_reg_reads.3111639392
Directory /workspace/38.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/38.gpio_smoke.2072767154
Short name T127
Test name
Test status
Simulation time 122025898 ps
CPU time 1.11 seconds
Started Apr 18 12:31:54 PM PDT 24
Finished Apr 18 12:32:03 PM PDT 24
Peak memory 195772 kb
Host smart-d29c00e0-b9af-4a49-9ca1-c6a1509bc974
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2072767154 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_smoke.2072767154
Directory /workspace/38.gpio_smoke/latest

Test location /workspace/coverage/default/38.gpio_smoke_no_pullup_pulldown.2656047987
Short name T445
Test name
Test status
Simulation time 257663740 ps
CPU time 1.14 seconds
Started Apr 18 12:31:46 PM PDT 24
Finished Apr 18 12:31:48 PM PDT 24
Peak memory 196464 kb
Host smart-faf3587e-5920-4640-a136-cad78dfdab2a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2656047987 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_no_pullup_pulldown.2656047987
Directory /workspace/38.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/38.gpio_stress_all.3067468866
Short name T337
Test name
Test status
Simulation time 16606413707 ps
CPU time 163.42 seconds
Started Apr 18 12:31:53 PM PDT 24
Finished Apr 18 12:34:38 PM PDT 24
Peak memory 198028 kb
Host smart-8c4afc94-868d-448c-8f55-a579f7646849
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3067468866 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.
gpio_stress_all.3067468866
Directory /workspace/38.gpio_stress_all/latest

Test location /workspace/coverage/default/39.gpio_alert_test.172521835
Short name T154
Test name
Test status
Simulation time 21397662 ps
CPU time 0.59 seconds
Started Apr 18 12:32:42 PM PDT 24
Finished Apr 18 12:32:44 PM PDT 24
Peak memory 193820 kb
Host smart-45d6604d-383a-4d47-a132-90048ff715ad
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=172521835 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_alert_test.172521835
Directory /workspace/39.gpio_alert_test/latest

Test location /workspace/coverage/default/39.gpio_dout_din_regs_random_rw.554943113
Short name T670
Test name
Test status
Simulation time 73690834 ps
CPU time 0.71 seconds
Started Apr 18 12:31:52 PM PDT 24
Finished Apr 18 12:31:54 PM PDT 24
Peak memory 195828 kb
Host smart-24d6f313-6a6e-4b13-96f4-9e3fab016111
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=554943113 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_dout_din_regs_random_rw.554943113
Directory /workspace/39.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/39.gpio_filter_stress.275348954
Short name T340
Test name
Test status
Simulation time 789514124 ps
CPU time 22.62 seconds
Started Apr 18 12:31:42 PM PDT 24
Finished Apr 18 12:32:06 PM PDT 24
Peak memory 196920 kb
Host smart-71930a93-8870-4f68-b000-bcc015179c94
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=275348954 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_filter_stres
s.275348954
Directory /workspace/39.gpio_filter_stress/latest

Test location /workspace/coverage/default/39.gpio_full_random.2580177807
Short name T330
Test name
Test status
Simulation time 48332476 ps
CPU time 0.78 seconds
Started Apr 18 12:31:54 PM PDT 24
Finished Apr 18 12:31:57 PM PDT 24
Peak memory 196472 kb
Host smart-74ff2f71-7949-41a3-ab4d-d4ec805bcad4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2580177807 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_full_random.2580177807
Directory /workspace/39.gpio_full_random/latest

Test location /workspace/coverage/default/39.gpio_intr_rand_pgm.736351431
Short name T322
Test name
Test status
Simulation time 46474522 ps
CPU time 1.07 seconds
Started Apr 18 12:31:49 PM PDT 24
Finished Apr 18 12:31:51 PM PDT 24
Peak memory 196388 kb
Host smart-2f81e451-2f73-480a-8163-2f075b9965fa
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=736351431 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_intr_rand_pgm.736351431
Directory /workspace/39.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/39.gpio_intr_with_filter_rand_intr_event.3444782992
Short name T239
Test name
Test status
Simulation time 82658219 ps
CPU time 2.99 seconds
Started Apr 18 12:32:00 PM PDT 24
Finished Apr 18 12:32:06 PM PDT 24
Peak memory 198100 kb
Host smart-7d224563-44e5-49ef-873d-8cc35b579c44
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3444782992 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 39.gpio_intr_with_filter_rand_intr_event.3444782992
Directory /workspace/39.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/39.gpio_rand_intr_trigger.938038614
Short name T512
Test name
Test status
Simulation time 309694541 ps
CPU time 3.28 seconds
Started Apr 18 12:31:41 PM PDT 24
Finished Apr 18 12:31:46 PM PDT 24
Peak memory 196588 kb
Host smart-07278fa0-c448-46e4-bb66-466a0812b565
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=938038614 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_rand_intr_trigger.
938038614
Directory /workspace/39.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/39.gpio_random_dout_din.435487915
Short name T379
Test name
Test status
Simulation time 43231706 ps
CPU time 0.73 seconds
Started Apr 18 12:31:50 PM PDT 24
Finished Apr 18 12:31:51 PM PDT 24
Peak memory 196072 kb
Host smart-45361a90-9c10-4a63-99f6-4d02556b3d15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=435487915 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_random_dout_din.435487915
Directory /workspace/39.gpio_random_dout_din/latest

Test location /workspace/coverage/default/39.gpio_random_dout_din_no_pullup_pulldown.3804643265
Short name T298
Test name
Test status
Simulation time 61436026 ps
CPU time 1.14 seconds
Started Apr 18 12:31:58 PM PDT 24
Finished Apr 18 12:32:02 PM PDT 24
Peak memory 196952 kb
Host smart-25c74757-1564-4409-88cd-2189787e36d7
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3804643265 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_random_dout_din_no_pullu
p_pulldown.3804643265
Directory /workspace/39.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/39.gpio_random_long_reg_writes_reg_reads.2697149694
Short name T261
Test name
Test status
Simulation time 294629709 ps
CPU time 3.97 seconds
Started Apr 18 12:31:51 PM PDT 24
Finished Apr 18 12:31:55 PM PDT 24
Peak memory 197904 kb
Host smart-d38193c3-f3d6-4161-a84b-7ee482ce49b0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2697149694 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_ra
ndom_long_reg_writes_reg_reads.2697149694
Directory /workspace/39.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/39.gpio_smoke.1614788173
Short name T153
Test name
Test status
Simulation time 201060625 ps
CPU time 0.95 seconds
Started Apr 18 12:31:54 PM PDT 24
Finished Apr 18 12:31:56 PM PDT 24
Peak memory 196316 kb
Host smart-8c64067f-1cdc-4ade-a8b9-b1170efcb535
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1614788173 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_smoke.1614788173
Directory /workspace/39.gpio_smoke/latest

Test location /workspace/coverage/default/39.gpio_smoke_no_pullup_pulldown.2221269079
Short name T168
Test name
Test status
Simulation time 64396035 ps
CPU time 0.84 seconds
Started Apr 18 12:31:50 PM PDT 24
Finished Apr 18 12:31:51 PM PDT 24
Peak memory 196108 kb
Host smart-b0b9e9bb-f273-4568-8541-ddab6e44da0a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2221269079 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_no_pullup_pulldown.2221269079
Directory /workspace/39.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/39.gpio_stress_all.3126787290
Short name T126
Test name
Test status
Simulation time 8413625454 ps
CPU time 122.14 seconds
Started Apr 18 12:32:00 PM PDT 24
Finished Apr 18 12:34:06 PM PDT 24
Peak memory 198104 kb
Host smart-f2e37ea6-6baa-4c09-9617-3c3bf913233d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3126787290 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.
gpio_stress_all.3126787290
Directory /workspace/39.gpio_stress_all/latest

Test location /workspace/coverage/default/4.gpio_alert_test.1051662833
Short name T119
Test name
Test status
Simulation time 14927307 ps
CPU time 0.55 seconds
Started Apr 18 12:30:35 PM PDT 24
Finished Apr 18 12:30:36 PM PDT 24
Peak memory 193816 kb
Host smart-7dbaf274-5cc9-45e6-887d-c8c6b681078f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1051662833 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_alert_test.1051662833
Directory /workspace/4.gpio_alert_test/latest

Test location /workspace/coverage/default/4.gpio_dout_din_regs_random_rw.2961534042
Short name T498
Test name
Test status
Simulation time 185067245 ps
CPU time 0.84 seconds
Started Apr 18 12:30:34 PM PDT 24
Finished Apr 18 12:30:36 PM PDT 24
Peak memory 196396 kb
Host smart-2f1ddd63-9334-4e91-972a-9147237f6859
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2961534042 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_dout_din_regs_random_rw.2961534042
Directory /workspace/4.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/4.gpio_filter_stress.1054595936
Short name T398
Test name
Test status
Simulation time 122461271 ps
CPU time 6.29 seconds
Started Apr 18 12:30:49 PM PDT 24
Finished Apr 18 12:30:57 PM PDT 24
Peak memory 196816 kb
Host smart-024f1fe0-6bd3-4869-8ac9-c8bf5fcffd9a
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1054595936 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_filter_stres
s.1054595936
Directory /workspace/4.gpio_filter_stress/latest

Test location /workspace/coverage/default/4.gpio_full_random.994615698
Short name T19
Test name
Test status
Simulation time 73111396 ps
CPU time 0.93 seconds
Started Apr 18 12:31:55 PM PDT 24
Finished Apr 18 12:31:58 PM PDT 24
Peak memory 196876 kb
Host smart-2dae9e8e-8122-4777-9193-e3e81c77d4b8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=994615698 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_full_random.994615698
Directory /workspace/4.gpio_full_random/latest

Test location /workspace/coverage/default/4.gpio_intr_rand_pgm.2780947977
Short name T142
Test name
Test status
Simulation time 77374576 ps
CPU time 1.24 seconds
Started Apr 18 12:30:44 PM PDT 24
Finished Apr 18 12:30:46 PM PDT 24
Peak memory 196580 kb
Host smart-65d56fc6-6768-4232-862e-2bb54f22fdcc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2780947977 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_intr_rand_pgm.2780947977
Directory /workspace/4.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/4.gpio_intr_with_filter_rand_intr_event.2654014557
Short name T386
Test name
Test status
Simulation time 52977596 ps
CPU time 1.97 seconds
Started Apr 18 12:30:55 PM PDT 24
Finished Apr 18 12:30:59 PM PDT 24
Peak memory 198552 kb
Host smart-99b01d2f-ea66-43d2-9634-4c59b98ec8cf
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2654014557 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 4.gpio_intr_with_filter_rand_intr_event.2654014557
Directory /workspace/4.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/4.gpio_rand_intr_trigger.2783647542
Short name T706
Test name
Test status
Simulation time 70371350 ps
CPU time 1.68 seconds
Started Apr 18 12:30:43 PM PDT 24
Finished Apr 18 12:30:45 PM PDT 24
Peak memory 196116 kb
Host smart-da1949fb-2b68-4df0-8a49-f31976904163
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2783647542 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_rand_intr_trigger.
2783647542
Directory /workspace/4.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/4.gpio_random_dout_din.2207435689
Short name T474
Test name
Test status
Simulation time 63139727 ps
CPU time 1.29 seconds
Started Apr 18 12:30:55 PM PDT 24
Finished Apr 18 12:30:57 PM PDT 24
Peak memory 197012 kb
Host smart-84c6a053-f830-4672-aa9e-a5d37b2c0e4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2207435689 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_random_dout_din.2207435689
Directory /workspace/4.gpio_random_dout_din/latest

Test location /workspace/coverage/default/4.gpio_random_dout_din_no_pullup_pulldown.3222345336
Short name T457
Test name
Test status
Simulation time 67161329 ps
CPU time 0.71 seconds
Started Apr 18 12:30:27 PM PDT 24
Finished Apr 18 12:30:29 PM PDT 24
Peak memory 195268 kb
Host smart-035b176c-245d-406d-88e8-9254217a1ee8
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3222345336 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_random_dout_din_no_pullup
_pulldown.3222345336
Directory /workspace/4.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/4.gpio_random_long_reg_writes_reg_reads.2537764922
Short name T523
Test name
Test status
Simulation time 367257319 ps
CPU time 6.21 seconds
Started Apr 18 12:30:34 PM PDT 24
Finished Apr 18 12:30:41 PM PDT 24
Peak memory 198008 kb
Host smart-8e665b1a-33da-44aa-80cb-c9d4b1e625b3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2537764922 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_ran
dom_long_reg_writes_reg_reads.2537764922
Directory /workspace/4.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/4.gpio_sec_cm.433824527
Short name T51
Test name
Test status
Simulation time 225605215 ps
CPU time 0.94 seconds
Started Apr 18 12:30:25 PM PDT 24
Finished Apr 18 12:30:28 PM PDT 24
Peak memory 213692 kb
Host smart-e64f6488-5307-4e36-a653-c31785301a3e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=433824527 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_sec_cm.433824527
Directory /workspace/4.gpio_sec_cm/latest

Test location /workspace/coverage/default/4.gpio_smoke.1763661046
Short name T683
Test name
Test status
Simulation time 174033578 ps
CPU time 0.89 seconds
Started Apr 18 12:30:22 PM PDT 24
Finished Apr 18 12:30:24 PM PDT 24
Peak memory 196388 kb
Host smart-84324a9d-743b-4ff7-9a7a-bdc2e195fc28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1763661046 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_smoke.1763661046
Directory /workspace/4.gpio_smoke/latest

Test location /workspace/coverage/default/4.gpio_smoke_no_pullup_pulldown.3698149720
Short name T236
Test name
Test status
Simulation time 61917461 ps
CPU time 1.13 seconds
Started Apr 18 12:30:39 PM PDT 24
Finished Apr 18 12:30:40 PM PDT 24
Peak memory 196520 kb
Host smart-a96773f3-c39c-4dfe-b55d-0140b358cb19
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3698149720 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_no_pullup_pulldown.3698149720
Directory /workspace/4.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/4.gpio_stress_all.561240143
Short name T150
Test name
Test status
Simulation time 17124453154 ps
CPU time 102.98 seconds
Started Apr 18 12:30:38 PM PDT 24
Finished Apr 18 12:32:21 PM PDT 24
Peak memory 198016 kb
Host smart-f76f9a7f-77a5-4706-9c9e-65ceaafdfc7e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=561240143 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gp
io_stress_all.561240143
Directory /workspace/4.gpio_stress_all/latest

Test location /workspace/coverage/default/40.gpio_alert_test.4121274422
Short name T253
Test name
Test status
Simulation time 31979868 ps
CPU time 0.57 seconds
Started Apr 18 12:31:49 PM PDT 24
Finished Apr 18 12:31:50 PM PDT 24
Peak memory 193944 kb
Host smart-5f9b9d3b-5ad9-4307-9586-acecae1db8c3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4121274422 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_alert_test.4121274422
Directory /workspace/40.gpio_alert_test/latest

Test location /workspace/coverage/default/40.gpio_dout_din_regs_random_rw.2858670550
Short name T147
Test name
Test status
Simulation time 82910333 ps
CPU time 0.69 seconds
Started Apr 18 12:31:57 PM PDT 24
Finished Apr 18 12:32:00 PM PDT 24
Peak memory 194052 kb
Host smart-c915dcd2-b4a3-409c-b6d0-05319c65ce62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2858670550 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_dout_din_regs_random_rw.2858670550
Directory /workspace/40.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/40.gpio_filter_stress.3756691262
Short name T377
Test name
Test status
Simulation time 225258287 ps
CPU time 5.69 seconds
Started Apr 18 12:31:59 PM PDT 24
Finished Apr 18 12:32:08 PM PDT 24
Peak memory 197080 kb
Host smart-658e8aef-a282-4112-ab1c-2b49071327af
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3756691262 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_filter_stre
ss.3756691262
Directory /workspace/40.gpio_filter_stress/latest

Test location /workspace/coverage/default/40.gpio_full_random.160916680
Short name T121
Test name
Test status
Simulation time 377856409 ps
CPU time 0.99 seconds
Started Apr 18 12:31:50 PM PDT 24
Finished Apr 18 12:31:57 PM PDT 24
Peak memory 197864 kb
Host smart-77f38d3e-7fe7-476b-b1b1-c90c2f754e27
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=160916680 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_full_random.160916680
Directory /workspace/40.gpio_full_random/latest

Test location /workspace/coverage/default/40.gpio_intr_rand_pgm.3973109513
Short name T114
Test name
Test status
Simulation time 104126399 ps
CPU time 0.79 seconds
Started Apr 18 12:31:43 PM PDT 24
Finished Apr 18 12:31:44 PM PDT 24
Peak memory 195432 kb
Host smart-64b2d4ef-5667-4874-83cb-5077b824a51c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3973109513 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_intr_rand_pgm.3973109513
Directory /workspace/40.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/40.gpio_intr_with_filter_rand_intr_event.3994005899
Short name T382
Test name
Test status
Simulation time 132436897 ps
CPU time 1.54 seconds
Started Apr 18 12:31:58 PM PDT 24
Finished Apr 18 12:32:03 PM PDT 24
Peak memory 196708 kb
Host smart-ba718bf3-ccdb-46f6-9ca6-865bcc553fe5
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3994005899 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 40.gpio_intr_with_filter_rand_intr_event.3994005899
Directory /workspace/40.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/40.gpio_rand_intr_trigger.2739734860
Short name T246
Test name
Test status
Simulation time 709714678 ps
CPU time 1.45 seconds
Started Apr 18 12:31:49 PM PDT 24
Finished Apr 18 12:31:51 PM PDT 24
Peak memory 196768 kb
Host smart-89cb143b-e48e-43bb-9c44-e7cfd3792804
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2739734860 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_rand_intr_trigger
.2739734860
Directory /workspace/40.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/40.gpio_random_dout_din.3690568054
Short name T134
Test name
Test status
Simulation time 91760661 ps
CPU time 0.89 seconds
Started Apr 18 12:31:57 PM PDT 24
Finished Apr 18 12:32:00 PM PDT 24
Peak memory 196684 kb
Host smart-52d0db50-4f4e-4c6d-9e7d-4383dda0a15c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3690568054 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_random_dout_din.3690568054
Directory /workspace/40.gpio_random_dout_din/latest

Test location /workspace/coverage/default/40.gpio_random_dout_din_no_pullup_pulldown.1575593114
Short name T316
Test name
Test status
Simulation time 224363916 ps
CPU time 1.05 seconds
Started Apr 18 12:31:54 PM PDT 24
Finished Apr 18 12:31:56 PM PDT 24
Peak memory 195896 kb
Host smart-a7a5d2e5-f4bf-48d5-b40a-82ba435294f9
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1575593114 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_random_dout_din_no_pullu
p_pulldown.1575593114
Directory /workspace/40.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/40.gpio_random_long_reg_writes_reg_reads.2443480700
Short name T713
Test name
Test status
Simulation time 133119870 ps
CPU time 2.31 seconds
Started Apr 18 12:31:56 PM PDT 24
Finished Apr 18 12:32:01 PM PDT 24
Peak memory 197880 kb
Host smart-caff5439-0145-4b6d-90dd-d908cf40bf6d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2443480700 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_ra
ndom_long_reg_writes_reg_reads.2443480700
Directory /workspace/40.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/40.gpio_smoke.2623255325
Short name T137
Test name
Test status
Simulation time 81943986 ps
CPU time 1.2 seconds
Started Apr 18 12:31:54 PM PDT 24
Finished Apr 18 12:31:57 PM PDT 24
Peak memory 196716 kb
Host smart-25b39a92-c7b8-4e58-90e4-bd32d979ac29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2623255325 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_smoke.2623255325
Directory /workspace/40.gpio_smoke/latest

Test location /workspace/coverage/default/40.gpio_smoke_no_pullup_pulldown.4089415017
Short name T205
Test name
Test status
Simulation time 84521249 ps
CPU time 1.27 seconds
Started Apr 18 12:31:55 PM PDT 24
Finished Apr 18 12:31:58 PM PDT 24
Peak memory 195896 kb
Host smart-42404772-7042-4578-9610-12ebefa00504
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4089415017 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_no_pullup_pulldown.4089415017
Directory /workspace/40.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/40.gpio_stress_all.1959887301
Short name T466
Test name
Test status
Simulation time 11704500210 ps
CPU time 159.41 seconds
Started Apr 18 12:31:56 PM PDT 24
Finished Apr 18 12:34:38 PM PDT 24
Peak memory 198084 kb
Host smart-46c63858-d88b-41fd-b43d-6d62b94f40db
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1959887301 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.
gpio_stress_all.1959887301
Directory /workspace/40.gpio_stress_all/latest

Test location /workspace/coverage/default/41.gpio_alert_test.187717570
Short name T521
Test name
Test status
Simulation time 20983630 ps
CPU time 0.56 seconds
Started Apr 18 12:31:59 PM PDT 24
Finished Apr 18 12:32:03 PM PDT 24
Peak memory 193832 kb
Host smart-ae4b5715-fcc9-4ba8-b94b-daf900d61268
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=187717570 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_alert_test.187717570
Directory /workspace/41.gpio_alert_test/latest

Test location /workspace/coverage/default/41.gpio_dout_din_regs_random_rw.1913040984
Short name T296
Test name
Test status
Simulation time 21448146 ps
CPU time 0.7 seconds
Started Apr 18 12:31:54 PM PDT 24
Finished Apr 18 12:31:56 PM PDT 24
Peak memory 194240 kb
Host smart-b23a2baa-7ade-4ca8-88a2-54842076af4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1913040984 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_dout_din_regs_random_rw.1913040984
Directory /workspace/41.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/41.gpio_filter_stress.3039122828
Short name T707
Test name
Test status
Simulation time 2372617753 ps
CPU time 19.84 seconds
Started Apr 18 12:31:57 PM PDT 24
Finished Apr 18 12:32:20 PM PDT 24
Peak memory 197528 kb
Host smart-dce1337e-47e8-489d-9785-d7488f6641a5
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3039122828 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_filter_stre
ss.3039122828
Directory /workspace/41.gpio_filter_stress/latest

Test location /workspace/coverage/default/41.gpio_full_random.1005796293
Short name T304
Test name
Test status
Simulation time 62284483 ps
CPU time 1.01 seconds
Started Apr 18 12:31:58 PM PDT 24
Finished Apr 18 12:32:03 PM PDT 24
Peak memory 196564 kb
Host smart-04b832c8-508f-4695-8ea3-09c2f70f1fdb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1005796293 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_full_random.1005796293
Directory /workspace/41.gpio_full_random/latest

Test location /workspace/coverage/default/41.gpio_intr_rand_pgm.3576994177
Short name T419
Test name
Test status
Simulation time 24061433 ps
CPU time 0.64 seconds
Started Apr 18 12:31:58 PM PDT 24
Finished Apr 18 12:32:02 PM PDT 24
Peak memory 194256 kb
Host smart-14db26b0-8213-44f8-9fae-9ab0487d0197
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3576994177 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_intr_rand_pgm.3576994177
Directory /workspace/41.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/41.gpio_intr_with_filter_rand_intr_event.461132004
Short name T125
Test name
Test status
Simulation time 46084763 ps
CPU time 2.04 seconds
Started Apr 18 12:31:49 PM PDT 24
Finished Apr 18 12:31:51 PM PDT 24
Peak memory 198020 kb
Host smart-111b7de7-4b22-4dec-993d-9211614ddc01
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=461132004 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 41.gpio_intr_with_filter_rand_intr_event.461132004
Directory /workspace/41.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/41.gpio_rand_intr_trigger.4179424702
Short name T496
Test name
Test status
Simulation time 102652132 ps
CPU time 2.2 seconds
Started Apr 18 12:31:59 PM PDT 24
Finished Apr 18 12:32:05 PM PDT 24
Peak memory 196148 kb
Host smart-8e4b0662-2900-41dd-b490-7f4219749e72
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4179424702 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_rand_intr_trigger
.4179424702
Directory /workspace/41.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/41.gpio_random_dout_din.2957075617
Short name T269
Test name
Test status
Simulation time 28726703 ps
CPU time 0.75 seconds
Started Apr 18 12:31:55 PM PDT 24
Finished Apr 18 12:31:58 PM PDT 24
Peak memory 195476 kb
Host smart-aca93d79-0c27-47fa-85dc-a7daf2f7cbe0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2957075617 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_random_dout_din.2957075617
Directory /workspace/41.gpio_random_dout_din/latest

Test location /workspace/coverage/default/41.gpio_random_dout_din_no_pullup_pulldown.541173578
Short name T181
Test name
Test status
Simulation time 51294201 ps
CPU time 0.7 seconds
Started Apr 18 12:31:53 PM PDT 24
Finished Apr 18 12:31:55 PM PDT 24
Peak memory 196024 kb
Host smart-b93db668-ec9d-4e34-b684-1a2644ffca0a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=541173578 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_random_dout_din_no_pullup
_pulldown.541173578
Directory /workspace/41.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/41.gpio_random_long_reg_writes_reg_reads.358808324
Short name T267
Test name
Test status
Simulation time 384926563 ps
CPU time 4.63 seconds
Started Apr 18 12:31:59 PM PDT 24
Finished Apr 18 12:32:07 PM PDT 24
Peak memory 198000 kb
Host smart-e53daa3b-626c-454f-91b6-8439c7c450c3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=358808324 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_ran
dom_long_reg_writes_reg_reads.358808324
Directory /workspace/41.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/41.gpio_smoke.3866172479
Short name T653
Test name
Test status
Simulation time 176025862 ps
CPU time 1.39 seconds
Started Apr 18 12:31:56 PM PDT 24
Finished Apr 18 12:31:59 PM PDT 24
Peak memory 196732 kb
Host smart-17d8e38f-1fc4-4d89-b0d0-62ede868ff33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3866172479 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_smoke.3866172479
Directory /workspace/41.gpio_smoke/latest

Test location /workspace/coverage/default/41.gpio_smoke_no_pullup_pulldown.563419800
Short name T307
Test name
Test status
Simulation time 71600082 ps
CPU time 0.82 seconds
Started Apr 18 12:32:00 PM PDT 24
Finished Apr 18 12:32:04 PM PDT 24
Peak memory 195256 kb
Host smart-dcebfec9-41b5-406d-89c5-f6f08c65580d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=563419800 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_no_pullup_pulldown.563419800
Directory /workspace/41.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/41.gpio_stress_all.1042026048
Short name T108
Test name
Test status
Simulation time 7585441064 ps
CPU time 104.36 seconds
Started Apr 18 12:31:55 PM PDT 24
Finished Apr 18 12:33:42 PM PDT 24
Peak memory 198064 kb
Host smart-a94bbbe0-d2a9-4a0c-bd17-c861fb70d87a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1042026048 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.
gpio_stress_all.1042026048
Directory /workspace/41.gpio_stress_all/latest

Test location /workspace/coverage/default/41.gpio_stress_all_with_rand_reset.484036201
Short name T585
Test name
Test status
Simulation time 613145477149 ps
CPU time 2428.7 seconds
Started Apr 18 12:31:55 PM PDT 24
Finished Apr 18 01:12:26 PM PDT 24
Peak memory 198088 kb
Host smart-8f038ee2-a8a2-48f1-bd56-86f0b72df2dd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=484036201 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_stress_all_with_rand_reset.484036201
Directory /workspace/41.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.gpio_alert_test.576131228
Short name T684
Test name
Test status
Simulation time 12052655 ps
CPU time 0.57 seconds
Started Apr 18 12:31:52 PM PDT 24
Finished Apr 18 12:31:54 PM PDT 24
Peak memory 193780 kb
Host smart-dedda529-6f6c-4ad4-a77a-74eca3730bfe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=576131228 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_alert_test.576131228
Directory /workspace/42.gpio_alert_test/latest

Test location /workspace/coverage/default/42.gpio_dout_din_regs_random_rw.116496256
Short name T402
Test name
Test status
Simulation time 420200813 ps
CPU time 0.93 seconds
Started Apr 18 12:31:51 PM PDT 24
Finished Apr 18 12:31:53 PM PDT 24
Peak memory 196080 kb
Host smart-cd821d37-bec2-4691-99b8-6bc71c41ba22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=116496256 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_dout_din_regs_random_rw.116496256
Directory /workspace/42.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/42.gpio_filter_stress.2855585359
Short name T151
Test name
Test status
Simulation time 453461001 ps
CPU time 5.44 seconds
Started Apr 18 12:31:56 PM PDT 24
Finished Apr 18 12:32:03 PM PDT 24
Peak memory 196960 kb
Host smart-34aaedcd-c5ac-464c-8943-d79bc1805587
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2855585359 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_filter_stre
ss.2855585359
Directory /workspace/42.gpio_filter_stress/latest

Test location /workspace/coverage/default/42.gpio_full_random.395916451
Short name T421
Test name
Test status
Simulation time 60226113 ps
CPU time 0.95 seconds
Started Apr 18 12:32:11 PM PDT 24
Finished Apr 18 12:32:14 PM PDT 24
Peak memory 196484 kb
Host smart-bf9daa66-2831-4cf8-899d-f84b8b906e47
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=395916451 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_full_random.395916451
Directory /workspace/42.gpio_full_random/latest

Test location /workspace/coverage/default/42.gpio_intr_rand_pgm.2855078171
Short name T198
Test name
Test status
Simulation time 69549954 ps
CPU time 1.29 seconds
Started Apr 18 12:31:46 PM PDT 24
Finished Apr 18 12:31:49 PM PDT 24
Peak memory 196812 kb
Host smart-204c74a9-3a3c-4b5c-8060-19d5e3c1d6b2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2855078171 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_intr_rand_pgm.2855078171
Directory /workspace/42.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/42.gpio_intr_with_filter_rand_intr_event.227059966
Short name T570
Test name
Test status
Simulation time 46421590 ps
CPU time 1.78 seconds
Started Apr 18 12:31:57 PM PDT 24
Finished Apr 18 12:32:01 PM PDT 24
Peak memory 198056 kb
Host smart-9508a203-2a3b-4ff1-91e2-b1e15d6619e7
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=227059966 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 42.gpio_intr_with_filter_rand_intr_event.227059966
Directory /workspace/42.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/42.gpio_rand_intr_trigger.240735796
Short name T502
Test name
Test status
Simulation time 697875508 ps
CPU time 3.5 seconds
Started Apr 18 12:31:57 PM PDT 24
Finished Apr 18 12:32:03 PM PDT 24
Peak memory 198016 kb
Host smart-3241fcb9-1330-4eb0-9866-3c5ec390a2f5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=240735796 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_rand_intr_trigger.
240735796
Directory /workspace/42.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/42.gpio_random_dout_din.693024914
Short name T156
Test name
Test status
Simulation time 51889885 ps
CPU time 1.25 seconds
Started Apr 18 12:31:52 PM PDT 24
Finished Apr 18 12:31:54 PM PDT 24
Peak memory 197272 kb
Host smart-9781d38f-671a-4189-beeb-61da4ac45670
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=693024914 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_random_dout_din.693024914
Directory /workspace/42.gpio_random_dout_din/latest

Test location /workspace/coverage/default/42.gpio_random_dout_din_no_pullup_pulldown.2075577814
Short name T234
Test name
Test status
Simulation time 114664749 ps
CPU time 1.29 seconds
Started Apr 18 12:31:56 PM PDT 24
Finished Apr 18 12:32:00 PM PDT 24
Peak memory 198140 kb
Host smart-c1226013-c11e-4ef8-94e8-6cd54a3adce5
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2075577814 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_random_dout_din_no_pullu
p_pulldown.2075577814
Directory /workspace/42.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/42.gpio_random_long_reg_writes_reg_reads.1815195919
Short name T182
Test name
Test status
Simulation time 238231229 ps
CPU time 5.35 seconds
Started Apr 18 12:31:54 PM PDT 24
Finished Apr 18 12:32:00 PM PDT 24
Peak memory 198004 kb
Host smart-6ddb8f23-2d48-4ac1-8f43-a0c0da7c2c62
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1815195919 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_ra
ndom_long_reg_writes_reg_reads.1815195919
Directory /workspace/42.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/42.gpio_smoke.2935906652
Short name T416
Test name
Test status
Simulation time 62965930 ps
CPU time 0.83 seconds
Started Apr 18 12:31:51 PM PDT 24
Finished Apr 18 12:31:53 PM PDT 24
Peak memory 196884 kb
Host smart-352c2e68-fa26-45c3-a85f-e1c0b39e3c9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2935906652 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_smoke.2935906652
Directory /workspace/42.gpio_smoke/latest

Test location /workspace/coverage/default/42.gpio_smoke_no_pullup_pulldown.2753606280
Short name T383
Test name
Test status
Simulation time 76424348 ps
CPU time 1.13 seconds
Started Apr 18 12:31:54 PM PDT 24
Finished Apr 18 12:31:57 PM PDT 24
Peak memory 195468 kb
Host smart-0da7f053-fcdd-49d3-8dd5-fd0e080c1f60
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2753606280 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_no_pullup_pulldown.2753606280
Directory /workspace/42.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/42.gpio_stress_all.412583856
Short name T584
Test name
Test status
Simulation time 99558396318 ps
CPU time 131.68 seconds
Started Apr 18 12:31:52 PM PDT 24
Finished Apr 18 12:34:05 PM PDT 24
Peak memory 198080 kb
Host smart-c743ca36-e35e-43f8-b30c-395b84fd7c61
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=412583856 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.g
pio_stress_all.412583856
Directory /workspace/42.gpio_stress_all/latest

Test location /workspace/coverage/default/43.gpio_alert_test.2681672930
Short name T326
Test name
Test status
Simulation time 14626009 ps
CPU time 0.58 seconds
Started Apr 18 12:31:52 PM PDT 24
Finished Apr 18 12:31:54 PM PDT 24
Peak memory 194716 kb
Host smart-ab3af40e-99b6-431d-836a-b8659a6d1a98
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2681672930 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_alert_test.2681672930
Directory /workspace/43.gpio_alert_test/latest

Test location /workspace/coverage/default/43.gpio_dout_din_regs_random_rw.4089509875
Short name T357
Test name
Test status
Simulation time 29108393 ps
CPU time 0.61 seconds
Started Apr 18 12:31:53 PM PDT 24
Finished Apr 18 12:31:55 PM PDT 24
Peak memory 193812 kb
Host smart-65b05984-8f58-4c1f-a3a2-f5241341cd97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4089509875 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_dout_din_regs_random_rw.4089509875
Directory /workspace/43.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/43.gpio_filter_stress.2690045639
Short name T139
Test name
Test status
Simulation time 147683550 ps
CPU time 7.55 seconds
Started Apr 18 12:32:11 PM PDT 24
Finished Apr 18 12:32:20 PM PDT 24
Peak memory 197160 kb
Host smart-026e7f4e-f294-4705-a089-3ef65fcd1248
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2690045639 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_filter_stre
ss.2690045639
Directory /workspace/43.gpio_filter_stress/latest

Test location /workspace/coverage/default/43.gpio_full_random.4165446652
Short name T355
Test name
Test status
Simulation time 278938895 ps
CPU time 0.6 seconds
Started Apr 18 12:32:06 PM PDT 24
Finished Apr 18 12:32:08 PM PDT 24
Peak memory 194280 kb
Host smart-de5282d7-829e-400c-9df2-403476c8cb2d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4165446652 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_full_random.4165446652
Directory /workspace/43.gpio_full_random/latest

Test location /workspace/coverage/default/43.gpio_intr_rand_pgm.1141757579
Short name T266
Test name
Test status
Simulation time 70457769 ps
CPU time 1.1 seconds
Started Apr 18 12:31:59 PM PDT 24
Finished Apr 18 12:32:04 PM PDT 24
Peak memory 195696 kb
Host smart-00ad6561-eaae-4eb8-84d4-0f07e16608fc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1141757579 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_intr_rand_pgm.1141757579
Directory /workspace/43.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/43.gpio_intr_with_filter_rand_intr_event.4105060263
Short name T678
Test name
Test status
Simulation time 49649966 ps
CPU time 2.03 seconds
Started Apr 18 12:31:56 PM PDT 24
Finished Apr 18 12:32:06 PM PDT 24
Peak memory 198208 kb
Host smart-974a511c-6e7b-46fe-aa8b-d5432de193ca
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4105060263 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 43.gpio_intr_with_filter_rand_intr_event.4105060263
Directory /workspace/43.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/43.gpio_rand_intr_trigger.3803499304
Short name T274
Test name
Test status
Simulation time 275989282 ps
CPU time 2.7 seconds
Started Apr 18 12:31:52 PM PDT 24
Finished Apr 18 12:31:56 PM PDT 24
Peak memory 198064 kb
Host smart-79eeba52-f6d0-4a29-be15-c707ac53f555
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3803499304 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_rand_intr_trigger
.3803499304
Directory /workspace/43.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/43.gpio_random_dout_din.1967825258
Short name T303
Test name
Test status
Simulation time 30902933 ps
CPU time 1.09 seconds
Started Apr 18 12:31:52 PM PDT 24
Finished Apr 18 12:31:54 PM PDT 24
Peak memory 196660 kb
Host smart-94781a35-8ead-435b-9c88-cf1941a0aa8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1967825258 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_random_dout_din.1967825258
Directory /workspace/43.gpio_random_dout_din/latest

Test location /workspace/coverage/default/43.gpio_random_dout_din_no_pullup_pulldown.3208759592
Short name T550
Test name
Test status
Simulation time 93855932 ps
CPU time 1.1 seconds
Started Apr 18 12:31:59 PM PDT 24
Finished Apr 18 12:32:03 PM PDT 24
Peak memory 195768 kb
Host smart-e5502ac9-8769-4036-a24b-6cbbdb7cb877
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3208759592 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_random_dout_din_no_pullu
p_pulldown.3208759592
Directory /workspace/43.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/43.gpio_random_long_reg_writes_reg_reads.3822180732
Short name T176
Test name
Test status
Simulation time 108822645 ps
CPU time 1.42 seconds
Started Apr 18 12:31:58 PM PDT 24
Finished Apr 18 12:32:03 PM PDT 24
Peak memory 197940 kb
Host smart-d8190bf3-428b-4f7b-8a20-0f3212c47113
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3822180732 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_ra
ndom_long_reg_writes_reg_reads.3822180732
Directory /workspace/43.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/43.gpio_smoke.3737860596
Short name T140
Test name
Test status
Simulation time 109408335 ps
CPU time 1.04 seconds
Started Apr 18 12:31:55 PM PDT 24
Finished Apr 18 12:31:58 PM PDT 24
Peak memory 195772 kb
Host smart-9b728e65-33db-414b-a785-75b6dbd56846
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3737860596 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_smoke.3737860596
Directory /workspace/43.gpio_smoke/latest

Test location /workspace/coverage/default/43.gpio_smoke_no_pullup_pulldown.1939556450
Short name T403
Test name
Test status
Simulation time 126624635 ps
CPU time 1.1 seconds
Started Apr 18 12:32:12 PM PDT 24
Finished Apr 18 12:32:15 PM PDT 24
Peak memory 196316 kb
Host smart-0cdc14d3-149e-44d3-b585-b711b4596a9a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1939556450 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_no_pullup_pulldown.1939556450
Directory /workspace/43.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/43.gpio_stress_all.954578840
Short name T2
Test name
Test status
Simulation time 30637884780 ps
CPU time 163.82 seconds
Started Apr 18 12:32:06 PM PDT 24
Finished Apr 18 12:34:51 PM PDT 24
Peak memory 198136 kb
Host smart-e9696611-df3d-498a-be75-1e344c1d3005
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=954578840 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.g
pio_stress_all.954578840
Directory /workspace/43.gpio_stress_all/latest

Test location /workspace/coverage/default/43.gpio_stress_all_with_rand_reset.2717623251
Short name T650
Test name
Test status
Simulation time 203542941862 ps
CPU time 1036.56 seconds
Started Apr 18 12:31:59 PM PDT 24
Finished Apr 18 12:49:19 PM PDT 24
Peak memory 198172 kb
Host smart-ea9a81e6-dcd1-415a-b24e-557aa145a985
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2717623251 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_stress_all_with_rand_reset.2717623251
Directory /workspace/43.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.gpio_alert_test.761554700
Short name T213
Test name
Test status
Simulation time 19021069 ps
CPU time 0.56 seconds
Started Apr 18 12:32:00 PM PDT 24
Finished Apr 18 12:32:04 PM PDT 24
Peak memory 193796 kb
Host smart-238e59e3-9072-4a14-9098-698da683cfc9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=761554700 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_alert_test.761554700
Directory /workspace/44.gpio_alert_test/latest

Test location /workspace/coverage/default/44.gpio_dout_din_regs_random_rw.3654307753
Short name T438
Test name
Test status
Simulation time 24528297 ps
CPU time 0.65 seconds
Started Apr 18 12:32:11 PM PDT 24
Finished Apr 18 12:32:14 PM PDT 24
Peak memory 194792 kb
Host smart-f73f68e7-a3b8-47ec-ad55-db868f92446e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3654307753 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_dout_din_regs_random_rw.3654307753
Directory /workspace/44.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/44.gpio_filter_stress.1319557929
Short name T539
Test name
Test status
Simulation time 1372633750 ps
CPU time 22.8 seconds
Started Apr 18 12:31:54 PM PDT 24
Finished Apr 18 12:32:19 PM PDT 24
Peak memory 196544 kb
Host smart-0a99e0e2-c805-4051-9566-f8ef11ac62ae
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1319557929 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_filter_stre
ss.1319557929
Directory /workspace/44.gpio_filter_stress/latest

Test location /workspace/coverage/default/44.gpio_full_random.91915487
Short name T410
Test name
Test status
Simulation time 103736308 ps
CPU time 1.02 seconds
Started Apr 18 12:32:13 PM PDT 24
Finished Apr 18 12:32:16 PM PDT 24
Peak memory 196556 kb
Host smart-4a7b9932-bc2c-41a0-ab98-931ac88b2114
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91915487 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_full_random.91915487
Directory /workspace/44.gpio_full_random/latest

Test location /workspace/coverage/default/44.gpio_intr_rand_pgm.645296496
Short name T374
Test name
Test status
Simulation time 159165352 ps
CPU time 1.26 seconds
Started Apr 18 12:32:04 PM PDT 24
Finished Apr 18 12:32:07 PM PDT 24
Peak memory 196784 kb
Host smart-7cd2938f-284c-4bd2-9d65-6bd76942045d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=645296496 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_intr_rand_pgm.645296496
Directory /workspace/44.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/44.gpio_intr_with_filter_rand_intr_event.138052296
Short name T218
Test name
Test status
Simulation time 619519474 ps
CPU time 2.88 seconds
Started Apr 18 12:31:55 PM PDT 24
Finished Apr 18 12:31:59 PM PDT 24
Peak memory 198096 kb
Host smart-cbd80b46-d319-4a54-9bcc-6a28188a771f
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=138052296 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 44.gpio_intr_with_filter_rand_intr_event.138052296
Directory /workspace/44.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/44.gpio_rand_intr_trigger.68441559
Short name T526
Test name
Test status
Simulation time 1784465595 ps
CPU time 3.27 seconds
Started Apr 18 12:32:05 PM PDT 24
Finished Apr 18 12:32:09 PM PDT 24
Peak memory 197016 kb
Host smart-c9ea762f-d830-4080-808f-3ed0ce7665d1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68441559 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigger
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_rand_intr_trigger.68441559
Directory /workspace/44.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/44.gpio_random_dout_din.740518779
Short name T184
Test name
Test status
Simulation time 98898474 ps
CPU time 1.19 seconds
Started Apr 18 12:32:09 PM PDT 24
Finished Apr 18 12:32:11 PM PDT 24
Peak memory 198004 kb
Host smart-5d62bf3d-0dd7-4c28-978f-c1ad5415b180
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=740518779 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_random_dout_din.740518779
Directory /workspace/44.gpio_random_dout_din/latest

Test location /workspace/coverage/default/44.gpio_random_dout_din_no_pullup_pulldown.3383644961
Short name T212
Test name
Test status
Simulation time 71661740 ps
CPU time 1.35 seconds
Started Apr 18 12:31:58 PM PDT 24
Finished Apr 18 12:32:03 PM PDT 24
Peak memory 197956 kb
Host smart-9e459281-b397-44ea-8f1b-c251f3dcc29d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3383644961 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_random_dout_din_no_pullu
p_pulldown.3383644961
Directory /workspace/44.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/44.gpio_random_long_reg_writes_reg_reads.2357091800
Short name T136
Test name
Test status
Simulation time 1160998488 ps
CPU time 4.87 seconds
Started Apr 18 12:32:00 PM PDT 24
Finished Apr 18 12:32:08 PM PDT 24
Peak memory 197984 kb
Host smart-d08adea3-e409-483c-b7a5-a6f2889113da
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2357091800 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_ra
ndom_long_reg_writes_reg_reads.2357091800
Directory /workspace/44.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/44.gpio_smoke.266777953
Short name T203
Test name
Test status
Simulation time 362284283 ps
CPU time 1.26 seconds
Started Apr 18 12:32:10 PM PDT 24
Finished Apr 18 12:32:12 PM PDT 24
Peak memory 195528 kb
Host smart-a0fe9378-cb67-4b99-ade5-109f2c338f16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=266777953 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_smoke.266777953
Directory /workspace/44.gpio_smoke/latest

Test location /workspace/coverage/default/44.gpio_smoke_no_pullup_pulldown.823181417
Short name T333
Test name
Test status
Simulation time 226213060 ps
CPU time 1.12 seconds
Started Apr 18 12:31:57 PM PDT 24
Finished Apr 18 12:32:01 PM PDT 24
Peak memory 196200 kb
Host smart-00223690-fabe-4af9-8cee-0e3d1da4a699
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=823181417 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_no_pullup_pulldown.823181417
Directory /workspace/44.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/44.gpio_stress_all.3581710139
Short name T69
Test name
Test status
Simulation time 8683234006 ps
CPU time 28.46 seconds
Started Apr 18 12:31:54 PM PDT 24
Finished Apr 18 12:32:23 PM PDT 24
Peak memory 198072 kb
Host smart-db45b9d9-fd89-4d28-89c7-50cf157d09b9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3581710139 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.
gpio_stress_all.3581710139
Directory /workspace/44.gpio_stress_all/latest

Test location /workspace/coverage/default/44.gpio_stress_all_with_rand_reset.4273508496
Short name T36
Test name
Test status
Simulation time 100221355088 ps
CPU time 2149.64 seconds
Started Apr 18 12:31:56 PM PDT 24
Finished Apr 18 01:07:49 PM PDT 24
Peak memory 198316 kb
Host smart-b6bfd0c3-c708-4ad2-9b67-a5bd4f6b254b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=4273508496 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_stress_all_with_rand_reset.4273508496
Directory /workspace/44.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.gpio_alert_test.1375266752
Short name T667
Test name
Test status
Simulation time 15320276 ps
CPU time 0.55 seconds
Started Apr 18 12:31:57 PM PDT 24
Finished Apr 18 12:32:01 PM PDT 24
Peak memory 194160 kb
Host smart-d56c5d86-3a44-4658-ba65-a28aaed3356d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1375266752 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_alert_test.1375266752
Directory /workspace/45.gpio_alert_test/latest

Test location /workspace/coverage/default/45.gpio_dout_din_regs_random_rw.560067697
Short name T226
Test name
Test status
Simulation time 40122612 ps
CPU time 0.66 seconds
Started Apr 18 12:31:54 PM PDT 24
Finished Apr 18 12:31:56 PM PDT 24
Peak memory 194192 kb
Host smart-5120a12c-dbe2-4c7a-886d-d13cf8472251
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=560067697 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_dout_din_regs_random_rw.560067697
Directory /workspace/45.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/45.gpio_filter_stress.1127836315
Short name T621
Test name
Test status
Simulation time 280808505 ps
CPU time 14.4 seconds
Started Apr 18 12:31:56 PM PDT 24
Finished Apr 18 12:32:14 PM PDT 24
Peak memory 197084 kb
Host smart-4e481739-c60b-4881-8216-327d47389833
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1127836315 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_filter_stre
ss.1127836315
Directory /workspace/45.gpio_filter_stress/latest

Test location /workspace/coverage/default/45.gpio_full_random.3601779916
Short name T612
Test name
Test status
Simulation time 181325203 ps
CPU time 1.08 seconds
Started Apr 18 12:31:58 PM PDT 24
Finished Apr 18 12:32:03 PM PDT 24
Peak memory 196492 kb
Host smart-3a17c68c-ffd8-4a49-9302-9ba17a1d1be4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3601779916 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_full_random.3601779916
Directory /workspace/45.gpio_full_random/latest

Test location /workspace/coverage/default/45.gpio_intr_rand_pgm.217707243
Short name T309
Test name
Test status
Simulation time 800824702 ps
CPU time 1.1 seconds
Started Apr 18 12:31:57 PM PDT 24
Finished Apr 18 12:32:01 PM PDT 24
Peak memory 196068 kb
Host smart-59db43d4-0481-4b7b-914d-2e53de643931
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=217707243 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_intr_rand_pgm.217707243
Directory /workspace/45.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/45.gpio_intr_with_filter_rand_intr_event.1306173157
Short name T437
Test name
Test status
Simulation time 253058571 ps
CPU time 2.49 seconds
Started Apr 18 12:31:53 PM PDT 24
Finished Apr 18 12:31:57 PM PDT 24
Peak memory 196932 kb
Host smart-c603ca97-1dcb-4aaa-9680-14ba063ed776
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1306173157 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 45.gpio_intr_with_filter_rand_intr_event.1306173157
Directory /workspace/45.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/45.gpio_rand_intr_trigger.3967521651
Short name T431
Test name
Test status
Simulation time 148010150 ps
CPU time 3.63 seconds
Started Apr 18 12:32:10 PM PDT 24
Finished Apr 18 12:32:15 PM PDT 24
Peak memory 197164 kb
Host smart-3caec7ba-0eb1-4095-b69e-9e4fe1a82768
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3967521651 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_rand_intr_trigger
.3967521651
Directory /workspace/45.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/45.gpio_random_dout_din.1968500425
Short name T628
Test name
Test status
Simulation time 97511011 ps
CPU time 1.01 seconds
Started Apr 18 12:31:53 PM PDT 24
Finished Apr 18 12:31:55 PM PDT 24
Peak memory 195956 kb
Host smart-0114bbde-c415-426f-8825-a340f40ac921
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1968500425 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_random_dout_din.1968500425
Directory /workspace/45.gpio_random_dout_din/latest

Test location /workspace/coverage/default/45.gpio_random_dout_din_no_pullup_pulldown.142182400
Short name T441
Test name
Test status
Simulation time 67154477 ps
CPU time 1.28 seconds
Started Apr 18 12:32:09 PM PDT 24
Finished Apr 18 12:32:11 PM PDT 24
Peak memory 196532 kb
Host smart-07e2283b-b3f3-4985-8ad9-37f411ad17f3
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=142182400 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_random_dout_din_no_pullup
_pulldown.142182400
Directory /workspace/45.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/45.gpio_random_long_reg_writes_reg_reads.979637090
Short name T371
Test name
Test status
Simulation time 406992922 ps
CPU time 3.87 seconds
Started Apr 18 12:31:56 PM PDT 24
Finished Apr 18 12:32:03 PM PDT 24
Peak memory 197944 kb
Host smart-1058526c-b834-4377-a309-b210ad5a3047
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=979637090 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_ran
dom_long_reg_writes_reg_reads.979637090
Directory /workspace/45.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/45.gpio_smoke.3646325172
Short name T360
Test name
Test status
Simulation time 67675117 ps
CPU time 1.18 seconds
Started Apr 18 12:31:49 PM PDT 24
Finished Apr 18 12:31:50 PM PDT 24
Peak memory 196144 kb
Host smart-94b340ce-7d83-420a-89ca-ec646212ddc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3646325172 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_smoke.3646325172
Directory /workspace/45.gpio_smoke/latest

Test location /workspace/coverage/default/45.gpio_smoke_no_pullup_pulldown.698438169
Short name T679
Test name
Test status
Simulation time 195005754 ps
CPU time 0.96 seconds
Started Apr 18 12:32:15 PM PDT 24
Finished Apr 18 12:32:18 PM PDT 24
Peak memory 195804 kb
Host smart-e878d1d3-95c4-4316-861a-2a7cde36bad6
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=698438169 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_no_pullup_pulldown.698438169
Directory /workspace/45.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/45.gpio_stress_all.342199
Short name T291
Test name
Test status
Simulation time 4466654080 ps
CPU time 77.03 seconds
Started Apr 18 12:31:53 PM PDT 24
Finished Apr 18 12:33:12 PM PDT 24
Peak memory 198104 kb
Host smart-f608f2e7-279b-4f10-babd-6e5341445aa2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=342199 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio
_stress_all.342199
Directory /workspace/45.gpio_stress_all/latest

Test location /workspace/coverage/default/46.gpio_alert_test.1444674345
Short name T677
Test name
Test status
Simulation time 49806594 ps
CPU time 0.57 seconds
Started Apr 18 12:32:01 PM PDT 24
Finished Apr 18 12:32:04 PM PDT 24
Peak memory 193812 kb
Host smart-5a6be378-6558-4d18-a8b7-668795dae7b1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1444674345 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_alert_test.1444674345
Directory /workspace/46.gpio_alert_test/latest

Test location /workspace/coverage/default/46.gpio_dout_din_regs_random_rw.4022104763
Short name T268
Test name
Test status
Simulation time 93629308 ps
CPU time 0.93 seconds
Started Apr 18 12:32:09 PM PDT 24
Finished Apr 18 12:32:11 PM PDT 24
Peak memory 196632 kb
Host smart-27be621c-1550-45c8-9494-0c0935cfe5e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4022104763 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_dout_din_regs_random_rw.4022104763
Directory /workspace/46.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/46.gpio_filter_stress.2707607782
Short name T549
Test name
Test status
Simulation time 220438691 ps
CPU time 10.83 seconds
Started Apr 18 12:31:59 PM PDT 24
Finished Apr 18 12:32:13 PM PDT 24
Peak memory 197944 kb
Host smart-b251bbe2-84cb-43b1-8308-27cc66352dee
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2707607782 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_filter_stre
ss.2707607782
Directory /workspace/46.gpio_filter_stress/latest

Test location /workspace/coverage/default/46.gpio_full_random.489334071
Short name T400
Test name
Test status
Simulation time 27114863 ps
CPU time 0.6 seconds
Started Apr 18 12:31:55 PM PDT 24
Finished Apr 18 12:31:58 PM PDT 24
Peak memory 194628 kb
Host smart-e2cc16e1-23fa-4eae-aad1-f2ae895a1464
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=489334071 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_full_random.489334071
Directory /workspace/46.gpio_full_random/latest

Test location /workspace/coverage/default/46.gpio_intr_rand_pgm.394866039
Short name T540
Test name
Test status
Simulation time 64630385 ps
CPU time 0.74 seconds
Started Apr 18 12:32:09 PM PDT 24
Finished Apr 18 12:32:10 PM PDT 24
Peak memory 195348 kb
Host smart-508f4922-3a99-4224-8805-cb1baebc83b3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=394866039 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_intr_rand_pgm.394866039
Directory /workspace/46.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/46.gpio_intr_with_filter_rand_intr_event.496395127
Short name T630
Test name
Test status
Simulation time 146088770 ps
CPU time 2.84 seconds
Started Apr 18 12:32:02 PM PDT 24
Finished Apr 18 12:32:07 PM PDT 24
Peak memory 196488 kb
Host smart-1b870a7b-84bd-4df9-88f6-5c1ff2f7bce2
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=496395127 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 46.gpio_intr_with_filter_rand_intr_event.496395127
Directory /workspace/46.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/46.gpio_rand_intr_trigger.1310171361
Short name T190
Test name
Test status
Simulation time 334189930 ps
CPU time 2.41 seconds
Started Apr 18 12:31:55 PM PDT 24
Finished Apr 18 12:32:00 PM PDT 24
Peak memory 195820 kb
Host smart-cada510f-71ca-4c03-b044-0b068d1e1d35
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1310171361 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_rand_intr_trigger
.1310171361
Directory /workspace/46.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/46.gpio_random_dout_din.589815044
Short name T648
Test name
Test status
Simulation time 37299406 ps
CPU time 1.32 seconds
Started Apr 18 12:31:56 PM PDT 24
Finished Apr 18 12:31:59 PM PDT 24
Peak memory 198460 kb
Host smart-3a2abe63-86bb-49b5-a512-ba2683e6779a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=589815044 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_random_dout_din.589815044
Directory /workspace/46.gpio_random_dout_din/latest

Test location /workspace/coverage/default/46.gpio_random_dout_din_no_pullup_pulldown.2967620605
Short name T423
Test name
Test status
Simulation time 108031548 ps
CPU time 1.03 seconds
Started Apr 18 12:32:05 PM PDT 24
Finished Apr 18 12:32:07 PM PDT 24
Peak memory 196504 kb
Host smart-0f173b23-18b1-497c-9858-29a1f3dc58ed
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2967620605 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_random_dout_din_no_pullu
p_pulldown.2967620605
Directory /workspace/46.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/46.gpio_random_long_reg_writes_reg_reads.1468855597
Short name T564
Test name
Test status
Simulation time 388827771 ps
CPU time 4.62 seconds
Started Apr 18 12:32:00 PM PDT 24
Finished Apr 18 12:32:08 PM PDT 24
Peak memory 197916 kb
Host smart-386fbac8-66e3-4a90-b77d-e4376b2028ec
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1468855597 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_ra
ndom_long_reg_writes_reg_reads.1468855597
Directory /workspace/46.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/46.gpio_smoke.2557094992
Short name T510
Test name
Test status
Simulation time 113454606 ps
CPU time 1.16 seconds
Started Apr 18 12:31:58 PM PDT 24
Finished Apr 18 12:32:03 PM PDT 24
Peak memory 196472 kb
Host smart-d712b732-e6fa-4210-88bb-bff06e40bafd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2557094992 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_smoke.2557094992
Directory /workspace/46.gpio_smoke/latest

Test location /workspace/coverage/default/46.gpio_smoke_no_pullup_pulldown.87748690
Short name T532
Test name
Test status
Simulation time 23992852 ps
CPU time 0.69 seconds
Started Apr 18 12:31:58 PM PDT 24
Finished Apr 18 12:32:02 PM PDT 24
Peak memory 194140 kb
Host smart-dfed099b-7bc7-472d-911a-95fe05d82273
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87748690 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_no_pullup_pulldown.87748690
Directory /workspace/46.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/46.gpio_stress_all.1822901530
Short name T519
Test name
Test status
Simulation time 7322758771 ps
CPU time 50.53 seconds
Started Apr 18 12:31:55 PM PDT 24
Finished Apr 18 12:32:48 PM PDT 24
Peak memory 198196 kb
Host smart-30f1c654-fda0-461b-9314-cf6032372025
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1822901530 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.
gpio_stress_all.1822901530
Directory /workspace/46.gpio_stress_all/latest

Test location /workspace/coverage/default/47.gpio_alert_test.1146144898
Short name T133
Test name
Test status
Simulation time 14184848 ps
CPU time 0.56 seconds
Started Apr 18 12:32:06 PM PDT 24
Finished Apr 18 12:32:07 PM PDT 24
Peak memory 193820 kb
Host smart-6ef48c71-e0c2-4ec5-a72d-fe6424d0cc27
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1146144898 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_alert_test.1146144898
Directory /workspace/47.gpio_alert_test/latest

Test location /workspace/coverage/default/47.gpio_dout_din_regs_random_rw.802903369
Short name T180
Test name
Test status
Simulation time 223188884 ps
CPU time 0.91 seconds
Started Apr 18 12:32:10 PM PDT 24
Finished Apr 18 12:32:12 PM PDT 24
Peak memory 196192 kb
Host smart-7cf4e34a-a700-497a-8e6f-a963f9f196f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=802903369 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_dout_din_regs_random_rw.802903369
Directory /workspace/47.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/47.gpio_filter_stress.2741372705
Short name T596
Test name
Test status
Simulation time 654197736 ps
CPU time 8.68 seconds
Started Apr 18 12:32:30 PM PDT 24
Finished Apr 18 12:32:39 PM PDT 24
Peak memory 198096 kb
Host smart-595aa3de-dfa3-4b15-bf85-4fd854958ff8
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2741372705 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_filter_stre
ss.2741372705
Directory /workspace/47.gpio_filter_stress/latest

Test location /workspace/coverage/default/47.gpio_full_random.89290724
Short name T580
Test name
Test status
Simulation time 120431224 ps
CPU time 0.92 seconds
Started Apr 18 12:32:10 PM PDT 24
Finished Apr 18 12:32:12 PM PDT 24
Peak memory 196868 kb
Host smart-a9cfffae-3ad1-416d-8114-ec6eb4eadaca
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89290724 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_full_random.89290724
Directory /workspace/47.gpio_full_random/latest

Test location /workspace/coverage/default/47.gpio_intr_rand_pgm.1725889987
Short name T217
Test name
Test status
Simulation time 217137118 ps
CPU time 1.01 seconds
Started Apr 18 12:32:10 PM PDT 24
Finished Apr 18 12:32:13 PM PDT 24
Peak memory 196868 kb
Host smart-77cffffc-80b8-446a-b8f3-28c178684265
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1725889987 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_intr_rand_pgm.1725889987
Directory /workspace/47.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/47.gpio_intr_with_filter_rand_intr_event.3602755350
Short name T493
Test name
Test status
Simulation time 178994036 ps
CPU time 1.86 seconds
Started Apr 18 12:31:59 PM PDT 24
Finished Apr 18 12:32:05 PM PDT 24
Peak memory 198016 kb
Host smart-09b510ad-11df-4ffb-9134-4467b52c69fb
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3602755350 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 47.gpio_intr_with_filter_rand_intr_event.3602755350
Directory /workspace/47.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/47.gpio_rand_intr_trigger.1668620969
Short name T515
Test name
Test status
Simulation time 376735894 ps
CPU time 2.68 seconds
Started Apr 18 12:32:00 PM PDT 24
Finished Apr 18 12:32:06 PM PDT 24
Peak memory 198188 kb
Host smart-c14dbc5a-7c80-4899-92f4-4116338e89fc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1668620969 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_rand_intr_trigger
.1668620969
Directory /workspace/47.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/47.gpio_random_dout_din.296718905
Short name T536
Test name
Test status
Simulation time 50101132 ps
CPU time 1.09 seconds
Started Apr 18 12:31:59 PM PDT 24
Finished Apr 18 12:32:03 PM PDT 24
Peak memory 196708 kb
Host smart-53684fa9-ed4e-49b2-8764-71e8243c4f85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=296718905 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_random_dout_din.296718905
Directory /workspace/47.gpio_random_dout_din/latest

Test location /workspace/coverage/default/47.gpio_random_dout_din_no_pullup_pulldown.751116355
Short name T332
Test name
Test status
Simulation time 120111821 ps
CPU time 1.26 seconds
Started Apr 18 12:32:12 PM PDT 24
Finished Apr 18 12:32:15 PM PDT 24
Peak memory 196996 kb
Host smart-6a276e68-1705-48d1-809d-e9369bc70812
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=751116355 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_random_dout_din_no_pullup
_pulldown.751116355
Directory /workspace/47.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/47.gpio_random_long_reg_writes_reg_reads.686944216
Short name T604
Test name
Test status
Simulation time 138525385 ps
CPU time 5.65 seconds
Started Apr 18 12:32:00 PM PDT 24
Finished Apr 18 12:32:09 PM PDT 24
Peak memory 197936 kb
Host smart-fb1b408a-d83d-4056-9fb4-475a3d207656
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=686944216 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_ran
dom_long_reg_writes_reg_reads.686944216
Directory /workspace/47.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/47.gpio_smoke.3173837231
Short name T206
Test name
Test status
Simulation time 51785373 ps
CPU time 1.02 seconds
Started Apr 18 12:31:59 PM PDT 24
Finished Apr 18 12:32:04 PM PDT 24
Peak memory 195512 kb
Host smart-b7897e2f-0ac4-4daf-b821-c6bcb7a66b30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3173837231 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_smoke.3173837231
Directory /workspace/47.gpio_smoke/latest

Test location /workspace/coverage/default/47.gpio_smoke_no_pullup_pulldown.2528973883
Short name T392
Test name
Test status
Simulation time 59021323 ps
CPU time 0.94 seconds
Started Apr 18 12:32:08 PM PDT 24
Finished Apr 18 12:32:10 PM PDT 24
Peak memory 195376 kb
Host smart-7aa0d083-0a2b-4c18-a940-0dac628c63f6
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2528973883 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_no_pullup_pulldown.2528973883
Directory /workspace/47.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/47.gpio_stress_all.2959760373
Short name T144
Test name
Test status
Simulation time 2004686179 ps
CPU time 51.5 seconds
Started Apr 18 12:32:00 PM PDT 24
Finished Apr 18 12:32:54 PM PDT 24
Peak memory 197716 kb
Host smart-2716c313-bd9b-4c6c-9a1e-932e0105e7e5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2959760373 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.
gpio_stress_all.2959760373
Directory /workspace/47.gpio_stress_all/latest

Test location /workspace/coverage/default/47.gpio_stress_all_with_rand_reset.866929673
Short name T529
Test name
Test status
Simulation time 104125897895 ps
CPU time 1393.17 seconds
Started Apr 18 12:32:16 PM PDT 24
Finished Apr 18 12:55:32 PM PDT 24
Peak memory 198180 kb
Host smart-73ec5aa2-ed18-401d-8a3c-ec956e623eb4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=866929673 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_stress_all_with_rand_reset.866929673
Directory /workspace/47.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.gpio_alert_test.533321779
Short name T432
Test name
Test status
Simulation time 40379112 ps
CPU time 0.61 seconds
Started Apr 18 12:32:05 PM PDT 24
Finished Apr 18 12:32:07 PM PDT 24
Peak memory 193932 kb
Host smart-f81ac42a-1c9c-437e-95da-76b5e29e5e38
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=533321779 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_alert_test.533321779
Directory /workspace/48.gpio_alert_test/latest

Test location /workspace/coverage/default/48.gpio_dout_din_regs_random_rw.2044423107
Short name T483
Test name
Test status
Simulation time 124549071 ps
CPU time 0.77 seconds
Started Apr 18 12:31:59 PM PDT 24
Finished Apr 18 12:32:04 PM PDT 24
Peak memory 195912 kb
Host smart-0094e879-2250-4faf-aa72-ecef76940e8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2044423107 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_dout_din_regs_random_rw.2044423107
Directory /workspace/48.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/48.gpio_filter_stress.32436321
Short name T393
Test name
Test status
Simulation time 1133377270 ps
CPU time 15.45 seconds
Started Apr 18 12:32:13 PM PDT 24
Finished Apr 18 12:32:30 PM PDT 24
Peak memory 196724 kb
Host smart-8a01a931-d18a-4e63-a700-c324e107cad2
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32436321 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter_
stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_filter_stress
.32436321
Directory /workspace/48.gpio_filter_stress/latest

Test location /workspace/coverage/default/48.gpio_full_random.398113812
Short name T533
Test name
Test status
Simulation time 250727295 ps
CPU time 0.83 seconds
Started Apr 18 12:31:59 PM PDT 24
Finished Apr 18 12:32:04 PM PDT 24
Peak memory 196008 kb
Host smart-50aa8a1e-a958-4fda-8700-7e5fc9fee5dc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=398113812 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_full_random.398113812
Directory /workspace/48.gpio_full_random/latest

Test location /workspace/coverage/default/48.gpio_intr_rand_pgm.28226876
Short name T15
Test name
Test status
Simulation time 64260871 ps
CPU time 0.66 seconds
Started Apr 18 12:32:07 PM PDT 24
Finished Apr 18 12:32:09 PM PDT 24
Peak memory 194312 kb
Host smart-08ce9166-d9de-43d8-820b-b655770bdeb2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28226876 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_intr_rand_pgm.28226876
Directory /workspace/48.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/48.gpio_intr_with_filter_rand_intr_event.3845356973
Short name T235
Test name
Test status
Simulation time 59868182 ps
CPU time 2.34 seconds
Started Apr 18 12:32:31 PM PDT 24
Finished Apr 18 12:32:35 PM PDT 24
Peak memory 198064 kb
Host smart-20adfd9a-51b6-4568-98fe-7d0dcde7a909
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3845356973 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 48.gpio_intr_with_filter_rand_intr_event.3845356973
Directory /workspace/48.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/48.gpio_rand_intr_trigger.888250246
Short name T504
Test name
Test status
Simulation time 248298531 ps
CPU time 1.52 seconds
Started Apr 18 12:32:13 PM PDT 24
Finished Apr 18 12:32:17 PM PDT 24
Peak memory 196484 kb
Host smart-97071245-e3a8-4343-b7be-92132602a636
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=888250246 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_rand_intr_trigger.
888250246
Directory /workspace/48.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/48.gpio_random_dout_din.2895943313
Short name T289
Test name
Test status
Simulation time 47653794 ps
CPU time 0.81 seconds
Started Apr 18 12:32:11 PM PDT 24
Finished Apr 18 12:32:13 PM PDT 24
Peak memory 197112 kb
Host smart-61cb652f-719a-4442-8e51-00240dee2fe2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2895943313 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_random_dout_din.2895943313
Directory /workspace/48.gpio_random_dout_din/latest

Test location /workspace/coverage/default/48.gpio_random_dout_din_no_pullup_pulldown.3944474855
Short name T285
Test name
Test status
Simulation time 75050729 ps
CPU time 0.72 seconds
Started Apr 18 12:32:07 PM PDT 24
Finished Apr 18 12:32:09 PM PDT 24
Peak memory 194300 kb
Host smart-b8e9d45a-71ce-457f-80d1-c489db138323
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3944474855 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_random_dout_din_no_pullu
p_pulldown.3944474855
Directory /workspace/48.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/48.gpio_random_long_reg_writes_reg_reads.1725277487
Short name T109
Test name
Test status
Simulation time 430306401 ps
CPU time 4.68 seconds
Started Apr 18 12:32:04 PM PDT 24
Finished Apr 18 12:32:10 PM PDT 24
Peak memory 197912 kb
Host smart-9c215521-e8db-4518-ad94-0726816c9921
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1725277487 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_ra
ndom_long_reg_writes_reg_reads.1725277487
Directory /workspace/48.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/48.gpio_smoke.2528615697
Short name T454
Test name
Test status
Simulation time 156783707 ps
CPU time 1.14 seconds
Started Apr 18 12:31:55 PM PDT 24
Finished Apr 18 12:31:59 PM PDT 24
Peak memory 196636 kb
Host smart-3fd78cc8-039e-4968-be2d-95960dd68f40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2528615697 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_smoke.2528615697
Directory /workspace/48.gpio_smoke/latest

Test location /workspace/coverage/default/48.gpio_smoke_no_pullup_pulldown.4282942272
Short name T530
Test name
Test status
Simulation time 147069190 ps
CPU time 1.34 seconds
Started Apr 18 12:31:56 PM PDT 24
Finished Apr 18 12:32:00 PM PDT 24
Peak memory 196736 kb
Host smart-aa1f0eac-e587-4e9f-a851-9128e237e192
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4282942272 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_no_pullup_pulldown.4282942272
Directory /workspace/48.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/48.gpio_stress_all.53611083
Short name T33
Test name
Test status
Simulation time 5867218499 ps
CPU time 35.07 seconds
Started Apr 18 12:32:09 PM PDT 24
Finished Apr 18 12:32:45 PM PDT 24
Peak memory 198088 kb
Host smart-1b3ae6ba-ec8a-4699-a89c-decb3a33868a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53611083 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TE
ST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gp
io_stress_all.53611083
Directory /workspace/48.gpio_stress_all/latest

Test location /workspace/coverage/default/49.gpio_alert_test.3813620330
Short name T613
Test name
Test status
Simulation time 12190435 ps
CPU time 0.58 seconds
Started Apr 18 12:32:01 PM PDT 24
Finished Apr 18 12:32:05 PM PDT 24
Peak memory 193880 kb
Host smart-5eb0d804-26bc-4993-b980-3016f194b3e2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3813620330 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_alert_test.3813620330
Directory /workspace/49.gpio_alert_test/latest

Test location /workspace/coverage/default/49.gpio_dout_din_regs_random_rw.2115442758
Short name T563
Test name
Test status
Simulation time 30014367 ps
CPU time 0.86 seconds
Started Apr 18 12:32:07 PM PDT 24
Finished Apr 18 12:32:09 PM PDT 24
Peak memory 196484 kb
Host smart-5ede85a2-33e3-4960-b1c4-4d80b2461365
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2115442758 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_dout_din_regs_random_rw.2115442758
Directory /workspace/49.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/49.gpio_filter_stress.175077
Short name T378
Test name
Test status
Simulation time 3198495066 ps
CPU time 20.14 seconds
Started Apr 18 12:32:00 PM PDT 24
Finished Apr 18 12:32:24 PM PDT 24
Peak memory 197408 kb
Host smart-3c5569a2-e530-4a9c-b017-8e454d559cec
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=175077 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter_st
ress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_filter_stress.175077
Directory /workspace/49.gpio_filter_stress/latest

Test location /workspace/coverage/default/49.gpio_full_random.3068364402
Short name T369
Test name
Test status
Simulation time 47433484 ps
CPU time 0.85 seconds
Started Apr 18 12:32:10 PM PDT 24
Finished Apr 18 12:32:12 PM PDT 24
Peak memory 196012 kb
Host smart-4c2f62a0-3f80-4fd8-9cc8-7d60810a8fc9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3068364402 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_full_random.3068364402
Directory /workspace/49.gpio_full_random/latest

Test location /workspace/coverage/default/49.gpio_intr_rand_pgm.1915158377
Short name T110
Test name
Test status
Simulation time 180071796 ps
CPU time 1.21 seconds
Started Apr 18 12:32:07 PM PDT 24
Finished Apr 18 12:32:09 PM PDT 24
Peak memory 197968 kb
Host smart-cb4eb329-6b0a-406b-8059-6dcd47373c3b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1915158377 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_intr_rand_pgm.1915158377
Directory /workspace/49.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/49.gpio_intr_with_filter_rand_intr_event.384043119
Short name T524
Test name
Test status
Simulation time 84232477 ps
CPU time 3.2 seconds
Started Apr 18 12:31:57 PM PDT 24
Finished Apr 18 12:32:03 PM PDT 24
Peak memory 198016 kb
Host smart-5c73df00-3d5d-4abc-a8a9-4e56b7093aee
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=384043119 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 49.gpio_intr_with_filter_rand_intr_event.384043119
Directory /workspace/49.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/49.gpio_rand_intr_trigger.4154728098
Short name T649
Test name
Test status
Simulation time 93580104 ps
CPU time 2.18 seconds
Started Apr 18 12:32:03 PM PDT 24
Finished Apr 18 12:32:07 PM PDT 24
Peak memory 197144 kb
Host smart-7e5b3324-5516-4373-8794-70cad61df260
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4154728098 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_rand_intr_trigger
.4154728098
Directory /workspace/49.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/49.gpio_random_dout_din.714785042
Short name T477
Test name
Test status
Simulation time 133842216 ps
CPU time 1.1 seconds
Started Apr 18 12:31:56 PM PDT 24
Finished Apr 18 12:32:00 PM PDT 24
Peak memory 196920 kb
Host smart-7a22c207-f61e-4dda-8937-88bf24186044
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=714785042 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_random_dout_din.714785042
Directory /workspace/49.gpio_random_dout_din/latest

Test location /workspace/coverage/default/49.gpio_random_dout_din_no_pullup_pulldown.1011624001
Short name T364
Test name
Test status
Simulation time 55548604 ps
CPU time 0.76 seconds
Started Apr 18 12:32:00 PM PDT 24
Finished Apr 18 12:32:04 PM PDT 24
Peak memory 195404 kb
Host smart-57096334-7c95-44aa-bff3-3d478372c080
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1011624001 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_random_dout_din_no_pullu
p_pulldown.1011624001
Directory /workspace/49.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/49.gpio_random_long_reg_writes_reg_reads.46742390
Short name T237
Test name
Test status
Simulation time 56762458 ps
CPU time 2.48 seconds
Started Apr 18 12:32:09 PM PDT 24
Finished Apr 18 12:32:13 PM PDT 24
Peak memory 197916 kb
Host smart-dcbfee8f-1d2e-4751-917d-8766b02e64be
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46742390 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_w
rites_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_rand
om_long_reg_writes_reg_reads.46742390
Directory /workspace/49.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/49.gpio_smoke.1249452594
Short name T229
Test name
Test status
Simulation time 57953638 ps
CPU time 1.15 seconds
Started Apr 18 12:31:59 PM PDT 24
Finished Apr 18 12:32:03 PM PDT 24
Peak memory 195740 kb
Host smart-02ff3050-8ebc-4e2e-b744-e37cf2d9cd3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1249452594 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_smoke.1249452594
Directory /workspace/49.gpio_smoke/latest

Test location /workspace/coverage/default/49.gpio_smoke_no_pullup_pulldown.3790691036
Short name T417
Test name
Test status
Simulation time 25709925 ps
CPU time 0.83 seconds
Started Apr 18 12:32:05 PM PDT 24
Finished Apr 18 12:32:07 PM PDT 24
Peak memory 196228 kb
Host smart-81dbe3b4-8c7d-46ed-8845-d4fa4d5720a7
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3790691036 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_no_pullup_pulldown.3790691036
Directory /workspace/49.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/49.gpio_stress_all.1965504824
Short name T301
Test name
Test status
Simulation time 3481749861 ps
CPU time 44.38 seconds
Started Apr 18 12:32:00 PM PDT 24
Finished Apr 18 12:32:47 PM PDT 24
Peak memory 198024 kb
Host smart-53cd2756-be71-46c0-b355-b1f7e0a8ab08
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1965504824 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.
gpio_stress_all.1965504824
Directory /workspace/49.gpio_stress_all/latest

Test location /workspace/coverage/default/5.gpio_alert_test.3741611509
Short name T170
Test name
Test status
Simulation time 15477591 ps
CPU time 0.61 seconds
Started Apr 18 12:30:52 PM PDT 24
Finished Apr 18 12:30:54 PM PDT 24
Peak memory 194764 kb
Host smart-0497ee84-d13c-471a-98b7-36536013a4e9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3741611509 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_alert_test.3741611509
Directory /workspace/5.gpio_alert_test/latest

Test location /workspace/coverage/default/5.gpio_dout_din_regs_random_rw.1198938130
Short name T294
Test name
Test status
Simulation time 31041728 ps
CPU time 0.92 seconds
Started Apr 18 12:30:49 PM PDT 24
Finished Apr 18 12:30:51 PM PDT 24
Peak memory 196520 kb
Host smart-40ce98f4-f0a9-48f9-91a0-8326edee3d29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1198938130 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_dout_din_regs_random_rw.1198938130
Directory /workspace/5.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/5.gpio_filter_stress.2600684980
Short name T319
Test name
Test status
Simulation time 516742423 ps
CPU time 28.71 seconds
Started Apr 18 12:30:38 PM PDT 24
Finished Apr 18 12:31:07 PM PDT 24
Peak memory 198124 kb
Host smart-5cafa4e0-4e5d-4b92-a8e5-ec2dc9ebc391
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2600684980 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_filter_stres
s.2600684980
Directory /workspace/5.gpio_filter_stress/latest

Test location /workspace/coverage/default/5.gpio_full_random.3991743353
Short name T372
Test name
Test status
Simulation time 100369746 ps
CPU time 1.07 seconds
Started Apr 18 12:31:50 PM PDT 24
Finished Apr 18 12:31:52 PM PDT 24
Peak memory 196500 kb
Host smart-80100997-d523-4238-b0e2-a8870c41573d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3991743353 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_full_random.3991743353
Directory /workspace/5.gpio_full_random/latest

Test location /workspace/coverage/default/5.gpio_intr_rand_pgm.2245904572
Short name T627
Test name
Test status
Simulation time 85532007 ps
CPU time 1.22 seconds
Started Apr 18 12:30:36 PM PDT 24
Finished Apr 18 12:30:37 PM PDT 24
Peak memory 195764 kb
Host smart-eb8db563-ff15-4025-8bfe-5e868ffeb061
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2245904572 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_intr_rand_pgm.2245904572
Directory /workspace/5.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/5.gpio_intr_with_filter_rand_intr_event.1786299095
Short name T702
Test name
Test status
Simulation time 695575592 ps
CPU time 3.46 seconds
Started Apr 18 12:30:37 PM PDT 24
Finished Apr 18 12:30:41 PM PDT 24
Peak memory 198124 kb
Host smart-f4394471-9cdf-41e7-b9a9-81a6c9994fc3
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1786299095 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 5.gpio_intr_with_filter_rand_intr_event.1786299095
Directory /workspace/5.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/5.gpio_rand_intr_trigger.2839828438
Short name T615
Test name
Test status
Simulation time 67086379 ps
CPU time 0.88 seconds
Started Apr 18 12:31:08 PM PDT 24
Finished Apr 18 12:31:16 PM PDT 24
Peak memory 194280 kb
Host smart-9bfe0f74-e5cf-47c8-ad95-083c7810c66b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2839828438 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_rand_intr_trigger.
2839828438
Directory /workspace/5.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/5.gpio_random_dout_din.2554570781
Short name T314
Test name
Test status
Simulation time 45828529 ps
CPU time 1.03 seconds
Started Apr 18 12:31:38 PM PDT 24
Finished Apr 18 12:31:40 PM PDT 24
Peak memory 195980 kb
Host smart-203ac7b7-70a8-4ef9-aea4-9c7be2d67c27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2554570781 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_random_dout_din.2554570781
Directory /workspace/5.gpio_random_dout_din/latest

Test location /workspace/coverage/default/5.gpio_random_dout_din_no_pullup_pulldown.1426716483
Short name T105
Test name
Test status
Simulation time 138267782 ps
CPU time 1.04 seconds
Started Apr 18 12:30:39 PM PDT 24
Finished Apr 18 12:30:41 PM PDT 24
Peak memory 195972 kb
Host smart-30b0bedd-5c2e-41ec-87e4-21fa0e05833a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1426716483 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_random_dout_din_no_pullup
_pulldown.1426716483
Directory /workspace/5.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/5.gpio_random_long_reg_writes_reg_reads.3771573077
Short name T499
Test name
Test status
Simulation time 129560093 ps
CPU time 2.1 seconds
Started Apr 18 12:30:25 PM PDT 24
Finished Apr 18 12:30:30 PM PDT 24
Peak memory 197892 kb
Host smart-3e796526-0666-40e8-85b4-e23726c79187
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3771573077 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_ran
dom_long_reg_writes_reg_reads.3771573077
Directory /workspace/5.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/5.gpio_smoke.3912836083
Short name T488
Test name
Test status
Simulation time 89084652 ps
CPU time 1.34 seconds
Started Apr 18 12:30:36 PM PDT 24
Finished Apr 18 12:30:38 PM PDT 24
Peak memory 196500 kb
Host smart-e16ab494-9f82-457c-a662-8d2f093bc485
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3912836083 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_smoke.3912836083
Directory /workspace/5.gpio_smoke/latest

Test location /workspace/coverage/default/5.gpio_smoke_no_pullup_pulldown.3500570834
Short name T385
Test name
Test status
Simulation time 105633438 ps
CPU time 0.76 seconds
Started Apr 18 12:30:51 PM PDT 24
Finished Apr 18 12:30:52 PM PDT 24
Peak memory 195060 kb
Host smart-d08205df-6c55-43e6-896f-fd5760de658b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3500570834 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_no_pullup_pulldown.3500570834
Directory /workspace/5.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/5.gpio_stress_all.1598946301
Short name T32
Test name
Test status
Simulation time 55220789910 ps
CPU time 178.46 seconds
Started Apr 18 12:30:38 PM PDT 24
Finished Apr 18 12:33:37 PM PDT 24
Peak memory 198128 kb
Host smart-b8033cfa-6f15-41e8-befc-419d39644b05
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1598946301 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.g
pio_stress_all.1598946301
Directory /workspace/5.gpio_stress_all/latest

Test location /workspace/coverage/default/5.gpio_stress_all_with_rand_reset.1994927929
Short name T56
Test name
Test status
Simulation time 358407367360 ps
CPU time 1873.98 seconds
Started Apr 18 12:31:54 PM PDT 24
Finished Apr 18 01:03:09 PM PDT 24
Peak memory 198100 kb
Host smart-d6acd10c-ca65-4dae-84d4-d855b1d296b5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1994927929 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_stress_all_with_rand_reset.1994927929
Directory /workspace/5.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.gpio_alert_test.1811226489
Short name T518
Test name
Test status
Simulation time 31790081 ps
CPU time 0.6 seconds
Started Apr 18 12:30:47 PM PDT 24
Finished Apr 18 12:30:48 PM PDT 24
Peak memory 193828 kb
Host smart-1ecf35aa-01db-411a-9403-3f82b144c8fc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1811226489 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_alert_test.1811226489
Directory /workspace/6.gpio_alert_test/latest

Test location /workspace/coverage/default/6.gpio_dout_din_regs_random_rw.3604189452
Short name T581
Test name
Test status
Simulation time 149340022 ps
CPU time 0.91 seconds
Started Apr 18 12:30:52 PM PDT 24
Finished Apr 18 12:30:53 PM PDT 24
Peak memory 197440 kb
Host smart-623ab40c-abd0-4083-a743-e4265659db83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3604189452 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_dout_din_regs_random_rw.3604189452
Directory /workspace/6.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/6.gpio_filter_stress.2481268520
Short name T401
Test name
Test status
Simulation time 6936009607 ps
CPU time 21.52 seconds
Started Apr 18 12:30:57 PM PDT 24
Finished Apr 18 12:31:19 PM PDT 24
Peak memory 198448 kb
Host smart-76bb41e4-d5f8-45b2-972e-5581c079eba6
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2481268520 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_filter_stres
s.2481268520
Directory /workspace/6.gpio_filter_stress/latest

Test location /workspace/coverage/default/6.gpio_full_random.1403700929
Short name T565
Test name
Test status
Simulation time 61852249 ps
CPU time 0.72 seconds
Started Apr 18 12:30:49 PM PDT 24
Finished Apr 18 12:30:51 PM PDT 24
Peak memory 195696 kb
Host smart-0a8561a3-0ffe-4f02-9722-31f123f8fc2b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1403700929 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_full_random.1403700929
Directory /workspace/6.gpio_full_random/latest

Test location /workspace/coverage/default/6.gpio_intr_rand_pgm.320156657
Short name T321
Test name
Test status
Simulation time 62358186 ps
CPU time 0.99 seconds
Started Apr 18 12:30:46 PM PDT 24
Finished Apr 18 12:30:48 PM PDT 24
Peak memory 196252 kb
Host smart-138fe821-fb5f-474d-813a-bd23c09740c0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=320156657 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_intr_rand_pgm.320156657
Directory /workspace/6.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/6.gpio_intr_with_filter_rand_intr_event.3809737126
Short name T390
Test name
Test status
Simulation time 537242201 ps
CPU time 2.53 seconds
Started Apr 18 12:30:45 PM PDT 24
Finished Apr 18 12:30:48 PM PDT 24
Peak memory 198012 kb
Host smart-50553e32-19b8-403e-bafa-ed7b73ea0a40
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3809737126 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 6.gpio_intr_with_filter_rand_intr_event.3809737126
Directory /workspace/6.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/6.gpio_rand_intr_trigger.470860299
Short name T465
Test name
Test status
Simulation time 613647031 ps
CPU time 3.17 seconds
Started Apr 18 12:30:48 PM PDT 24
Finished Apr 18 12:30:52 PM PDT 24
Peak memory 196456 kb
Host smart-bef35da2-5c6b-41d5-a469-983b98207236
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=470860299 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_rand_intr_trigger.470860299
Directory /workspace/6.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/6.gpio_random_dout_din.866737898
Short name T214
Test name
Test status
Simulation time 27792653 ps
CPU time 0.77 seconds
Started Apr 18 12:30:40 PM PDT 24
Finished Apr 18 12:30:41 PM PDT 24
Peak memory 195316 kb
Host smart-4eb666c4-e66f-4969-94a1-4e31abf11ece
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=866737898 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_random_dout_din.866737898
Directory /workspace/6.gpio_random_dout_din/latest

Test location /workspace/coverage/default/6.gpio_random_dout_din_no_pullup_pulldown.1758822416
Short name T259
Test name
Test status
Simulation time 94052613 ps
CPU time 0.82 seconds
Started Apr 18 12:30:46 PM PDT 24
Finished Apr 18 12:30:48 PM PDT 24
Peak memory 195380 kb
Host smart-677b4b0c-2e65-4fce-b3ea-e3be4b7b51b3
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1758822416 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_random_dout_din_no_pullup
_pulldown.1758822416
Directory /workspace/6.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/6.gpio_random_long_reg_writes_reg_reads.758537552
Short name T593
Test name
Test status
Simulation time 458980022 ps
CPU time 3.75 seconds
Started Apr 18 12:30:36 PM PDT 24
Finished Apr 18 12:30:41 PM PDT 24
Peak memory 198052 kb
Host smart-d7492a86-7731-42fb-a3e0-4ce396f2b422
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=758537552 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_rand
om_long_reg_writes_reg_reads.758537552
Directory /workspace/6.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/6.gpio_smoke.711737989
Short name T528
Test name
Test status
Simulation time 132338624 ps
CPU time 1.21 seconds
Started Apr 18 12:30:42 PM PDT 24
Finished Apr 18 12:30:44 PM PDT 24
Peak memory 196656 kb
Host smart-da23ca65-431c-45e7-b623-a9529190f97c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=711737989 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_smoke.711737989
Directory /workspace/6.gpio_smoke/latest

Test location /workspace/coverage/default/6.gpio_smoke_no_pullup_pulldown.2682585868
Short name T66
Test name
Test status
Simulation time 66143275 ps
CPU time 1.06 seconds
Started Apr 18 12:30:44 PM PDT 24
Finished Apr 18 12:30:46 PM PDT 24
Peak memory 196292 kb
Host smart-8ab96531-b76a-4c21-b57c-bfd333d24bab
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2682585868 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_no_pullup_pulldown.2682585868
Directory /workspace/6.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/6.gpio_stress_all.464719588
Short name T546
Test name
Test status
Simulation time 41555568680 ps
CPU time 201.97 seconds
Started Apr 18 12:31:04 PM PDT 24
Finished Apr 18 12:34:32 PM PDT 24
Peak memory 198088 kb
Host smart-cd3cb0f9-a03c-4103-9f1d-aec95d895c56
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=464719588 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gp
io_stress_all.464719588
Directory /workspace/6.gpio_stress_all/latest

Test location /workspace/coverage/default/7.gpio_alert_test.2402594586
Short name T600
Test name
Test status
Simulation time 70118820 ps
CPU time 0.6 seconds
Started Apr 18 12:30:59 PM PDT 24
Finished Apr 18 12:31:01 PM PDT 24
Peak memory 194520 kb
Host smart-79c036c3-ba58-4029-8b9b-e2f68e59d4f4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2402594586 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_alert_test.2402594586
Directory /workspace/7.gpio_alert_test/latest

Test location /workspace/coverage/default/7.gpio_dout_din_regs_random_rw.2902982146
Short name T448
Test name
Test status
Simulation time 378342290 ps
CPU time 0.85 seconds
Started Apr 18 12:30:28 PM PDT 24
Finished Apr 18 12:30:30 PM PDT 24
Peak memory 196452 kb
Host smart-96ea0db5-1f50-48a4-a39a-8cbd4b71b5c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2902982146 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_dout_din_regs_random_rw.2902982146
Directory /workspace/7.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/7.gpio_filter_stress.3201263932
Short name T388
Test name
Test status
Simulation time 395163062 ps
CPU time 10.39 seconds
Started Apr 18 12:30:45 PM PDT 24
Finished Apr 18 12:30:57 PM PDT 24
Peak memory 196368 kb
Host smart-411f99b6-cd43-45b7-89e3-6fbcefb1f957
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3201263932 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_filter_stres
s.3201263932
Directory /workspace/7.gpio_filter_stress/latest

Test location /workspace/coverage/default/7.gpio_full_random.830185834
Short name T442
Test name
Test status
Simulation time 58226023 ps
CPU time 0.85 seconds
Started Apr 18 12:31:00 PM PDT 24
Finished Apr 18 12:31:03 PM PDT 24
Peak memory 195976 kb
Host smart-266a359a-b95d-44f6-923c-f43609f26457
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=830185834 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_full_random.830185834
Directory /workspace/7.gpio_full_random/latest

Test location /workspace/coverage/default/7.gpio_intr_rand_pgm.1451659924
Short name T54
Test name
Test status
Simulation time 78037675 ps
CPU time 0.65 seconds
Started Apr 18 12:30:45 PM PDT 24
Finished Apr 18 12:30:47 PM PDT 24
Peak memory 194136 kb
Host smart-3d790877-f4dd-47d4-b3f6-0bd45baf18da
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1451659924 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_intr_rand_pgm.1451659924
Directory /workspace/7.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/7.gpio_intr_with_filter_rand_intr_event.2244771380
Short name T651
Test name
Test status
Simulation time 29497389 ps
CPU time 1.37 seconds
Started Apr 18 12:30:48 PM PDT 24
Finished Apr 18 12:30:51 PM PDT 24
Peak memory 196800 kb
Host smart-b55d1110-07d1-47e8-b1a2-6e12976d784d
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2244771380 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 7.gpio_intr_with_filter_rand_intr_event.2244771380
Directory /workspace/7.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/7.gpio_rand_intr_trigger.485248380
Short name T327
Test name
Test status
Simulation time 256724106 ps
CPU time 1.46 seconds
Started Apr 18 12:30:46 PM PDT 24
Finished Apr 18 12:30:48 PM PDT 24
Peak memory 195724 kb
Host smart-1879dc0e-a90d-4078-bba7-39599aee0fbe
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=485248380 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_rand_intr_trigger.485248380
Directory /workspace/7.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/7.gpio_random_dout_din.645686957
Short name T282
Test name
Test status
Simulation time 71007823 ps
CPU time 0.89 seconds
Started Apr 18 12:30:43 PM PDT 24
Finished Apr 18 12:30:45 PM PDT 24
Peak memory 196708 kb
Host smart-c76f93da-9572-4644-9697-54f997205589
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=645686957 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_random_dout_din.645686957
Directory /workspace/7.gpio_random_dout_din/latest

Test location /workspace/coverage/default/7.gpio_random_dout_din_no_pullup_pulldown.4165699451
Short name T273
Test name
Test status
Simulation time 99432093 ps
CPU time 1.17 seconds
Started Apr 18 12:30:47 PM PDT 24
Finished Apr 18 12:30:49 PM PDT 24
Peak memory 196032 kb
Host smart-5a2ca1c9-7134-458e-b854-e656ca23fe5e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4165699451 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_random_dout_din_no_pullup
_pulldown.4165699451
Directory /workspace/7.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/7.gpio_random_long_reg_writes_reg_reads.11379855
Short name T245
Test name
Test status
Simulation time 209541367 ps
CPU time 1.83 seconds
Started Apr 18 12:30:53 PM PDT 24
Finished Apr 18 12:30:56 PM PDT 24
Peak memory 198128 kb
Host smart-486ceeab-f763-4e3e-bae7-caafef8b4541
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11379855 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_w
rites_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_rando
m_long_reg_writes_reg_reads.11379855
Directory /workspace/7.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/7.gpio_smoke.2269848044
Short name T397
Test name
Test status
Simulation time 46208576 ps
CPU time 0.88 seconds
Started Apr 18 12:30:51 PM PDT 24
Finished Apr 18 12:30:53 PM PDT 24
Peak memory 196392 kb
Host smart-a84b5522-7c0c-4e5e-9123-3de699a52f48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2269848044 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_smoke.2269848044
Directory /workspace/7.gpio_smoke/latest

Test location /workspace/coverage/default/7.gpio_smoke_no_pullup_pulldown.2659256716
Short name T221
Test name
Test status
Simulation time 34884802 ps
CPU time 1.04 seconds
Started Apr 18 12:30:41 PM PDT 24
Finished Apr 18 12:30:43 PM PDT 24
Peak memory 196284 kb
Host smart-663d3d7a-92be-4ed6-b558-2749ce19ee52
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2659256716 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_no_pullup_pulldown.2659256716
Directory /workspace/7.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/7.gpio_stress_all.139252171
Short name T178
Test name
Test status
Simulation time 5777608742 ps
CPU time 143.95 seconds
Started Apr 18 12:30:52 PM PDT 24
Finished Apr 18 12:33:17 PM PDT 24
Peak memory 197988 kb
Host smart-fe42a854-663a-4ff8-b60b-1553c6fa6bc6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=139252171 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gp
io_stress_all.139252171
Directory /workspace/7.gpio_stress_all/latest

Test location /workspace/coverage/default/8.gpio_alert_test.1287064344
Short name T43
Test name
Test status
Simulation time 12344616 ps
CPU time 0.58 seconds
Started Apr 18 12:30:48 PM PDT 24
Finished Apr 18 12:30:50 PM PDT 24
Peak memory 193824 kb
Host smart-cacd3c15-7484-4693-bf43-dff6cb3bfe68
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1287064344 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_alert_test.1287064344
Directory /workspace/8.gpio_alert_test/latest

Test location /workspace/coverage/default/8.gpio_dout_din_regs_random_rw.1874266101
Short name T279
Test name
Test status
Simulation time 23216334 ps
CPU time 0.82 seconds
Started Apr 18 12:31:01 PM PDT 24
Finished Apr 18 12:31:04 PM PDT 24
Peak memory 195176 kb
Host smart-92e953c3-1599-465f-b3a6-41b935d59c59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1874266101 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_dout_din_regs_random_rw.1874266101
Directory /workspace/8.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/8.gpio_filter_stress.2053409971
Short name T449
Test name
Test status
Simulation time 4199163095 ps
CPU time 11.24 seconds
Started Apr 18 12:30:42 PM PDT 24
Finished Apr 18 12:30:54 PM PDT 24
Peak memory 196556 kb
Host smart-26b0154b-85a3-4731-a669-da4b301defc9
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2053409971 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_filter_stres
s.2053409971
Directory /workspace/8.gpio_filter_stress/latest

Test location /workspace/coverage/default/8.gpio_full_random.1992282051
Short name T162
Test name
Test status
Simulation time 332466966 ps
CPU time 0.91 seconds
Started Apr 18 12:31:07 PM PDT 24
Finished Apr 18 12:31:15 PM PDT 24
Peak memory 196964 kb
Host smart-bc52186f-c17d-4919-9891-d4fdbef66c3e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1992282051 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_full_random.1992282051
Directory /workspace/8.gpio_full_random/latest

Test location /workspace/coverage/default/8.gpio_intr_rand_pgm.2969903833
Short name T354
Test name
Test status
Simulation time 85419621 ps
CPU time 1.3 seconds
Started Apr 18 12:30:56 PM PDT 24
Finished Apr 18 12:30:59 PM PDT 24
Peak memory 197964 kb
Host smart-8446f367-5fe5-47a2-820a-9f7eb30694cd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2969903833 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_intr_rand_pgm.2969903833
Directory /workspace/8.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/8.gpio_intr_with_filter_rand_intr_event.1813105997
Short name T292
Test name
Test status
Simulation time 347883545 ps
CPU time 3.39 seconds
Started Apr 18 12:31:02 PM PDT 24
Finished Apr 18 12:31:09 PM PDT 24
Peak memory 198024 kb
Host smart-e8b61e1f-3217-4220-af57-39e55a03abc1
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1813105997 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 8.gpio_intr_with_filter_rand_intr_event.1813105997
Directory /workspace/8.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/8.gpio_rand_intr_trigger.3050496410
Short name T200
Test name
Test status
Simulation time 1139284232 ps
CPU time 2.85 seconds
Started Apr 18 12:30:55 PM PDT 24
Finished Apr 18 12:30:58 PM PDT 24
Peak memory 195856 kb
Host smart-ff470100-a61e-4d97-b56d-3b9bf9b8aadd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3050496410 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_rand_intr_trigger.
3050496410
Directory /workspace/8.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/8.gpio_random_dout_din.575702142
Short name T665
Test name
Test status
Simulation time 49825491 ps
CPU time 1.11 seconds
Started Apr 18 12:30:50 PM PDT 24
Finished Apr 18 12:30:52 PM PDT 24
Peak memory 196096 kb
Host smart-3722f477-4913-44d3-867c-c6b7c3eda32b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=575702142 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_random_dout_din.575702142
Directory /workspace/8.gpio_random_dout_din/latest

Test location /workspace/coverage/default/8.gpio_random_dout_din_no_pullup_pulldown.4165867118
Short name T586
Test name
Test status
Simulation time 47987876 ps
CPU time 1.15 seconds
Started Apr 18 12:31:03 PM PDT 24
Finished Apr 18 12:31:09 PM PDT 24
Peak memory 195912 kb
Host smart-28db959a-3f52-455d-86b4-7fb4df67c059
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4165867118 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_random_dout_din_no_pullup
_pulldown.4165867118
Directory /workspace/8.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/8.gpio_random_long_reg_writes_reg_reads.304164516
Short name T582
Test name
Test status
Simulation time 295480420 ps
CPU time 3.57 seconds
Started Apr 18 12:30:53 PM PDT 24
Finished Apr 18 12:30:57 PM PDT 24
Peak memory 197936 kb
Host smart-5ead418d-6978-4ebc-bfca-69f17aef0b41
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=304164516 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_rand
om_long_reg_writes_reg_reads.304164516
Directory /workspace/8.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/8.gpio_smoke.1413866244
Short name T104
Test name
Test status
Simulation time 738000211 ps
CPU time 0.95 seconds
Started Apr 18 12:31:03 PM PDT 24
Finished Apr 18 12:31:09 PM PDT 24
Peak memory 195680 kb
Host smart-e89e5363-a7d2-41b8-822b-72002e554346
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1413866244 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_smoke.1413866244
Directory /workspace/8.gpio_smoke/latest

Test location /workspace/coverage/default/8.gpio_smoke_no_pullup_pulldown.484442493
Short name T541
Test name
Test status
Simulation time 44679931 ps
CPU time 1.24 seconds
Started Apr 18 12:30:59 PM PDT 24
Finished Apr 18 12:31:01 PM PDT 24
Peak memory 196480 kb
Host smart-74d60680-4798-4b27-a579-319ecec88e05
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=484442493 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_no_pullup_pulldown.484442493
Directory /workspace/8.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/8.gpio_stress_all.1025063313
Short name T633
Test name
Test status
Simulation time 47834586314 ps
CPU time 219.53 seconds
Started Apr 18 12:31:00 PM PDT 24
Finished Apr 18 12:34:42 PM PDT 24
Peak memory 198048 kb
Host smart-25e889f7-b7b2-4969-b187-32cee623ddc5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1025063313 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.g
pio_stress_all.1025063313
Directory /workspace/8.gpio_stress_all/latest

Test location /workspace/coverage/default/8.gpio_stress_all_with_rand_reset.375841032
Short name T58
Test name
Test status
Simulation time 123904288215 ps
CPU time 1827.37 seconds
Started Apr 18 12:30:52 PM PDT 24
Finished Apr 18 01:01:21 PM PDT 24
Peak memory 198128 kb
Host smart-4f39f44e-5cc1-46a2-ae72-3375418d3d81
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=375841032 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_stress_all_with_rand_reset.375841032
Directory /workspace/8.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.gpio_alert_test.835444140
Short name T260
Test name
Test status
Simulation time 42957610 ps
CPU time 0.58 seconds
Started Apr 18 12:30:56 PM PDT 24
Finished Apr 18 12:30:58 PM PDT 24
Peak memory 194740 kb
Host smart-b5433b8e-37bb-4d7a-9d18-6816dc51df4e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=835444140 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_alert_test.835444140
Directory /workspace/9.gpio_alert_test/latest

Test location /workspace/coverage/default/9.gpio_dout_din_regs_random_rw.1005450041
Short name T254
Test name
Test status
Simulation time 29939766 ps
CPU time 0.88 seconds
Started Apr 18 12:30:47 PM PDT 24
Finished Apr 18 12:30:49 PM PDT 24
Peak memory 195856 kb
Host smart-b0fe149a-0af2-42ec-b3e7-d1994c608c8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1005450041 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_dout_din_regs_random_rw.1005450041
Directory /workspace/9.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/9.gpio_filter_stress.1467867636
Short name T535
Test name
Test status
Simulation time 494718075 ps
CPU time 24.28 seconds
Started Apr 18 12:30:54 PM PDT 24
Finished Apr 18 12:31:19 PM PDT 24
Peak memory 197940 kb
Host smart-ff311590-0d32-48a3-9096-dab32b0ca365
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1467867636 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_filter_stres
s.1467867636
Directory /workspace/9.gpio_filter_stress/latest

Test location /workspace/coverage/default/9.gpio_full_random.2696627905
Short name T682
Test name
Test status
Simulation time 133733019 ps
CPU time 0.72 seconds
Started Apr 18 12:30:59 PM PDT 24
Finished Apr 18 12:31:00 PM PDT 24
Peak memory 195380 kb
Host smart-597aa411-834a-4237-b6d6-75c26e924a02
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2696627905 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_full_random.2696627905
Directory /workspace/9.gpio_full_random/latest

Test location /workspace/coverage/default/9.gpio_intr_rand_pgm.1413563513
Short name T202
Test name
Test status
Simulation time 68561488 ps
CPU time 0.78 seconds
Started Apr 18 12:31:04 PM PDT 24
Finished Apr 18 12:31:09 PM PDT 24
Peak memory 195484 kb
Host smart-7c187a90-56ce-49fd-b2ed-41d63227bc5e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1413563513 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_intr_rand_pgm.1413563513
Directory /workspace/9.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/9.gpio_intr_with_filter_rand_intr_event.2696914138
Short name T626
Test name
Test status
Simulation time 75180954 ps
CPU time 1 seconds
Started Apr 18 12:30:49 PM PDT 24
Finished Apr 18 12:30:52 PM PDT 24
Peak memory 195956 kb
Host smart-b27455e8-a9ee-4c07-a87e-3bd52ca5243f
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2696914138 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 9.gpio_intr_with_filter_rand_intr_event.2696914138
Directory /workspace/9.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/9.gpio_rand_intr_trigger.647967285
Short name T356
Test name
Test status
Simulation time 85583019 ps
CPU time 2.43 seconds
Started Apr 18 12:30:55 PM PDT 24
Finished Apr 18 12:30:58 PM PDT 24
Peak memory 196972 kb
Host smart-f004dc91-c2a5-42a5-8942-fba4392b077e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=647967285 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_rand_intr_trigger.647967285
Directory /workspace/9.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/9.gpio_random_dout_din.3196309917
Short name T697
Test name
Test status
Simulation time 37979589 ps
CPU time 1 seconds
Started Apr 18 12:31:05 PM PDT 24
Finished Apr 18 12:31:13 PM PDT 24
Peak memory 195764 kb
Host smart-29e8eb1b-ad66-4f9a-965e-58dbfcc97ca7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3196309917 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_random_dout_din.3196309917
Directory /workspace/9.gpio_random_dout_din/latest

Test location /workspace/coverage/default/9.gpio_random_dout_din_no_pullup_pulldown.3135173505
Short name T30
Test name
Test status
Simulation time 45818188 ps
CPU time 0.94 seconds
Started Apr 18 12:30:55 PM PDT 24
Finished Apr 18 12:30:56 PM PDT 24
Peak memory 196464 kb
Host smart-b6d47d98-26ce-4d46-9414-e00dcdee3192
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3135173505 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_random_dout_din_no_pullup
_pulldown.3135173505
Directory /workspace/9.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/9.gpio_random_long_reg_writes_reg_reads.3626760048
Short name T418
Test name
Test status
Simulation time 1597234952 ps
CPU time 3.85 seconds
Started Apr 18 12:30:58 PM PDT 24
Finished Apr 18 12:31:03 PM PDT 24
Peak memory 197916 kb
Host smart-5859d03d-60aa-4c5a-8395-530866f3e20a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3626760048 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_ran
dom_long_reg_writes_reg_reads.3626760048
Directory /workspace/9.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/9.gpio_smoke.794704198
Short name T547
Test name
Test status
Simulation time 103692423 ps
CPU time 0.77 seconds
Started Apr 18 12:31:01 PM PDT 24
Finished Apr 18 12:31:04 PM PDT 24
Peak memory 195348 kb
Host smart-f7efa74f-a54f-4861-b9e9-d9e36fcc6665
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=794704198 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_smoke.794704198
Directory /workspace/9.gpio_smoke/latest

Test location /workspace/coverage/default/9.gpio_smoke_no_pullup_pulldown.1761726398
Short name T329
Test name
Test status
Simulation time 180241143 ps
CPU time 1.24 seconds
Started Apr 18 12:30:56 PM PDT 24
Finished Apr 18 12:30:59 PM PDT 24
Peak memory 196672 kb
Host smart-43b7b829-19f6-44fc-8fdc-c3899b398d28
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1761726398 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_no_pullup_pulldown.1761726398
Directory /workspace/9.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/9.gpio_stress_all.371280369
Short name T516
Test name
Test status
Simulation time 23198589109 ps
CPU time 143.78 seconds
Started Apr 18 12:30:46 PM PDT 24
Finished Apr 18 12:33:10 PM PDT 24
Peak memory 198120 kb
Host smart-3e9a9521-af3b-4d2c-a6d3-2de6ae79c477
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=371280369 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gp
io_stress_all.371280369
Directory /workspace/9.gpio_stress_all/latest

Test location /workspace/coverage/default/9.gpio_stress_all_with_rand_reset.2030987724
Short name T60
Test name
Test status
Simulation time 40911512121 ps
CPU time 936.08 seconds
Started Apr 18 12:31:03 PM PDT 24
Finished Apr 18 12:46:44 PM PDT 24
Peak memory 198096 kb
Host smart-65abe8d3-882a-4b80-879f-6dd3a5a45c7c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2030987724 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_stress_all_with_rand_reset.2030987724
Directory /workspace/9.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/en_cdc_prims/0.gpio_smoke_en_cdc_prim.908812197
Short name T911
Test name
Test status
Simulation time 57915383 ps
CPU time 1.44 seconds
Started Apr 18 12:30:09 PM PDT 24
Finished Apr 18 12:30:12 PM PDT 24
Peak memory 191336 kb
Host smart-4c21ef37-f460-49a7-8424-8b1249dc3e6c
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=908812197 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_en_cdc_prim.908812197
Directory /workspace/0.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1076154230
Short name T891
Test name
Test status
Simulation time 131074563 ps
CPU time 0.88 seconds
Started Apr 18 12:30:18 PM PDT 24
Finished Apr 18 12:30:20 PM PDT 24
Peak memory 191284 kb
Host smart-5b24f156-9eb0-473d-9504-084250c9cd57
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1076154230 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.1076154230
Directory /workspace/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/1.gpio_smoke_en_cdc_prim.3383186147
Short name T862
Test name
Test status
Simulation time 38607136 ps
CPU time 1.21 seconds
Started Apr 18 12:30:18 PM PDT 24
Finished Apr 18 12:30:20 PM PDT 24
Peak memory 191296 kb
Host smart-249f11b8-1014-4b6d-8d30-e1d33667c651
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3383186147 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_en_cdc_prim.3383186147
Directory /workspace/1.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2239609356
Short name T888
Test name
Test status
Simulation time 257105905 ps
CPU time 0.75 seconds
Started Apr 18 12:30:10 PM PDT 24
Finished Apr 18 12:30:13 PM PDT 24
Peak memory 191264 kb
Host smart-1f4dc0e1-eb88-4de9-893f-a5b87ef902ee
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2239609356 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.2239609356
Directory /workspace/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/10.gpio_smoke_en_cdc_prim.2990416048
Short name T897
Test name
Test status
Simulation time 53090956 ps
CPU time 1.13 seconds
Started Apr 18 12:30:20 PM PDT 24
Finished Apr 18 12:30:22 PM PDT 24
Peak memory 191292 kb
Host smart-fa6d92f0-7944-4701-b1b8-91d0586623ea
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2990416048 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_en_cdc_prim.2990416048
Directory /workspace/10.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1217004313
Short name T913
Test name
Test status
Simulation time 150114263 ps
CPU time 1.14 seconds
Started Apr 18 12:30:27 PM PDT 24
Finished Apr 18 12:30:30 PM PDT 24
Peak memory 191376 kb
Host smart-4297c8a6-4c9b-4f83-8f05-b22b5a94cd5d
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1217004313 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1217004313
Directory /workspace/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/11.gpio_smoke_en_cdc_prim.4213491718
Short name T860
Test name
Test status
Simulation time 40813655 ps
CPU time 1.1 seconds
Started Apr 18 12:30:25 PM PDT 24
Finished Apr 18 12:30:28 PM PDT 24
Peak memory 197844 kb
Host smart-d3b542f1-38bb-4873-b008-fa207737bb19
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4213491718 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_en_cdc_prim.4213491718
Directory /workspace/11.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4189824398
Short name T863
Test name
Test status
Simulation time 98707917 ps
CPU time 0.88 seconds
Started Apr 18 12:30:04 PM PDT 24
Finished Apr 18 12:30:06 PM PDT 24
Peak memory 195936 kb
Host smart-47b4f46a-7128-4792-8f9d-e5d6a477de4e
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4189824398 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.4189824398
Directory /workspace/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/12.gpio_smoke_en_cdc_prim.1371026042
Short name T921
Test name
Test status
Simulation time 214433865 ps
CPU time 1.01 seconds
Started Apr 18 12:30:07 PM PDT 24
Finished Apr 18 12:30:09 PM PDT 24
Peak memory 191244 kb
Host smart-4a602fa5-f2a6-4092-80bd-4808039ec463
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1371026042 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_en_cdc_prim.1371026042
Directory /workspace/12.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2894140707
Short name T887
Test name
Test status
Simulation time 194920592 ps
CPU time 1.38 seconds
Started Apr 18 12:30:23 PM PDT 24
Finished Apr 18 12:30:26 PM PDT 24
Peak memory 191372 kb
Host smart-66d307a3-7a3d-40c7-807c-6984d1cd6518
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2894140707 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2894140707
Directory /workspace/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/13.gpio_smoke_en_cdc_prim.661232612
Short name T938
Test name
Test status
Simulation time 143863406 ps
CPU time 1.33 seconds
Started Apr 18 12:31:05 PM PDT 24
Finished Apr 18 12:31:14 PM PDT 24
Peak memory 189692 kb
Host smart-afb68bdc-4475-49bc-8f8a-d149c4d3e690
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=661232612 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_en_cdc_prim.661232612
Directory /workspace/13.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1322567528
Short name T928
Test name
Test status
Simulation time 136878813 ps
CPU time 1.16 seconds
Started Apr 18 12:30:25 PM PDT 24
Finished Apr 18 12:30:28 PM PDT 24
Peak memory 191472 kb
Host smart-bb8c6e87-a674-4635-a9b8-f835895e058b
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1322567528 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1322567528
Directory /workspace/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/14.gpio_smoke_en_cdc_prim.1954001234
Short name T867
Test name
Test status
Simulation time 43320910 ps
CPU time 1.12 seconds
Started Apr 18 12:30:13 PM PDT 24
Finished Apr 18 12:30:16 PM PDT 24
Peak memory 191356 kb
Host smart-43a7d366-e130-4bbb-bb56-fb4c4170e9f2
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1954001234 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_en_cdc_prim.1954001234
Directory /workspace/14.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1886097542
Short name T935
Test name
Test status
Simulation time 151702120 ps
CPU time 1.21 seconds
Started Apr 18 12:30:24 PM PDT 24
Finished Apr 18 12:30:31 PM PDT 24
Peak memory 197672 kb
Host smart-262d24c2-bc57-4c28-b643-ac582f92177c
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1886097542 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1886097542
Directory /workspace/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/15.gpio_smoke_en_cdc_prim.3279638011
Short name T843
Test name
Test status
Simulation time 103449418 ps
CPU time 0.95 seconds
Started Apr 18 12:30:25 PM PDT 24
Finished Apr 18 12:30:28 PM PDT 24
Peak memory 191480 kb
Host smart-0f561acc-d784-4aa6-a769-6aa9e1c4580d
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3279638011 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_en_cdc_prim.3279638011
Directory /workspace/15.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3942277310
Short name T924
Test name
Test status
Simulation time 42600252 ps
CPU time 0.96 seconds
Started Apr 18 12:30:13 PM PDT 24
Finished Apr 18 12:30:16 PM PDT 24
Peak memory 191348 kb
Host smart-1338f73c-6889-4291-9d40-5bc0276ac50d
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3942277310 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3942277310
Directory /workspace/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/16.gpio_smoke_en_cdc_prim.2594369928
Short name T899
Test name
Test status
Simulation time 44822149 ps
CPU time 1.16 seconds
Started Apr 18 12:30:20 PM PDT 24
Finished Apr 18 12:30:22 PM PDT 24
Peak memory 191480 kb
Host smart-f969b900-7be7-4b89-9941-9addf7fe1405
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2594369928 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_en_cdc_prim.2594369928
Directory /workspace/16.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2294534095
Short name T865
Test name
Test status
Simulation time 531832762 ps
CPU time 1.19 seconds
Started Apr 18 12:31:34 PM PDT 24
Finished Apr 18 12:31:36 PM PDT 24
Peak memory 191276 kb
Host smart-15c88b6d-9b84-4e83-b318-574a170daf78
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2294534095 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2294534095
Directory /workspace/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/17.gpio_smoke_en_cdc_prim.2614434368
Short name T923
Test name
Test status
Simulation time 1054822297 ps
CPU time 1.39 seconds
Started Apr 18 12:30:22 PM PDT 24
Finished Apr 18 12:30:25 PM PDT 24
Peak memory 191468 kb
Host smart-af680a33-e78f-47a5-8737-6216f2e92c2b
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2614434368 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_en_cdc_prim.2614434368
Directory /workspace/17.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3565375082
Short name T884
Test name
Test status
Simulation time 489004931 ps
CPU time 1.25 seconds
Started Apr 18 12:31:05 PM PDT 24
Finished Apr 18 12:31:14 PM PDT 24
Peak memory 189580 kb
Host smart-63f43811-d414-4732-9535-617b2b717327
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3565375082 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3565375082
Directory /workspace/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/18.gpio_smoke_en_cdc_prim.1840558268
Short name T857
Test name
Test status
Simulation time 94641217 ps
CPU time 0.98 seconds
Started Apr 18 12:30:10 PM PDT 24
Finished Apr 18 12:30:13 PM PDT 24
Peak memory 191360 kb
Host smart-0d8127e3-59aa-4ae1-a9bc-cbd564fa78d0
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1840558268 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_en_cdc_prim.1840558268
Directory /workspace/18.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim.714053536
Short name T929
Test name
Test status
Simulation time 337536826 ps
CPU time 1.43 seconds
Started Apr 18 12:30:27 PM PDT 24
Finished Apr 18 12:30:30 PM PDT 24
Peak memory 191484 kb
Host smart-2fca4e74-8037-4612-a32f-f45f8d2dbc1e
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=714053536 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.714053536
Directory /workspace/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/19.gpio_smoke_en_cdc_prim.4191095531
Short name T919
Test name
Test status
Simulation time 195327935 ps
CPU time 1.35 seconds
Started Apr 18 12:30:29 PM PDT 24
Finished Apr 18 12:30:31 PM PDT 24
Peak memory 191784 kb
Host smart-f8298904-3249-4579-b21d-338e0631134a
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4191095531 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_en_cdc_prim.4191095531
Directory /workspace/19.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2508556830
Short name T901
Test name
Test status
Simulation time 206690076 ps
CPU time 1.09 seconds
Started Apr 18 12:31:05 PM PDT 24
Finished Apr 18 12:31:14 PM PDT 24
Peak memory 189848 kb
Host smart-4b92aa3f-b06b-4729-bd2b-842af7939ed8
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2508556830 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2508556830
Directory /workspace/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/2.gpio_smoke_en_cdc_prim.1867878855
Short name T898
Test name
Test status
Simulation time 121039158 ps
CPU time 1.27 seconds
Started Apr 18 12:30:14 PM PDT 24
Finished Apr 18 12:30:17 PM PDT 24
Peak memory 191800 kb
Host smart-99d3a873-dec0-481f-8b13-ae3776ebfd0f
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1867878855 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_en_cdc_prim.1867878855
Directory /workspace/2.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4239023035
Short name T910
Test name
Test status
Simulation time 239401994 ps
CPU time 1.08 seconds
Started Apr 18 12:30:28 PM PDT 24
Finished Apr 18 12:30:30 PM PDT 24
Peak memory 191324 kb
Host smart-6ac15f89-2b8a-4552-b6ff-24579f9ddb66
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4239023035 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.4239023035
Directory /workspace/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/20.gpio_smoke_en_cdc_prim.2327123202
Short name T917
Test name
Test status
Simulation time 365167218 ps
CPU time 1.3 seconds
Started Apr 18 12:30:23 PM PDT 24
Finished Apr 18 12:30:26 PM PDT 24
Peak memory 191796 kb
Host smart-29a50e5d-602f-4462-b974-1493e624cd42
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2327123202 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_en_cdc_prim.2327123202
Directory /workspace/20.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1701927995
Short name T900
Test name
Test status
Simulation time 170549260 ps
CPU time 1.18 seconds
Started Apr 18 12:30:13 PM PDT 24
Finished Apr 18 12:30:16 PM PDT 24
Peak memory 197644 kb
Host smart-5269f594-d25a-435e-9b6e-2d8c0e81fa27
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1701927995 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1701927995
Directory /workspace/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/21.gpio_smoke_en_cdc_prim.4108011709
Short name T934
Test name
Test status
Simulation time 790590241 ps
CPU time 1.07 seconds
Started Apr 18 12:30:20 PM PDT 24
Finished Apr 18 12:30:23 PM PDT 24
Peak memory 191480 kb
Host smart-06ea492c-e368-4424-89f9-6d3572eea35c
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4108011709 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_en_cdc_prim.4108011709
Directory /workspace/21.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim.636090163
Short name T839
Test name
Test status
Simulation time 41517001 ps
CPU time 1.05 seconds
Started Apr 18 12:30:10 PM PDT 24
Finished Apr 18 12:30:18 PM PDT 24
Peak memory 191332 kb
Host smart-f18f135e-7f24-4475-8510-064bd5093d1b
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=636090163 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.636090163
Directory /workspace/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/22.gpio_smoke_en_cdc_prim.713894979
Short name T866
Test name
Test status
Simulation time 35309745 ps
CPU time 1.03 seconds
Started Apr 18 12:30:23 PM PDT 24
Finished Apr 18 12:30:25 PM PDT 24
Peak memory 191360 kb
Host smart-f33572d1-f837-4d77-a580-4cf4383ca3c0
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=713894979 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_en_cdc_prim.713894979
Directory /workspace/22.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2298462063
Short name T893
Test name
Test status
Simulation time 117166517 ps
CPU time 0.94 seconds
Started Apr 18 12:30:18 PM PDT 24
Finished Apr 18 12:30:20 PM PDT 24
Peak memory 191380 kb
Host smart-2ee1d227-223c-4c64-ac41-3efc4441b17c
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2298462063 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2298462063
Directory /workspace/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/23.gpio_smoke_en_cdc_prim.2821848985
Short name T879
Test name
Test status
Simulation time 79213205 ps
CPU time 0.8 seconds
Started Apr 18 12:30:21 PM PDT 24
Finished Apr 18 12:30:24 PM PDT 24
Peak memory 195900 kb
Host smart-2d3e3fb3-b00d-4416-8813-1a09917102ec
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2821848985 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_en_cdc_prim.2821848985
Directory /workspace/23.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3055374267
Short name T933
Test name
Test status
Simulation time 209246373 ps
CPU time 1.43 seconds
Started Apr 18 12:30:20 PM PDT 24
Finished Apr 18 12:30:23 PM PDT 24
Peak memory 191324 kb
Host smart-3eb935e6-0aa4-4c58-a6fe-5602b64fd553
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3055374267 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3055374267
Directory /workspace/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/24.gpio_smoke_en_cdc_prim.1706937672
Short name T854
Test name
Test status
Simulation time 209366332 ps
CPU time 1.04 seconds
Started Apr 18 12:30:16 PM PDT 24
Finished Apr 18 12:30:19 PM PDT 24
Peak memory 191280 kb
Host smart-4a37ef13-2c78-406f-ac33-b657519577bc
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1706937672 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_en_cdc_prim.1706937672
Directory /workspace/24.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4224537133
Short name T915
Test name
Test status
Simulation time 67225918 ps
CPU time 1.2 seconds
Started Apr 18 12:30:08 PM PDT 24
Finished Apr 18 12:30:11 PM PDT 24
Peak memory 191324 kb
Host smart-b30b47af-21c0-48c2-842e-07f1ff5ab61f
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4224537133 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.4224537133
Directory /workspace/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/25.gpio_smoke_en_cdc_prim.2956537469
Short name T889
Test name
Test status
Simulation time 376570335 ps
CPU time 1.58 seconds
Started Apr 18 12:30:13 PM PDT 24
Finished Apr 18 12:30:17 PM PDT 24
Peak memory 197916 kb
Host smart-5f6478f7-87f1-4b53-8f84-9963e330a0b0
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2956537469 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_en_cdc_prim.2956537469
Directory /workspace/25.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim.491969862
Short name T859
Test name
Test status
Simulation time 301160749 ps
CPU time 1.36 seconds
Started Apr 18 12:30:08 PM PDT 24
Finished Apr 18 12:30:11 PM PDT 24
Peak memory 191380 kb
Host smart-4952215f-9d7a-4b13-9182-575632b0fce8
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=491969862 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.491969862
Directory /workspace/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/26.gpio_smoke_en_cdc_prim.1711520410
Short name T873
Test name
Test status
Simulation time 170212153 ps
CPU time 0.91 seconds
Started Apr 18 12:30:19 PM PDT 24
Finished Apr 18 12:30:21 PM PDT 24
Peak memory 191256 kb
Host smart-f80580a9-3423-444a-9a20-6276e06ac2c8
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1711520410 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_en_cdc_prim.1711520410
Directory /workspace/26.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1243397570
Short name T904
Test name
Test status
Simulation time 28696714 ps
CPU time 0.88 seconds
Started Apr 18 12:30:12 PM PDT 24
Finished Apr 18 12:30:16 PM PDT 24
Peak memory 197180 kb
Host smart-533c24eb-9656-4808-993b-6bb6ce8852c8
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1243397570 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1243397570
Directory /workspace/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/27.gpio_smoke_en_cdc_prim.4281358331
Short name T870
Test name
Test status
Simulation time 81925250 ps
CPU time 1.23 seconds
Started Apr 18 12:30:13 PM PDT 24
Finished Apr 18 12:30:16 PM PDT 24
Peak memory 191384 kb
Host smart-0928cf0e-72c8-4929-b1c6-e424f4c737e6
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4281358331 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_en_cdc_prim.4281358331
Directory /workspace/27.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim.866046643
Short name T936
Test name
Test status
Simulation time 623043011 ps
CPU time 0.98 seconds
Started Apr 18 12:30:16 PM PDT 24
Finished Apr 18 12:30:18 PM PDT 24
Peak memory 191280 kb
Host smart-da57b6e3-ebff-47ad-882f-3e1c94f2533f
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=866046643 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.866046643
Directory /workspace/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/28.gpio_smoke_en_cdc_prim.1571492841
Short name T892
Test name
Test status
Simulation time 85336699 ps
CPU time 0.86 seconds
Started Apr 18 12:30:44 PM PDT 24
Finished Apr 18 12:30:46 PM PDT 24
Peak memory 195820 kb
Host smart-3c504d45-cdd0-451e-9da2-84d58d6f5f25
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1571492841 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_en_cdc_prim.1571492841
Directory /workspace/28.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim.630444271
Short name T855
Test name
Test status
Simulation time 306193823 ps
CPU time 1.23 seconds
Started Apr 18 12:30:13 PM PDT 24
Finished Apr 18 12:30:21 PM PDT 24
Peak memory 197648 kb
Host smart-8d0ee490-7898-463c-b254-e4ed9d3649cf
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=630444271 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.630444271
Directory /workspace/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/29.gpio_smoke_en_cdc_prim.308536094
Short name T882
Test name
Test status
Simulation time 72317282 ps
CPU time 1.27 seconds
Started Apr 18 12:30:14 PM PDT 24
Finished Apr 18 12:30:18 PM PDT 24
Peak memory 191344 kb
Host smart-22f09102-8737-41b9-ac8e-ce2c39b4c6af
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=308536094 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_en_cdc_prim.308536094
Directory /workspace/29.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1806528289
Short name T927
Test name
Test status
Simulation time 50560256 ps
CPU time 1 seconds
Started Apr 18 12:30:22 PM PDT 24
Finished Apr 18 12:30:25 PM PDT 24
Peak memory 191412 kb
Host smart-bab871fb-520e-4b50-be86-fcf7a3f4174a
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1806528289 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1806528289
Directory /workspace/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/3.gpio_smoke_en_cdc_prim.1322037016
Short name T853
Test name
Test status
Simulation time 55190055 ps
CPU time 1.39 seconds
Started Apr 18 12:30:12 PM PDT 24
Finished Apr 18 12:30:15 PM PDT 24
Peak memory 191348 kb
Host smart-7188bdf1-9bc9-47f4-9004-9c69fb92367f
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1322037016 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_en_cdc_prim.1322037016
Directory /workspace/3.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim.434623760
Short name T906
Test name
Test status
Simulation time 63396105 ps
CPU time 1.01 seconds
Started Apr 18 12:30:24 PM PDT 24
Finished Apr 18 12:30:26 PM PDT 24
Peak memory 197620 kb
Host smart-0c06a7b4-e06b-4156-8def-61a2769553c3
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=434623760 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.434623760
Directory /workspace/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/30.gpio_smoke_en_cdc_prim.3221767945
Short name T845
Test name
Test status
Simulation time 155225203 ps
CPU time 1.08 seconds
Started Apr 18 12:30:27 PM PDT 24
Finished Apr 18 12:30:30 PM PDT 24
Peak memory 191484 kb
Host smart-bcff4b3b-5971-46e7-9dd6-d08719975c56
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3221767945 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_en_cdc_prim.3221767945
Directory /workspace/30.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1443535236
Short name T912
Test name
Test status
Simulation time 110743149 ps
CPU time 0.81 seconds
Started Apr 18 12:30:26 PM PDT 24
Finished Apr 18 12:30:29 PM PDT 24
Peak memory 191376 kb
Host smart-29626dab-e02b-471d-a916-7d8083d47840
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1443535236 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1443535236
Directory /workspace/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/31.gpio_smoke_en_cdc_prim.3004671360
Short name T871
Test name
Test status
Simulation time 31062927 ps
CPU time 0.84 seconds
Started Apr 18 12:30:24 PM PDT 24
Finished Apr 18 12:30:26 PM PDT 24
Peak memory 191280 kb
Host smart-49d1c09c-f5e3-4785-8977-1a5026f8a3ac
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3004671360 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_en_cdc_prim.3004671360
Directory /workspace/31.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4262736347
Short name T909
Test name
Test status
Simulation time 99918112 ps
CPU time 1.43 seconds
Started Apr 18 12:30:31 PM PDT 24
Finished Apr 18 12:30:33 PM PDT 24
Peak memory 191352 kb
Host smart-be56719d-4491-44ac-9e1b-dbc59d8d5c58
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4262736347 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.4262736347
Directory /workspace/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/32.gpio_smoke_en_cdc_prim.1742431058
Short name T914
Test name
Test status
Simulation time 73173413 ps
CPU time 0.82 seconds
Started Apr 18 12:30:26 PM PDT 24
Finished Apr 18 12:30:29 PM PDT 24
Peak memory 191276 kb
Host smart-5084a82e-8dc2-4da4-a9bc-d7f1e9233ad9
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1742431058 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_en_cdc_prim.1742431058
Directory /workspace/32.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2967652266
Short name T847
Test name
Test status
Simulation time 173229531 ps
CPU time 1.01 seconds
Started Apr 18 12:30:17 PM PDT 24
Finished Apr 18 12:30:19 PM PDT 24
Peak memory 191292 kb
Host smart-e3746966-b99a-4170-a4ef-1cfd7b576794
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2967652266 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2967652266
Directory /workspace/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/33.gpio_smoke_en_cdc_prim.1436414229
Short name T920
Test name
Test status
Simulation time 109002392 ps
CPU time 0.78 seconds
Started Apr 18 12:30:23 PM PDT 24
Finished Apr 18 12:30:30 PM PDT 24
Peak memory 196368 kb
Host smart-f10f0862-aca4-4215-bc37-fb2a046e7103
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1436414229 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_en_cdc_prim.1436414229
Directory /workspace/33.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1853855349
Short name T864
Test name
Test status
Simulation time 688785480 ps
CPU time 1.25 seconds
Started Apr 18 12:30:26 PM PDT 24
Finished Apr 18 12:30:29 PM PDT 24
Peak memory 191464 kb
Host smart-8d83e3ea-a30c-4232-bf61-bc69b54bbb82
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1853855349 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1853855349
Directory /workspace/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/34.gpio_smoke_en_cdc_prim.2348831931
Short name T852
Test name
Test status
Simulation time 30366150 ps
CPU time 0.74 seconds
Started Apr 18 12:30:10 PM PDT 24
Finished Apr 18 12:30:13 PM PDT 24
Peak memory 191228 kb
Host smart-5d808031-903c-432d-82e4-dc53d26a37cd
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2348831931 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_en_cdc_prim.2348831931
Directory /workspace/34.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2722762736
Short name T894
Test name
Test status
Simulation time 71961226 ps
CPU time 0.92 seconds
Started Apr 18 12:30:13 PM PDT 24
Finished Apr 18 12:30:16 PM PDT 24
Peak memory 196976 kb
Host smart-49baef4b-6c48-4d7e-be5e-7d807551272f
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2722762736 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2722762736
Directory /workspace/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/35.gpio_smoke_en_cdc_prim.2600520901
Short name T886
Test name
Test status
Simulation time 352075213 ps
CPU time 0.89 seconds
Started Apr 18 12:30:25 PM PDT 24
Finished Apr 18 12:30:28 PM PDT 24
Peak memory 196096 kb
Host smart-bfa21519-f0cf-4f3d-bf67-f86f20b86371
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2600520901 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_en_cdc_prim.2600520901
Directory /workspace/35.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2211324059
Short name T875
Test name
Test status
Simulation time 63823953 ps
CPU time 1.18 seconds
Started Apr 18 12:30:13 PM PDT 24
Finished Apr 18 12:30:17 PM PDT 24
Peak memory 197264 kb
Host smart-70614e59-53cb-41f5-9eea-985095805e87
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2211324059 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2211324059
Directory /workspace/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/36.gpio_smoke_en_cdc_prim.1680299198
Short name T846
Test name
Test status
Simulation time 76810702 ps
CPU time 1.19 seconds
Started Apr 18 12:30:23 PM PDT 24
Finished Apr 18 12:30:25 PM PDT 24
Peak memory 191548 kb
Host smart-3ece9487-1068-4461-827c-050a7947fbd6
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1680299198 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_en_cdc_prim.1680299198
Directory /workspace/36.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim.939746851
Short name T874
Test name
Test status
Simulation time 63113271 ps
CPU time 0.76 seconds
Started Apr 18 12:30:15 PM PDT 24
Finished Apr 18 12:30:20 PM PDT 24
Peak memory 191256 kb
Host smart-78c6b3e6-35ab-40d4-9f57-082c433ce282
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=939746851 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.939746851
Directory /workspace/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/37.gpio_smoke_en_cdc_prim.19767245
Short name T890
Test name
Test status
Simulation time 57324077 ps
CPU time 1.05 seconds
Started Apr 18 12:30:25 PM PDT 24
Finished Apr 18 12:30:28 PM PDT 24
Peak memory 196228 kb
Host smart-b17d1e3c-8469-449b-b9fc-4f5444eaacf5
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=19767245 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_en_cdc_prim.19767245
Directory /workspace/37.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim.144556110
Short name T931
Test name
Test status
Simulation time 95567315 ps
CPU time 0.74 seconds
Started Apr 18 12:30:19 PM PDT 24
Finished Apr 18 12:30:21 PM PDT 24
Peak memory 191248 kb
Host smart-9180f9ae-dfa3-4ef7-afa7-13412445d9ea
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=144556110 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.144556110
Directory /workspace/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/38.gpio_smoke_en_cdc_prim.3820508363
Short name T869
Test name
Test status
Simulation time 50295898 ps
CPU time 1.39 seconds
Started Apr 18 12:30:10 PM PDT 24
Finished Apr 18 12:30:14 PM PDT 24
Peak memory 197632 kb
Host smart-1477c15e-9863-4b4e-a776-c4aedd226a58
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3820508363 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_en_cdc_prim.3820508363
Directory /workspace/38.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3037487515
Short name T903
Test name
Test status
Simulation time 71348035 ps
CPU time 1.17 seconds
Started Apr 18 12:30:27 PM PDT 24
Finished Apr 18 12:30:30 PM PDT 24
Peak memory 191272 kb
Host smart-1030fb2b-2cb4-4432-90cc-89b30057999f
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3037487515 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3037487515
Directory /workspace/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/39.gpio_smoke_en_cdc_prim.3562910905
Short name T895
Test name
Test status
Simulation time 226668338 ps
CPU time 1.04 seconds
Started Apr 18 12:30:22 PM PDT 24
Finished Apr 18 12:30:25 PM PDT 24
Peak memory 191380 kb
Host smart-cacc79b9-f382-41d5-a32b-c18866c78c4d
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3562910905 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_en_cdc_prim.3562910905
Directory /workspace/39.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2306634434
Short name T861
Test name
Test status
Simulation time 166924700 ps
CPU time 1.04 seconds
Started Apr 18 12:30:30 PM PDT 24
Finished Apr 18 12:30:32 PM PDT 24
Peak memory 197228 kb
Host smart-fe30980e-99cc-4e22-9aea-736be848196c
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2306634434 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2306634434
Directory /workspace/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/4.gpio_smoke_en_cdc_prim.1470396545
Short name T881
Test name
Test status
Simulation time 25994115 ps
CPU time 0.82 seconds
Started Apr 18 12:30:07 PM PDT 24
Finished Apr 18 12:30:09 PM PDT 24
Peak memory 191244 kb
Host smart-5c4b39c7-9e96-479c-bc76-9697d033f82f
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1470396545 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_en_cdc_prim.1470396545
Directory /workspace/4.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim.699130003
Short name T842
Test name
Test status
Simulation time 633515272 ps
CPU time 1.02 seconds
Started Apr 18 12:30:19 PM PDT 24
Finished Apr 18 12:30:21 PM PDT 24
Peak memory 191364 kb
Host smart-1c6028f1-8e26-4700-bdea-fad93fbb3466
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=699130003 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.699130003
Directory /workspace/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/40.gpio_smoke_en_cdc_prim.106146625
Short name T848
Test name
Test status
Simulation time 100882848 ps
CPU time 1.11 seconds
Started Apr 18 12:30:25 PM PDT 24
Finished Apr 18 12:30:28 PM PDT 24
Peak memory 191376 kb
Host smart-3ab954a5-3ced-4b7d-964d-01a6bf985aee
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=106146625 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_en_cdc_prim.106146625
Directory /workspace/40.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3668210910
Short name T930
Test name
Test status
Simulation time 354355786 ps
CPU time 1.39 seconds
Started Apr 18 12:30:29 PM PDT 24
Finished Apr 18 12:30:31 PM PDT 24
Peak memory 191376 kb
Host smart-727662eb-2136-4614-ba82-bbde60037fb4
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3668210910 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3668210910
Directory /workspace/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/41.gpio_smoke_en_cdc_prim.3038909340
Short name T841
Test name
Test status
Simulation time 70780309 ps
CPU time 1.16 seconds
Started Apr 18 12:30:25 PM PDT 24
Finished Apr 18 12:30:32 PM PDT 24
Peak memory 196400 kb
Host smart-a61b2435-007f-42b2-b62c-7852702e1803
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3038909340 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_en_cdc_prim.3038909340
Directory /workspace/41.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3421467255
Short name T902
Test name
Test status
Simulation time 44288412 ps
CPU time 1.09 seconds
Started Apr 18 12:30:13 PM PDT 24
Finished Apr 18 12:30:16 PM PDT 24
Peak memory 191372 kb
Host smart-86456155-d395-4545-955d-2dd4cd7313f6
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3421467255 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3421467255
Directory /workspace/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/42.gpio_smoke_en_cdc_prim.1276317243
Short name T907
Test name
Test status
Simulation time 172064517 ps
CPU time 0.89 seconds
Started Apr 18 12:30:33 PM PDT 24
Finished Apr 18 12:30:35 PM PDT 24
Peak memory 195936 kb
Host smart-444d70bf-7dfb-4e6b-a867-ef76db812c02
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1276317243 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_en_cdc_prim.1276317243
Directory /workspace/42.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2864249748
Short name T877
Test name
Test status
Simulation time 33075974 ps
CPU time 0.89 seconds
Started Apr 18 12:30:43 PM PDT 24
Finished Apr 18 12:30:45 PM PDT 24
Peak memory 191248 kb
Host smart-8269b941-a52e-42e2-a607-4ef86418b729
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2864249748 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2864249748
Directory /workspace/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/43.gpio_smoke_en_cdc_prim.1698700511
Short name T851
Test name
Test status
Simulation time 309526191 ps
CPU time 1.41 seconds
Started Apr 18 12:30:25 PM PDT 24
Finished Apr 18 12:30:28 PM PDT 24
Peak memory 191376 kb
Host smart-ba1af4ac-0358-4744-95ba-f6309441fdd6
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1698700511 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_en_cdc_prim.1698700511
Directory /workspace/43.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim.422210416
Short name T856
Test name
Test status
Simulation time 144704603 ps
CPU time 1.21 seconds
Started Apr 18 12:30:33 PM PDT 24
Finished Apr 18 12:30:35 PM PDT 24
Peak memory 191320 kb
Host smart-edb48b07-d4c2-4e29-8f8c-3dee7116cb10
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=422210416 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.422210416
Directory /workspace/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/44.gpio_smoke_en_cdc_prim.3806136335
Short name T908
Test name
Test status
Simulation time 24080071 ps
CPU time 0.79 seconds
Started Apr 18 12:30:30 PM PDT 24
Finished Apr 18 12:30:31 PM PDT 24
Peak memory 195676 kb
Host smart-ca0f1737-a1e9-4f06-9511-b9ad9c5d59df
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3806136335 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_en_cdc_prim.3806136335
Directory /workspace/44.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2778085425
Short name T844
Test name
Test status
Simulation time 69778974 ps
CPU time 0.85 seconds
Started Apr 18 12:31:02 PM PDT 24
Finished Apr 18 12:31:07 PM PDT 24
Peak memory 197600 kb
Host smart-9cf8d922-2506-4c82-900b-6f39f802dd08
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2778085425 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2778085425
Directory /workspace/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/45.gpio_smoke_en_cdc_prim.3842034506
Short name T868
Test name
Test status
Simulation time 54462627 ps
CPU time 0.85 seconds
Started Apr 18 12:30:47 PM PDT 24
Finished Apr 18 12:30:49 PM PDT 24
Peak memory 191428 kb
Host smart-5baea4d4-10fc-421f-885a-1ab37769b579
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3842034506 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_en_cdc_prim.3842034506
Directory /workspace/45.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim.985641074
Short name T916
Test name
Test status
Simulation time 86954973 ps
CPU time 1.22 seconds
Started Apr 18 12:30:15 PM PDT 24
Finished Apr 18 12:30:21 PM PDT 24
Peak memory 196912 kb
Host smart-2faa3efb-9000-4df0-aba3-9d4730361c2e
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=985641074 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.985641074
Directory /workspace/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/46.gpio_smoke_en_cdc_prim.2784326516
Short name T876
Test name
Test status
Simulation time 113646805 ps
CPU time 0.93 seconds
Started Apr 18 12:30:44 PM PDT 24
Finished Apr 18 12:30:46 PM PDT 24
Peak memory 196008 kb
Host smart-ec410511-7c18-40bc-9160-cee53824ccd5
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2784326516 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_en_cdc_prim.2784326516
Directory /workspace/46.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1290157220
Short name T885
Test name
Test status
Simulation time 70068697 ps
CPU time 0.72 seconds
Started Apr 18 12:30:25 PM PDT 24
Finished Apr 18 12:30:27 PM PDT 24
Peak memory 194828 kb
Host smart-a3079b46-b5fe-47b8-9691-fabee9b821d5
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1290157220 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1290157220
Directory /workspace/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/47.gpio_smoke_en_cdc_prim.1928667627
Short name T849
Test name
Test status
Simulation time 126187420 ps
CPU time 1.06 seconds
Started Apr 18 12:30:36 PM PDT 24
Finished Apr 18 12:30:38 PM PDT 24
Peak memory 191380 kb
Host smart-d059deeb-f69a-4d4f-be19-e31d6c965b98
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1928667627 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_en_cdc_prim.1928667627
Directory /workspace/47.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim.561588242
Short name T932
Test name
Test status
Simulation time 171488750 ps
CPU time 1.13 seconds
Started Apr 18 12:30:27 PM PDT 24
Finished Apr 18 12:30:30 PM PDT 24
Peak memory 191356 kb
Host smart-542eae4f-fbc6-42b1-a750-b05442ffbf6c
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=561588242 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.561588242
Directory /workspace/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/48.gpio_smoke_en_cdc_prim.3343502985
Short name T896
Test name
Test status
Simulation time 48642654 ps
CPU time 0.97 seconds
Started Apr 18 12:30:25 PM PDT 24
Finished Apr 18 12:30:27 PM PDT 24
Peak memory 191200 kb
Host smart-9ebf4b48-a92e-4cd0-8365-0c77101df54d
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3343502985 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_en_cdc_prim.3343502985
Directory /workspace/48.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2406121129
Short name T918
Test name
Test status
Simulation time 63194175 ps
CPU time 1.35 seconds
Started Apr 18 12:30:15 PM PDT 24
Finished Apr 18 12:30:19 PM PDT 24
Peak memory 191324 kb
Host smart-3b1963a3-d5b5-46c3-a1fc-7faf50e1d80c
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2406121129 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2406121129
Directory /workspace/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/49.gpio_smoke_en_cdc_prim.825263098
Short name T883
Test name
Test status
Simulation time 38297178 ps
CPU time 1.03 seconds
Started Apr 18 12:30:20 PM PDT 24
Finished Apr 18 12:30:22 PM PDT 24
Peak memory 197796 kb
Host smart-d24bde8a-434f-4579-b0d9-3b11e94fb3eb
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=825263098 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_en_cdc_prim.825263098
Directory /workspace/49.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim.119509886
Short name T925
Test name
Test status
Simulation time 191587922 ps
CPU time 0.98 seconds
Started Apr 18 12:30:23 PM PDT 24
Finished Apr 18 12:30:25 PM PDT 24
Peak memory 191356 kb
Host smart-3bbab3e7-e3d4-45e4-8244-cdead86a5fe1
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=119509886 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.119509886
Directory /workspace/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/5.gpio_smoke_en_cdc_prim.3543162988
Short name T858
Test name
Test status
Simulation time 358890845 ps
CPU time 1 seconds
Started Apr 18 12:30:26 PM PDT 24
Finished Apr 18 12:30:29 PM PDT 24
Peak memory 191520 kb
Host smart-bb0fd625-8a47-4e87-8dba-e1eb9913ddc1
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3543162988 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_en_cdc_prim.3543162988
Directory /workspace/5.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1054880155
Short name T840
Test name
Test status
Simulation time 38293542 ps
CPU time 1.29 seconds
Started Apr 18 12:30:11 PM PDT 24
Finished Apr 18 12:30:15 PM PDT 24
Peak memory 191384 kb
Host smart-287b5a42-5777-4967-8464-21ef09e3045b
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1054880155 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.1054880155
Directory /workspace/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/6.gpio_smoke_en_cdc_prim.2847215121
Short name T880
Test name
Test status
Simulation time 102859534 ps
CPU time 1.4 seconds
Started Apr 18 12:30:21 PM PDT 24
Finished Apr 18 12:30:24 PM PDT 24
Peak memory 191472 kb
Host smart-f43107cc-2d40-4ca7-a71e-3dd1fe5d26d2
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2847215121 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_en_cdc_prim.2847215121
Directory /workspace/6.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim.348606136
Short name T905
Test name
Test status
Simulation time 321291185 ps
CPU time 1.26 seconds
Started Apr 18 12:30:06 PM PDT 24
Finished Apr 18 12:30:08 PM PDT 24
Peak memory 191388 kb
Host smart-a49c7ec7-13a8-4668-a43c-4a4a519f681e
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=348606136 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.348606136
Directory /workspace/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/7.gpio_smoke_en_cdc_prim.2723098279
Short name T872
Test name
Test status
Simulation time 282880094 ps
CPU time 1.43 seconds
Started Apr 18 12:30:05 PM PDT 24
Finished Apr 18 12:30:08 PM PDT 24
Peak memory 197668 kb
Host smart-3d2d5ccb-9a59-474e-91e5-84110a3af928
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2723098279 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_en_cdc_prim.2723098279
Directory /workspace/7.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3476085069
Short name T926
Test name
Test status
Simulation time 103043376 ps
CPU time 1 seconds
Started Apr 18 12:30:20 PM PDT 24
Finished Apr 18 12:30:23 PM PDT 24
Peak memory 198004 kb
Host smart-f312739e-e1c6-4630-b9dd-d6a54333ff9a
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3476085069 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.3476085069
Directory /workspace/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/8.gpio_smoke_en_cdc_prim.1743222518
Short name T878
Test name
Test status
Simulation time 125734334 ps
CPU time 1.09 seconds
Started Apr 18 12:30:24 PM PDT 24
Finished Apr 18 12:30:32 PM PDT 24
Peak memory 191368 kb
Host smart-a96937fd-1297-4a7d-a25e-a5bfc1644e06
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1743222518 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_en_cdc_prim.1743222518
Directory /workspace/8.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1172662718
Short name T850
Test name
Test status
Simulation time 161636236 ps
CPU time 1.34 seconds
Started Apr 18 12:30:20 PM PDT 24
Finished Apr 18 12:30:22 PM PDT 24
Peak memory 191292 kb
Host smart-200614b3-aa89-40c5-a2fc-c56f48d6eb96
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1172662718 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.1172662718
Directory /workspace/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/9.gpio_smoke_en_cdc_prim.1793489795
Short name T922
Test name
Test status
Simulation time 55715364 ps
CPU time 1.59 seconds
Started Apr 18 12:30:02 PM PDT 24
Finished Apr 18 12:30:04 PM PDT 24
Peak memory 197696 kb
Host smart-8589dc00-1d52-4906-b9c3-323c9b19a333
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1793489795 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_en_cdc_prim.1793489795
Directory /workspace/9.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2442349669
Short name T937
Test name
Test status
Simulation time 122611051 ps
CPU time 1.06 seconds
Started Apr 18 12:31:22 PM PDT 24
Finished Apr 18 12:31:25 PM PDT 24
Peak memory 191324 kb
Host smart-9887de1f-f972-4a9d-ba4e-1c00f6fecd07
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2442349669 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.2442349669
Directory /workspace/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest
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