Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=31}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=31}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=31}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	36	0	36	100.00
Crosses	128	0	128	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=31}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	32	0	32	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=31}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	128	0	128	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	13802250	1			T41	91		T42	354		T43	414
all_values[1]	13802250	1			T41	91		T42	354		T43	414
all_values[2]	13802250	1			T41	91		T42	354		T43	414
all_values[3]	13802250	1			T41	91		T42	354		T43	414
all_values[4]	13802250	1			T41	91		T42	354		T43	414
all_values[5]	13802250	1			T41	91		T42	354		T43	414
all_values[6]	13802250	1			T41	91		T42	354		T43	414
all_values[7]	13802250	1			T41	91		T42	354		T43	414
all_values[8]	13802250	1			T41	91		T42	354		T43	414
all_values[9]	13802250	1			T41	91		T42	354		T43	414
all_values[10]	13802250	1			T41	91		T42	354		T43	414
all_values[11]	13802250	1			T41	91		T42	354		T43	414
all_values[12]	13802250	1			T41	91		T42	354		T43	414
all_values[13]	13802250	1			T41	91		T42	354		T43	414
all_values[14]	13802250	1			T41	91		T42	354		T43	414
all_values[15]	13802250	1			T41	91		T42	354		T43	414
all_values[16]	13802250	1			T41	91		T42	354		T43	414
all_values[17]	13802250	1			T41	91		T42	354		T43	414
all_values[18]	13802250	1			T41	91		T42	354		T43	414
all_values[19]	13802250	1			T41	91		T42	354		T43	414
all_values[20]	13802250	1			T41	91		T42	354		T43	414
all_values[21]	13802250	1			T41	91		T42	354		T43	414
all_values[22]	13802250	1			T41	91		T42	354		T43	414
all_values[23]	13802250	1			T41	91		T42	354		T43	414
all_values[24]	13802250	1			T41	91		T42	354		T43	414
all_values[25]	13802250	1			T41	91		T42	354		T43	414
all_values[26]	13802250	1			T41	91		T42	354		T43	414
all_values[27]	13802250	1			T41	91		T42	354		T43	414
all_values[28]	13802250	1			T41	91		T42	354		T43	414
all_values[29]	13802250	1			T41	91		T42	354		T43	414
all_values[30]	13802250	1			T41	91		T42	354		T43	414
all_values[31]	13802250	1			T41	91		T42	354		T43	414

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

256049902

1

T41

2279

T42

11328

T43

13248

auto[1]

185622098

1

T41

633

T44

188664

T46

16666

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

106163016

1

T41

1851

T42

11328

T43

13248

auto[1]

335508984

1

T41

1061

T44

340876

T46

30330

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	2753498	1			T41	63		T42	354		T43	414
all_values[0]	auto[0]	auto[1]	5229601	1			T41	22		T44	52173		T46	501
all_values[0]	auto[1]	auto[0]	564147	1			T41	6		T44	5189		T46	29
all_values[0]	auto[1]	auto[1]	5255004	1			T44	53871		T46	495		T47	838
all_values[1]	auto[0]	auto[0]	2752358	1			T41	52		T42	354		T43	414
all_values[1]	auto[0]	auto[1]	5238322	1			T41	13		T44	54100		T46	467
all_values[1]	auto[1]	auto[0]	565621	1			T41	16		T44	5404		T46	74
all_values[1]	auto[1]	auto[1]	5245949	1			T41	10		T44	51975		T46	437
all_values[2]	auto[0]	auto[0]	2753047	1			T41	35		T42	354		T43	414
all_values[2]	auto[0]	auto[1]	5268706	1			T41	24		T44	52669		T46	459
all_values[2]	auto[1]	auto[0]	562330	1			T41	6		T44	6615		T46	59
all_values[2]	auto[1]	auto[1]	5218167	1			T41	26		T44	53253		T46	531
all_values[3]	auto[0]	auto[0]	2746165	1			T41	39		T42	354		T43	414
all_values[3]	auto[0]	auto[1]	5250626	1			T41	25		T44	54487		T46	580
all_values[3]	auto[1]	auto[0]	572152	1			T41	3		T44	5492		T46	119
all_values[3]	auto[1]	auto[1]	5233307	1			T41	24		T44	52041		T46	313
all_values[4]	auto[0]	auto[0]	2749162	1			T41	43		T42	354		T43	414
all_values[4]	auto[0]	auto[1]	5217320	1			T41	25		T44	54206		T46	455
all_values[4]	auto[1]	auto[0]	566526	1			T41	1		T44	5431		T46	66
all_values[4]	auto[1]	auto[1]	5269242	1			T41	22		T44	52794		T46	489
all_values[5]	auto[0]	auto[0]	2753046	1			T41	52		T42	354		T43	414
all_values[5]	auto[0]	auto[1]	5248746	1			T41	23		T44	55089		T46	594
all_values[5]	auto[1]	auto[0]	568464	1			T41	15		T44	5397		T46	37
all_values[5]	auto[1]	auto[1]	5231994	1			T41	1		T44	52070		T46	385
all_values[6]	auto[0]	auto[0]	2753573	1			T41	49		T42	354		T43	414
all_values[6]	auto[0]	auto[1]	5248938	1			T41	36		T44	53777		T46	402
all_values[6]	auto[1]	auto[0]	564622	1			T41	3		T44	5653		T46	69
all_values[6]	auto[1]	auto[1]	5235117	1			T41	3		T44	52927		T46	536
all_values[7]	auto[0]	auto[0]	2752696	1			T41	44		T42	354		T43	414
all_values[7]	auto[0]	auto[1]	5271032	1			T41	14		T44	52871		T46	586
all_values[7]	auto[1]	auto[0]	566565	1			T41	4		T44	6461		T46	40
all_values[7]	auto[1]	auto[1]	5211957	1			T41	29		T44	52597		T46	427
all_values[8]	auto[0]	auto[0]	2747979	1			T41	62		T42	354		T43	414
all_values[8]	auto[0]	auto[1]	5246770	1			T41	12		T44	53604		T46	441
all_values[8]	auto[1]	auto[0]	567250	1			T41	7		T44	5899		T46	71
all_values[8]	auto[1]	auto[1]	5240251	1			T41	10		T44	52909		T46	550
all_values[9]	auto[0]	auto[0]	2752134	1			T41	43		T42	354		T43	414
all_values[9]	auto[0]	auto[1]	5250330	1			T41	9		T44	52175		T46	516
all_values[9]	auto[1]	auto[0]	568606	1			T41	29		T44	5965		T46	68
all_values[9]	auto[1]	auto[1]	5231180	1			T41	10		T44	54568		T46	451
all_values[10]	auto[0]	auto[0]	2749499	1			T41	52		T42	354		T43	414
all_values[10]	auto[0]	auto[1]	5248339	1			T41	23		T44	53082		T46	400
all_values[10]	auto[1]	auto[0]	564983	1			T41	14		T44	5570		T46	85
all_values[10]	auto[1]	auto[1]	5239429	1			T41	2		T44	53305		T46	559
all_values[11]	auto[0]	auto[0]	2748634	1			T41	51		T42	354		T43	414
all_values[11]	auto[0]	auto[1]	5244520	1			T41	7		T44	52906		T46	564
all_values[11]	auto[1]	auto[0]	558070	1			T41	18		T44	5361		T46	52
all_values[11]	auto[1]	auto[1]	5251026	1			T41	15		T44	54108		T46	389
all_values[12]	auto[0]	auto[0]	2749920	1			T41	70		T42	354		T43	414
all_values[12]	auto[0]	auto[1]	5249351	1			T41	14		T44	52936		T46	480
all_values[12]	auto[1]	auto[0]	564123	1			T44	5698		T46	62		T47	90
all_values[12]	auto[1]	auto[1]	5238856	1			T41	7		T44	53908		T46	458
all_values[13]	auto[0]	auto[0]	2752082	1			T41	45		T42	354		T43	414
all_values[13]	auto[0]	auto[1]	5267123	1			T41	33		T44	53054		T46	439
all_values[13]	auto[1]	auto[0]	565038	1			T41	3		T44	6287		T46	63
all_values[13]	auto[1]	auto[1]	5218007	1			T41	10		T44	53167		T46	491
all_values[14]	auto[0]	auto[0]	2745941	1			T41	53		T42	354		T43	414
all_values[14]	auto[0]	auto[1]	5259571	1			T41	12		T44	54404		T46	511
all_values[14]	auto[1]	auto[0]	572653	1			T41	12		T44	5577		T46	28
all_values[14]	auto[1]	auto[1]	5224085	1			T41	14		T44	52362		T46	520
all_values[15]	auto[0]	auto[0]	2744631	1			T41	37		T42	354		T43	414
all_values[15]	auto[0]	auto[1]	5238775	1			T41	15		T44	52937		T46	481
all_values[15]	auto[1]	auto[0]	569129	1			T41	20		T44	5925		T46	79
all_values[15]	auto[1]	auto[1]	5249715	1			T41	19		T44	53354		T46	468
all_values[16]	auto[0]	auto[0]	2761136	1			T41	49		T42	354		T43	414
all_values[16]	auto[0]	auto[1]	5233569	1			T41	19		T44	53623		T46	503
all_values[16]	auto[1]	auto[0]	564994	1			T41	9		T44	5514		T46	70
all_values[16]	auto[1]	auto[1]	5242551	1			T41	14		T44	53186		T46	427
all_values[17]	auto[0]	auto[0]	2747491	1			T41	54		T42	354		T43	414
all_values[17]	auto[0]	auto[1]	5233259	1			T41	37		T44	52667		T46	560
all_values[17]	auto[1]	auto[0]	567390	1			T44	5999		T46	80		T47	100
all_values[17]	auto[1]	auto[1]	5254110	1			T44	53708		T46	380		T47	968
all_values[18]	auto[0]	auto[0]	2746270	1			T41	48		T42	354		T43	414
all_values[18]	auto[0]	auto[1]	5254635	1			T41	21		T44	53472		T46	422
all_values[18]	auto[1]	auto[0]	568795	1			T41	6		T44	5774		T46	50
all_values[18]	auto[1]	auto[1]	5232550	1			T41	16		T44	52709		T46	491
all_values[19]	auto[0]	auto[0]	2745465	1			T41	43		T42	354		T43	414
all_values[19]	auto[0]	auto[1]	5285240	1			T41	48		T44	54731		T46	424
all_values[19]	auto[1]	auto[0]	569481	1			T44	5601		T46	59		T47	34
all_values[19]	auto[1]	auto[1]	5202064	1			T44	52150		T46	535		T47	526
all_values[20]	auto[0]	auto[0]	2751955	1			T41	48		T42	354		T43	414
all_values[20]	auto[0]	auto[1]	5243642	1			T41	23		T44	53596		T46	598
all_values[20]	auto[1]	auto[0]	558915	1			T41	9		T44	5393		T46	95
all_values[20]	auto[1]	auto[1]	5247738	1			T41	11		T44	53259		T46	275
all_values[21]	auto[0]	auto[0]	2750662	1			T41	44		T42	354		T43	414
all_values[21]	auto[0]	auto[1]	5239306	1			T41	34		T44	52410		T46	473
all_values[21]	auto[1]	auto[0]	566733	1			T44	6008		T46	38		T47	63
all_values[21]	auto[1]	auto[1]	5245549	1			T41	13		T44	53820		T46	512
all_values[22]	auto[0]	auto[0]	2754395	1			T41	36		T42	354		T43	414
all_values[22]	auto[0]	auto[1]	5250182	1			T41	32		T44	52095		T46	467
all_values[22]	auto[1]	auto[0]	567122	1			T41	15		T44	5794		T46	82
all_values[22]	auto[1]	auto[1]	5230551	1			T41	8		T44	54390		T46	439
all_values[23]	auto[0]	auto[0]	2759556	1			T41	71		T42	354		T43	414
all_values[23]	auto[0]	auto[1]	5233584	1			T41	14		T44	52448		T46	428
all_values[23]	auto[1]	auto[0]	563852	1			T41	3		T44	5463		T46	96
all_values[23]	auto[1]	auto[1]	5245258	1			T41	3		T44	54630		T46	502
all_values[24]	auto[0]	auto[0]	2753770	1			T41	60		T42	354		T43	414
all_values[24]	auto[0]	auto[1]	5283433	1			T41	18		T44	53401		T46	576
all_values[24]	auto[1]	auto[0]	569303	1			T41	3		T44	5143		T46	62
all_values[24]	auto[1]	auto[1]	5195744	1			T41	10		T44	53715		T46	393
all_values[25]	auto[0]	auto[0]	2748555	1			T41	41		T42	354		T43	414
all_values[25]	auto[0]	auto[1]	5260592	1			T41	11		T44	52617		T46	492
all_values[25]	auto[1]	auto[0]	579211	1			T41	9		T44	6051		T46	28
all_values[25]	auto[1]	auto[1]	5213892	1			T41	30		T44	53442		T46	498
all_values[26]	auto[0]	auto[0]	2755364	1			T41	56		T42	354		T43	414
all_values[26]	auto[0]	auto[1]	5275315	1			T41	12		T44	53965		T46	463
all_values[26]	auto[1]	auto[0]	558480	1			T41	4		T44	6118		T46	37
all_values[26]	auto[1]	auto[1]	5213091	1			T41	19		T44	52291		T46	491
all_values[27]	auto[0]	auto[0]	2751496	1			T41	44		T42	354		T43	414
all_values[27]	auto[0]	auto[1]	5235366	1			T41	35		T44	54642		T46	427
all_values[27]	auto[1]	auto[0]	564250	1			T41	6		T44	5864		T46	48
all_values[27]	auto[1]	auto[1]	5251138	1			T41	6		T44	51899		T46	549
all_values[28]	auto[0]	auto[0]	2750433	1			T41	52		T42	354		T43	414
all_values[28]	auto[0]	auto[1]	5227672	1			T41	20		T44	52911		T46	419
all_values[28]	auto[1]	auto[0]	567198	1			T41	4		T44	5822		T46	87
all_values[28]	auto[1]	auto[1]	5256947	1			T41	15		T44	53419		T46	442
all_values[29]	auto[0]	auto[0]	2756465	1			T41	50		T42	354		T43	414
all_values[29]	auto[0]	auto[1]	5259549	1			T41	12		T44	53328		T46	501
all_values[29]	auto[1]	auto[0]	568864	1			T41	14		T44	5880		T46	68
all_values[29]	auto[1]	auto[1]	5217372	1			T41	15		T44	53518		T46	418
all_values[30]	auto[0]	auto[0]	2748298	1			T41	47		T42	354		T43	414
all_values[30]	auto[0]	auto[1]	5235615	1			T41	28		T44	52758		T46	481
all_values[30]	auto[1]	auto[0]	564381	1			T41	7		T44	5582		T46	53
all_values[30]	auto[1]	auto[1]	5253956	1			T41	9		T44	53897		T46	471
all_values[31]	auto[0]	auto[0]	2752651	1			T41	56		T42	354		T43	414
all_values[31]	auto[0]	auto[1]	5282546	1			T41	19		T44	52611		T46	579
all_values[31]	auto[1]	auto[0]	565441	1			T41	16		T44	5686		T46	71
all_values[31]	auto[1]	auto[1]	5201612	1			T44	53782		T46	319		T47	712