Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	36	0	36	100.00
Crosses	128	0	128	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	32	0	32	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	128	0	128	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	4139463	1			T41	41		T42	1		T43	1
all_pins[1]	4139463	1			T41	41		T42	1		T43	1
all_pins[2]	4139463	1			T41	41		T42	1		T43	1
all_pins[3]	4139463	1			T41	41		T42	1		T43	1
all_pins[4]	4139463	1			T41	41		T42	1		T43	1
all_pins[5]	4139463	1			T41	41		T42	1		T43	1
all_pins[6]	4139463	1			T41	41		T42	1		T43	1
all_pins[7]	4139463	1			T41	41		T42	1		T43	1
all_pins[8]	4139463	1			T41	41		T42	1		T43	1
all_pins[9]	4139463	1			T41	41		T42	1		T43	1
all_pins[10]	4139463	1			T41	41		T42	1		T43	1
all_pins[11]	4139463	1			T41	41		T42	1		T43	1
all_pins[12]	4139463	1			T41	41		T42	1		T43	1
all_pins[13]	4139463	1			T41	41		T42	1		T43	1
all_pins[14]	4139463	1			T41	41		T42	1		T43	1
all_pins[15]	4139463	1			T41	41		T42	1		T43	1
all_pins[16]	4139463	1			T41	41		T42	1		T43	1
all_pins[17]	4139463	1			T41	41		T42	1		T43	1
all_pins[18]	4139463	1			T41	41		T42	1		T43	1
all_pins[19]	4139463	1			T41	41		T42	1		T43	1
all_pins[20]	4139463	1			T41	41		T42	1		T43	1
all_pins[21]	4139463	1			T41	41		T42	1		T43	1
all_pins[22]	4139463	1			T41	41		T42	1		T43	1
all_pins[23]	4139463	1			T41	41		T42	1		T43	1
all_pins[24]	4139463	1			T41	41		T42	1		T43	1
all_pins[25]	4139463	1			T41	41		T42	1		T43	1
all_pins[26]	4139463	1			T41	41		T42	1		T43	1
all_pins[27]	4139463	1			T41	41		T42	1		T43	1
all_pins[28]	4139463	1			T41	41		T42	1		T43	1
all_pins[29]	4139463	1			T41	41		T42	1		T43	1
all_pins[30]	4139463	1			T41	41		T42	1		T43	1
all_pins[31]	4139463	1			T41	41		T42	1		T43	1

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	82270335	1			T41	1094		T42	32		T43	32
values[0x1]	50192481	1			T41	218		T44	509059		T46	4898
transitions[0x0=>0x1]	30072335	1			T41	143		T44	304904		T46	2938
transitions[0x1=>0x0]	30072191	1			T41	143		T44	304903		T46	2938

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	2573498	1			T41	41		T42	1		T43	1
all_pins[0]	values[0x1]	1565965	1			T44	16322		T46	167		T47	221
all_pins[0]	transitions[0x0=>0x1]	971903	1			T44	10018		T46	109		T47	141
all_pins[0]	transitions[0x1=>0x0]	975093	1			T44	9869		T46	65		T47	105
all_pins[1]	values[0x0]	2570418	1			T41	33		T42	1		T43	1
all_pins[1]	values[0x1]	1569045	1			T41	8		T44	15759		T46	145
all_pins[1]	transitions[0x0=>0x1]	939434	1			T41	8		T44	9405		T46	78
all_pins[1]	transitions[0x1=>0x0]	936354	1			T44	9968		T46	100		T47	122
all_pins[2]	values[0x0]	2572827	1			T41	23		T42	1		T43	1
all_pins[2]	values[0x1]	1566636	1			T41	18		T44	15882		T46	164
all_pins[2]	transitions[0x0=>0x1]	935077	1			T41	11		T44	9467		T46	112
all_pins[2]	transitions[0x1=>0x0]	937486	1			T41	1		T44	9344		T46	93
all_pins[3]	values[0x0]	2573486	1			T41	27		T42	1		T43	1
all_pins[3]	values[0x1]	1565977	1			T41	14		T44	15753		T46	109
all_pins[3]	transitions[0x0=>0x1]	939769	1			T41	4		T44	9493		T46	59
all_pins[3]	transitions[0x1=>0x0]	940428	1			T41	8		T44	9622		T46	114
all_pins[4]	values[0x0]	2568877	1			T41	29		T42	1		T43	1
all_pins[4]	values[0x1]	1570586	1			T41	12		T44	15795		T46	167
all_pins[4]	transitions[0x0=>0x1]	941059	1			T41	4		T44	9589		T46	115
all_pins[4]	transitions[0x1=>0x0]	936450	1			T41	6		T44	9547		T46	57
all_pins[5]	values[0x0]	2575010	1			T41	40		T42	1		T43	1
all_pins[5]	values[0x1]	1564453	1			T41	1		T44	15570		T46	130
all_pins[5]	transitions[0x0=>0x1]	935766	1			T44	9338		T46	81		T47	82
all_pins[5]	transitions[0x1=>0x0]	941899	1			T41	11		T44	9563		T46	118
all_pins[6]	values[0x0]	2572867	1			T41	39		T42	1		T43	1
all_pins[6]	values[0x1]	1566596	1			T41	2		T44	15625		T46	182
all_pins[6]	transitions[0x0=>0x1]	940505	1			T41	2		T44	9394		T46	128
all_pins[6]	transitions[0x1=>0x0]	938362	1			T41	1		T44	9339		T46	76
all_pins[7]	values[0x0]	2572937	1			T41	24		T42	1		T43	1
all_pins[7]	values[0x1]	1566526	1			T41	17		T44	15518		T46	130
all_pins[7]	transitions[0x0=>0x1]	937373	1			T41	17		T44	9352		T46	73
all_pins[7]	transitions[0x1=>0x0]	937443	1			T41	2		T44	9459		T46	125
all_pins[8]	values[0x0]	2566876	1			T41	37		T42	1		T43	1
all_pins[8]	values[0x1]	1572587	1			T41	4		T44	15874		T46	177
all_pins[8]	transitions[0x0=>0x1]	942887	1			T44	9689		T46	113		T47	124
all_pins[8]	transitions[0x1=>0x0]	936826	1			T41	13		T44	9333		T46	66
all_pins[9]	values[0x0]	2568768	1			T41	33		T42	1		T43	1
all_pins[9]	values[0x1]	1570695	1			T41	8		T44	16168		T46	168
all_pins[9]	transitions[0x0=>0x1]	936212	1			T41	5		T44	9734		T46	96
all_pins[9]	transitions[0x1=>0x0]	938104	1			T41	1		T44	9440		T46	105
all_pins[10]	values[0x0]	2568496	1			T41	39		T42	1		T43	1
all_pins[10]	values[0x1]	1570967	1			T41	2		T44	16051		T46	194
all_pins[10]	transitions[0x0=>0x1]	941398	1			T44	9425		T46	97		T47	143
all_pins[10]	transitions[0x1=>0x0]	941126	1			T41	6		T44	9542		T46	71
all_pins[11]	values[0x0]	2569804	1			T41	33		T42	1		T43	1
all_pins[11]	values[0x1]	1569659	1			T41	8		T44	16177		T46	122
all_pins[11]	transitions[0x0=>0x1]	939230	1			T41	6		T44	9784		T46	57
all_pins[11]	transitions[0x1=>0x0]	940538	1			T44	9658		T46	129		T47	129
all_pins[12]	values[0x0]	2569355	1			T41	39		T42	1		T43	1
all_pins[12]	values[0x1]	1570108	1			T41	2		T44	16201		T46	167
all_pins[12]	transitions[0x0=>0x1]	941828	1			T44	9679		T46	107		T47	163
all_pins[12]	transitions[0x1=>0x0]	941379	1			T41	6		T44	9655		T46	62
all_pins[13]	values[0x0]	2581474	1			T41	37		T42	1		T43	1
all_pins[13]	values[0x1]	1557989	1			T41	4		T44	15864		T46	166
all_pins[13]	transitions[0x0=>0x1]	930153	1			T41	2		T44	9264		T46	102
all_pins[13]	transitions[0x1=>0x0]	942272	1			T44	9601		T46	103		T47	116
all_pins[14]	values[0x0]	2568170	1			T41	31		T42	1		T43	1
all_pins[14]	values[0x1]	1571293	1			T41	10		T44	15631		T46	169
all_pins[14]	transitions[0x0=>0x1]	943762	1			T41	10		T44	9352		T46	93
all_pins[14]	transitions[0x1=>0x0]	930458	1			T41	4		T44	9585		T46	90
all_pins[15]	values[0x0]	2568747	1			T41	27		T42	1		T43	1
all_pins[15]	values[0x1]	1570716	1			T41	14		T44	15875		T46	161
all_pins[15]	transitions[0x0=>0x1]	939622	1			T41	6		T44	9650		T46	90
all_pins[15]	transitions[0x1=>0x0]	940199	1			T41	2		T44	9406		T46	98
all_pins[16]	values[0x0]	2570332	1			T41	35		T42	1		T43	1
all_pins[16]	values[0x1]	1569131	1			T41	6		T44	15761		T46	152
all_pins[16]	transitions[0x0=>0x1]	939472	1			T41	3		T44	9653		T46	85
all_pins[16]	transitions[0x1=>0x0]	941057	1			T41	11		T44	9767		T46	94
all_pins[17]	values[0x0]	2569463	1			T41	41		T42	1		T43	1
all_pins[17]	values[0x1]	1570000	1			T44	15627		T46	133		T47	267
all_pins[17]	transitions[0x0=>0x1]	939212	1			T44	9226		T46	79		T47	100
all_pins[17]	transitions[0x1=>0x0]	938343	1			T41	6		T44	9360		T46	98
all_pins[18]	values[0x0]	2567210	1			T41	30		T42	1		T43	1
all_pins[18]	values[0x1]	1572253	1			T41	11		T44	15522		T46	152
all_pins[18]	transitions[0x0=>0x1]	937521	1			T41	11		T44	9199		T46	99
all_pins[18]	transitions[0x1=>0x0]	935268	1			T44	9304		T46	80		T47	153
all_pins[19]	values[0x0]	2573539	1			T41	41		T42	1		T43	1
all_pins[19]	values[0x1]	1565924	1			T44	15950		T46	179		T47	152
all_pins[19]	transitions[0x0=>0x1]	935126	1			T44	9546		T46	104		T47	75
all_pins[19]	transitions[0x1=>0x0]	941455	1			T41	11		T44	9118		T46	77
all_pins[20]	values[0x0]	2568243	1			T41	33		T42	1		T43	1
all_pins[20]	values[0x1]	1571220	1			T41	8		T44	15559		T46	104
all_pins[20]	transitions[0x0=>0x1]	940701	1			T41	8		T44	9237		T46	56
all_pins[20]	transitions[0x1=>0x0]	935405	1			T44	9628		T46	131		T47	80
all_pins[21]	values[0x0]	2566986	1			T41	36		T42	1		T43	1
all_pins[21]	values[0x1]	1572477	1			T41	5		T44	16511		T46	153
all_pins[21]	transitions[0x0=>0x1]	939979	1			T41	5		T44	9857		T46	119
all_pins[21]	transitions[0x1=>0x0]	938722	1			T41	8		T44	8905		T46	70
all_pins[22]	values[0x0]	2573935	1			T41	38		T42	1		T43	1
all_pins[22]	values[0x1]	1565528	1			T41	3		T44	16250		T46	146
all_pins[22]	transitions[0x0=>0x1]	935736	1			T41	1		T44	9579		T46	81
all_pins[22]	transitions[0x1=>0x0]	942685	1			T41	3		T44	9840		T46	88
all_pins[23]	values[0x0]	2569103	1			T41	38		T42	1		T43	1
all_pins[23]	values[0x1]	1570360	1			T41	3		T44	16172		T46	172
all_pins[23]	transitions[0x0=>0x1]	940508	1			T41	3		T44	9701		T46	112
all_pins[23]	transitions[0x1=>0x0]	935676	1			T41	3		T44	9779		T46	86
all_pins[24]	values[0x0]	2577362	1			T41	36		T42	1		T43	1
all_pins[24]	values[0x1]	1562101	1			T41	5		T44	16087		T46	131
all_pins[24]	transitions[0x0=>0x1]	934125	1			T41	2		T44	9541		T46	65
all_pins[24]	transitions[0x1=>0x0]	942384	1			T44	9626		T46	106		T47	148
all_pins[25]	values[0x0]	2569718	1			T41	23		T42	1		T43	1
all_pins[25]	values[0x1]	1569745	1			T41	18		T44	15997		T46	159
all_pins[25]	transitions[0x0=>0x1]	946038	1			T41	16		T44	9582		T46	97
all_pins[25]	transitions[0x1=>0x0]	938394	1			T41	3		T44	9672		T46	69
all_pins[26]	values[0x0]	2572870	1			T41	30		T42	1		T43	1
all_pins[26]	values[0x1]	1566593	1			T41	11		T44	16098		T46	150
all_pins[26]	transitions[0x0=>0x1]	934350	1			T41	1		T44	9534		T46	91
all_pins[26]	transitions[0x1=>0x0]	937502	1			T41	8		T44	9433		T46	100
all_pins[27]	values[0x0]	2569335	1			T41	38		T42	1		T43	1
all_pins[27]	values[0x1]	1570128	1			T41	3		T44	15692		T46	196
all_pins[27]	transitions[0x0=>0x1]	940434	1			T41	1		T44	9425		T46	126
all_pins[27]	transitions[0x1=>0x0]	936899	1			T41	9		T44	9831		T46	80
all_pins[28]	values[0x0]	2571174	1			T41	33		T42	1		T43	1
all_pins[28]	values[0x1]	1568289	1			T41	8		T44	15710		T46	137
all_pins[28]	transitions[0x0=>0x1]	937650	1			T41	5		T44	9386		T46	56
all_pins[28]	transitions[0x1=>0x0]	939489	1			T44	9368		T46	115		T47	150
all_pins[29]	values[0x0]	2575874	1			T41	34		T42	1		T43	1
all_pins[29]	values[0x1]	1563589	1			T41	7		T44	16116		T46	140
all_pins[29]	transitions[0x0=>0x1]	935322	1			T41	6		T44	9791		T46	84
all_pins[29]	transitions[0x1=>0x0]	940022	1			T41	7		T44	9385		T46	81
all_pins[30]	values[0x0]	2563417	1			T41	35		T42	1		T43	1
all_pins[30]	values[0x1]	1576046	1			T41	6		T44	15768		T46	153
all_pins[30]	transitions[0x0=>0x1]	945888	1			T41	6		T44	9427		T46	102
all_pins[30]	transitions[0x1=>0x0]	933431	1			T41	7		T44	9775		T46	89
all_pins[31]	values[0x0]	2570164	1			T41	41		T42	1		T43	1
all_pins[31]	values[0x1]	1569299	1			T44	16174		T46	123		T47	185
all_pins[31]	transitions[0x0=>0x1]	934295	1			T44	9587		T46	72		T47	133
all_pins[31]	transitions[0x1=>0x0]	941042	1			T41	6		T44	9181		T46	102