Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	192	0	192	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	32	0	32	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	192	0	192	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	13802250	1			T41	91		T42	354		T43	414
all_values[1]	13802250	1			T41	91		T42	354		T43	414
all_values[2]	13802250	1			T41	91		T42	354		T43	414
all_values[3]	13802250	1			T41	91		T42	354		T43	414
all_values[4]	13802250	1			T41	91		T42	354		T43	414
all_values[5]	13802250	1			T41	91		T42	354		T43	414
all_values[6]	13802250	1			T41	91		T42	354		T43	414
all_values[7]	13802250	1			T41	91		T42	354		T43	414
all_values[8]	13802250	1			T41	91		T42	354		T43	414
all_values[9]	13802250	1			T41	91		T42	354		T43	414
all_values[10]	13802250	1			T41	91		T42	354		T43	414
all_values[11]	13802250	1			T41	91		T42	354		T43	414
all_values[12]	13802250	1			T41	91		T42	354		T43	414
all_values[13]	13802250	1			T41	91		T42	354		T43	414
all_values[14]	13802250	1			T41	91		T42	354		T43	414
all_values[15]	13802250	1			T41	91		T42	354		T43	414
all_values[16]	13802250	1			T41	91		T42	354		T43	414
all_values[17]	13802250	1			T41	91		T42	354		T43	414
all_values[18]	13802250	1			T41	91		T42	354		T43	414
all_values[19]	13802250	1			T41	91		T42	354		T43	414
all_values[20]	13802250	1			T41	91		T42	354		T43	414
all_values[21]	13802250	1			T41	91		T42	354		T43	414
all_values[22]	13802250	1			T41	91		T42	354		T43	414
all_values[23]	13802250	1			T41	91		T42	354		T43	414
all_values[24]	13802250	1			T41	91		T42	354		T43	414
all_values[25]	13802250	1			T41	91		T42	354		T43	414
all_values[26]	13802250	1			T41	91		T42	354		T43	414
all_values[27]	13802250	1			T41	91		T42	354		T43	414
all_values[28]	13802250	1			T41	91		T42	354		T43	414
all_values[29]	13802250	1			T41	91		T42	354		T43	414
all_values[30]	13802250	1			T41	91		T42	354		T43	414
all_values[31]	13802250	1			T41	91		T42	354		T43	414

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

256049902

1

T41

2279

T42

11328

T43

13248

auto[1]

185622098

1

T41

633

T44

188664

T46

16666

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

106163016

1

T41

1851

T42

11328

T43

13248

auto[1]

335508984

1

T41

1061

T44

340876

T46

30330

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

436849678

1

T41

2801

T42

11328

T43

13248

auto[1]

4822322

1

T41

111

T44

47684

T46

1377

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	192	0	192	100.00
Automatically Generated Cross Bins	192	0	192	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	2753498	1			T41	63		T42	354		T43	414
all_values[0]	auto[0]	auto[0]	auto[1]	5153819	1			T41	17		T44	51430		T46	482
all_values[0]	auto[0]	auto[1]	auto[0]	564147	1			T41	6		T44	5189		T46	29
all_values[0]	auto[0]	auto[1]	auto[1]	5179950	1			T44	53106		T46	474		T47	838
all_values[0]	auto[1]	auto[0]	auto[1]	75782	1			T41	5		T44	743		T46	19
all_values[0]	auto[1]	auto[1]	auto[1]	75054	1			T44	765		T46	21		T48	351
all_values[1]	auto[0]	auto[0]	auto[0]	2752358	1			T41	52		T42	354		T43	414
all_values[1]	auto[0]	auto[0]	auto[1]	5162689	1			T41	10		T44	53311		T46	448
all_values[1]	auto[0]	auto[1]	auto[0]	565621	1			T41	16		T44	5404		T46	74
all_values[1]	auto[0]	auto[1]	auto[1]	5171214	1			T41	9		T44	51256		T46	418
all_values[1]	auto[1]	auto[0]	auto[1]	75633	1			T41	3		T44	789		T46	19
all_values[1]	auto[1]	auto[1]	auto[1]	74735	1			T41	1		T44	719		T46	19
all_values[2]	auto[0]	auto[0]	auto[0]	2753047	1			T41	35		T42	354		T43	414
all_values[2]	auto[0]	auto[0]	auto[1]	5193192	1			T41	22		T44	51927		T46	444
all_values[2]	auto[0]	auto[1]	auto[0]	562330	1			T41	6		T44	6615		T46	59
all_values[2]	auto[0]	auto[1]	auto[1]	5143072	1			T41	25		T44	52527		T46	505
all_values[2]	auto[1]	auto[0]	auto[1]	75514	1			T41	2		T44	742		T46	15
all_values[2]	auto[1]	auto[1]	auto[1]	75095	1			T41	1		T44	726		T46	26
all_values[3]	auto[0]	auto[0]	auto[0]	2746165	1			T41	39		T42	354		T43	414
all_values[3]	auto[0]	auto[0]	auto[1]	5174568	1			T41	22		T44	53754		T46	551
all_values[3]	auto[0]	auto[1]	auto[0]	572152	1			T41	3		T44	5492		T46	119
all_values[3]	auto[0]	auto[1]	auto[1]	5158503	1			T41	22		T44	51311		T46	297
all_values[3]	auto[1]	auto[0]	auto[1]	76058	1			T41	3		T44	733		T46	29
all_values[3]	auto[1]	auto[1]	auto[1]	74804	1			T41	2		T44	730		T46	16
all_values[4]	auto[0]	auto[0]	auto[0]	2749162	1			T41	43		T42	354		T43	414
all_values[4]	auto[0]	auto[0]	auto[1]	5141772	1			T41	20		T44	53470		T46	437
all_values[4]	auto[0]	auto[1]	auto[0]	566526	1			T41	1		T44	5431		T46	66
all_values[4]	auto[0]	auto[1]	auto[1]	5193966	1			T41	22		T44	52033		T46	469
all_values[4]	auto[1]	auto[0]	auto[1]	75548	1			T41	5		T44	736		T46	18
all_values[4]	auto[1]	auto[1]	auto[1]	75276	1			T44	761		T46	20		T48	353
all_values[5]	auto[0]	auto[0]	auto[0]	2753046	1			T41	52		T42	354		T43	414
all_values[5]	auto[0]	auto[0]	auto[1]	5173446	1			T41	20		T44	54341		T46	569
all_values[5]	auto[0]	auto[1]	auto[0]	568464	1			T41	15		T44	5397		T46	37
all_values[5]	auto[0]	auto[1]	auto[1]	5156714	1			T41	1		T44	51353		T46	366
all_values[5]	auto[1]	auto[0]	auto[1]	75300	1			T41	3		T44	748		T46	25
all_values[5]	auto[1]	auto[1]	auto[1]	75280	1			T44	717		T46	19		T48	352
all_values[6]	auto[0]	auto[0]	auto[0]	2753573	1			T41	49		T42	354		T43	414
all_values[6]	auto[0]	auto[0]	auto[1]	5173464	1			T41	31		T44	53013		T46	381
all_values[6]	auto[0]	auto[1]	auto[0]	564622	1			T41	3		T44	5653		T46	69
all_values[6]	auto[0]	auto[1]	auto[1]	5159998	1			T41	3		T44	52196		T46	507
all_values[6]	auto[1]	auto[0]	auto[1]	75474	1			T41	5		T44	764		T46	21
all_values[6]	auto[1]	auto[1]	auto[1]	75119	1			T44	731		T46	29		T48	396
all_values[7]	auto[0]	auto[0]	auto[0]	2752696	1			T41	44		T42	354		T43	414
all_values[7]	auto[0]	auto[0]	auto[1]	5195124	1			T41	11		T44	52116		T46	560
all_values[7]	auto[0]	auto[1]	auto[0]	566565	1			T41	4		T44	6461		T46	40
all_values[7]	auto[0]	auto[1]	auto[1]	5136960	1			T41	28		T44	51878		T46	407
all_values[7]	auto[1]	auto[0]	auto[1]	75908	1			T41	3		T44	755		T46	26
all_values[7]	auto[1]	auto[1]	auto[1]	74997	1			T41	1		T44	719		T46	20
all_values[8]	auto[0]	auto[0]	auto[0]	2747979	1			T41	62		T42	354		T43	414
all_values[8]	auto[0]	auto[0]	auto[1]	5171170	1			T41	10		T44	52806		T46	419
all_values[8]	auto[0]	auto[1]	auto[0]	567250	1			T41	7		T44	5899		T46	71
all_values[8]	auto[0]	auto[1]	auto[1]	5165125	1			T41	10		T44	52196		T46	530
all_values[8]	auto[1]	auto[0]	auto[1]	75600	1			T41	2		T44	798		T46	22
all_values[8]	auto[1]	auto[1]	auto[1]	75126	1			T44	713		T46	20		T48	372
all_values[9]	auto[0]	auto[0]	auto[0]	2752134	1			T41	43		T42	354		T43	414
all_values[9]	auto[0]	auto[0]	auto[1]	5174878	1			T41	6		T44	51442		T46	495
all_values[9]	auto[0]	auto[1]	auto[0]	568606	1			T41	29		T44	5965		T46	68
all_values[9]	auto[0]	auto[1]	auto[1]	5156312	1			T41	8		T44	53797		T46	430
all_values[9]	auto[1]	auto[0]	auto[1]	75452	1			T41	3		T44	733		T46	21
all_values[9]	auto[1]	auto[1]	auto[1]	74868	1			T41	2		T44	771		T46	21
all_values[10]	auto[0]	auto[0]	auto[0]	2749499	1			T41	52		T42	354		T43	414
all_values[10]	auto[0]	auto[0]	auto[1]	5172648	1			T41	22		T44	52345		T46	387
all_values[10]	auto[0]	auto[1]	auto[0]	564983	1			T41	14		T44	5570		T46	85
all_values[10]	auto[0]	auto[1]	auto[1]	5164729	1			T44	52561		T46	537		T47	860
all_values[10]	auto[1]	auto[0]	auto[1]	75691	1			T41	1		T44	737		T46	13
all_values[10]	auto[1]	auto[1]	auto[1]	74700	1			T41	2		T44	744		T46	22
all_values[11]	auto[0]	auto[0]	auto[0]	2748634	1			T41	51		T42	354		T43	414
all_values[11]	auto[0]	auto[0]	auto[1]	5168922	1			T41	6		T44	52171		T46	537
all_values[11]	auto[0]	auto[1]	auto[0]	558070	1			T41	18		T44	5361		T46	52
all_values[11]	auto[0]	auto[1]	auto[1]	5175653	1			T41	14		T44	53367		T46	372
all_values[11]	auto[1]	auto[0]	auto[1]	75598	1			T41	1		T44	735		T46	27
all_values[11]	auto[1]	auto[1]	auto[1]	75373	1			T41	1		T44	741		T46	17
all_values[12]	auto[0]	auto[0]	auto[0]	2749920	1			T41	70		T42	354		T43	414
all_values[12]	auto[0]	auto[0]	auto[1]	5174399	1			T41	12		T44	52199		T46	459
all_values[12]	auto[0]	auto[1]	auto[0]	564123	1			T44	5698		T46	62		T47	90
all_values[12]	auto[0]	auto[1]	auto[1]	5163304	1			T41	7		T44	53167		T46	435
all_values[12]	auto[1]	auto[0]	auto[1]	74952	1			T41	2		T44	737		T46	21
all_values[12]	auto[1]	auto[1]	auto[1]	75552	1			T44	741		T46	23		T48	341
all_values[13]	auto[0]	auto[0]	auto[0]	2752082	1			T41	45		T42	354		T43	414
all_values[13]	auto[0]	auto[0]	auto[1]	5191471	1			T41	31		T44	52243		T46	416
all_values[13]	auto[0]	auto[1]	auto[0]	565038	1			T41	3		T44	6287		T46	63
all_values[13]	auto[0]	auto[1]	auto[1]	5142943	1			T41	10		T44	52433		T46	472
all_values[13]	auto[1]	auto[0]	auto[1]	75652	1			T41	2		T44	811		T46	23
all_values[13]	auto[1]	auto[1]	auto[1]	75064	1			T44	734		T46	19		T48	345
all_values[14]	auto[0]	auto[0]	auto[0]	2745941	1			T41	53		T42	354		T43	414
all_values[14]	auto[0]	auto[0]	auto[1]	5184345	1			T41	7		T44	53639		T46	484
all_values[14]	auto[0]	auto[1]	auto[0]	572653	1			T41	12		T44	5577		T46	28
all_values[14]	auto[0]	auto[1]	auto[1]	5148812	1			T41	13		T44	51659		T46	501
all_values[14]	auto[1]	auto[0]	auto[1]	75226	1			T41	5		T44	765		T46	27
all_values[14]	auto[1]	auto[1]	auto[1]	75273	1			T41	1		T44	703		T46	19
all_values[15]	auto[0]	auto[0]	auto[0]	2744631	1			T41	37		T42	354		T43	414
all_values[15]	auto[0]	auto[0]	auto[1]	5163511	1			T41	13		T44	52168		T46	464
all_values[15]	auto[0]	auto[1]	auto[0]	569129	1			T41	20		T44	5925		T46	79
all_values[15]	auto[0]	auto[1]	auto[1]	5174752	1			T41	18		T44	52613		T46	444
all_values[15]	auto[1]	auto[0]	auto[1]	75264	1			T41	2		T44	769		T46	17
all_values[15]	auto[1]	auto[1]	auto[1]	74963	1			T41	1		T44	741		T46	24
all_values[16]	auto[0]	auto[0]	auto[0]	2761136	1			T41	49		T42	354		T43	414
all_values[16]	auto[0]	auto[0]	auto[1]	5157812	1			T41	18		T44	52868		T46	477
all_values[16]	auto[0]	auto[1]	auto[0]	564994	1			T41	9		T44	5514		T46	70
all_values[16]	auto[0]	auto[1]	auto[1]	5167391	1			T41	13		T44	52454		T46	406
all_values[16]	auto[1]	auto[0]	auto[1]	75757	1			T41	1		T44	755		T46	26
all_values[16]	auto[1]	auto[1]	auto[1]	75160	1			T41	1		T44	732		T46	21
all_values[17]	auto[0]	auto[0]	auto[0]	2747491	1			T41	54		T42	354		T43	414
all_values[17]	auto[0]	auto[0]	auto[1]	5157191	1			T41	31		T44	51917		T46	530
all_values[17]	auto[0]	auto[1]	auto[0]	567390	1			T44	5999		T46	80		T47	100
all_values[17]	auto[0]	auto[1]	auto[1]	5179423	1			T44	53007		T46	365		T47	968
all_values[17]	auto[1]	auto[0]	auto[1]	76068	1			T41	6		T44	750		T46	30
all_values[17]	auto[1]	auto[1]	auto[1]	74687	1			T44	701		T46	15		T48	352
all_values[18]	auto[0]	auto[0]	auto[0]	2746270	1			T41	48		T42	354		T43	414
all_values[18]	auto[0]	auto[0]	auto[1]	5179186	1			T41	18		T44	52642		T46	404
all_values[18]	auto[0]	auto[1]	auto[0]	568795	1			T41	6		T44	5774		T46	50
all_values[18]	auto[0]	auto[1]	auto[1]	5157370	1			T41	15		T44	52031		T46	472
all_values[18]	auto[1]	auto[0]	auto[1]	75449	1			T41	3		T44	830		T46	18
all_values[18]	auto[1]	auto[1]	auto[1]	75180	1			T41	1		T44	678		T46	19
all_values[19]	auto[0]	auto[0]	auto[0]	2745465	1			T41	43		T42	354		T43	414
all_values[19]	auto[0]	auto[0]	auto[1]	5209563	1			T41	47		T44	54002		T46	399
all_values[19]	auto[0]	auto[1]	auto[0]	569481	1			T44	5601		T46	59		T47	34
all_values[19]	auto[0]	auto[1]	auto[1]	5126765	1			T44	51343		T46	514		T47	526
all_values[19]	auto[1]	auto[0]	auto[1]	75677	1			T41	1		T44	729		T46	25
all_values[19]	auto[1]	auto[1]	auto[1]	75299	1			T44	807		T46	21		T48	396
all_values[20]	auto[0]	auto[0]	auto[0]	2751955	1			T41	48		T42	354		T43	414
all_values[20]	auto[0]	auto[0]	auto[1]	5168098	1			T41	21		T44	52866		T46	571
all_values[20]	auto[0]	auto[1]	auto[0]	558915	1			T41	9		T44	5393		T46	95
all_values[20]	auto[0]	auto[1]	auto[1]	5172820	1			T41	10		T44	52537		T46	261
all_values[20]	auto[1]	auto[0]	auto[1]	75544	1			T41	2		T44	730		T46	27
all_values[20]	auto[1]	auto[1]	auto[1]	74918	1			T41	1		T44	722		T46	14
all_values[21]	auto[0]	auto[0]	auto[0]	2750662	1			T41	44		T42	354		T43	414
all_values[21]	auto[0]	auto[0]	auto[1]	5163577	1			T41	29		T44	51644		T46	447
all_values[21]	auto[0]	auto[1]	auto[0]	566733	1			T44	6008		T46	38		T47	63
all_values[21]	auto[0]	auto[1]	auto[1]	5170204	1			T41	13		T44	53080		T46	490
all_values[21]	auto[1]	auto[0]	auto[1]	75729	1			T41	5		T44	766		T46	26
all_values[21]	auto[1]	auto[1]	auto[1]	75345	1			T44	740		T46	22		T48	428
all_values[22]	auto[0]	auto[0]	auto[0]	2754395	1			T41	36		T42	354		T43	414
all_values[22]	auto[0]	auto[0]	auto[1]	5174760	1			T41	29		T44	51305		T46	445
all_values[22]	auto[0]	auto[1]	auto[0]	567122	1			T41	15		T44	5794		T46	82
all_values[22]	auto[0]	auto[1]	auto[1]	5155646	1			T41	7		T44	53672		T46	417
all_values[22]	auto[1]	auto[0]	auto[1]	75422	1			T41	3		T44	790		T46	22
all_values[22]	auto[1]	auto[1]	auto[1]	74905	1			T41	1		T44	718		T46	22
all_values[23]	auto[0]	auto[0]	auto[0]	2759556	1			T41	71		T42	354		T43	414
all_values[23]	auto[0]	auto[0]	auto[1]	5158235	1			T41	11		T44	51725		T46	407
all_values[23]	auto[0]	auto[1]	auto[0]	563852	1			T41	3		T44	5463		T46	96
all_values[23]	auto[0]	auto[1]	auto[1]	5169801	1			T41	3		T44	53881		T46	475
all_values[23]	auto[1]	auto[0]	auto[1]	75349	1			T41	3		T44	723		T46	21
all_values[23]	auto[1]	auto[1]	auto[1]	75457	1			T44	749		T46	27		T48	380
all_values[24]	auto[0]	auto[0]	auto[0]	2753770	1			T41	60		T42	354		T43	414
all_values[24]	auto[0]	auto[0]	auto[1]	5207395	1			T41	16		T44	52654		T46	547
all_values[24]	auto[0]	auto[1]	auto[0]	569303	1			T41	3		T44	5143		T46	62
all_values[24]	auto[0]	auto[1]	auto[1]	5120630	1			T41	10		T44	52963		T46	376
all_values[24]	auto[1]	auto[0]	auto[1]	76038	1			T41	2		T44	747		T46	29
all_values[24]	auto[1]	auto[1]	auto[1]	75114	1			T44	752		T46	17		T48	318
all_values[25]	auto[0]	auto[0]	auto[0]	2748555	1			T41	41		T42	354		T43	414
all_values[25]	auto[0]	auto[0]	auto[1]	5185451	1			T41	10		T44	51891		T46	472
all_values[25]	auto[0]	auto[1]	auto[0]	579211	1			T41	9		T44	6051		T46	28
all_values[25]	auto[0]	auto[1]	auto[1]	5138640	1			T41	29		T44	52672		T46	476
all_values[25]	auto[1]	auto[0]	auto[1]	75141	1			T41	1		T44	726		T46	20
all_values[25]	auto[1]	auto[1]	auto[1]	75252	1			T41	1		T44	770		T46	22
all_values[26]	auto[0]	auto[0]	auto[0]	2755364	1			T41	56		T42	354		T43	414
all_values[26]	auto[0]	auto[0]	auto[1]	5199535	1			T41	10		T44	53236		T46	448
all_values[26]	auto[0]	auto[1]	auto[0]	558480	1			T41	4		T44	6118		T46	37
all_values[26]	auto[0]	auto[1]	auto[1]	5137819	1			T41	19		T44	51569		T46	462
all_values[26]	auto[1]	auto[0]	auto[1]	75780	1			T41	2		T44	729		T46	15
all_values[26]	auto[1]	auto[1]	auto[1]	75272	1			T44	722		T46	29		T48	333
all_values[27]	auto[0]	auto[0]	auto[0]	2751496	1			T41	44		T42	354		T43	414
all_values[27]	auto[0]	auto[0]	auto[1]	5159879	1			T41	29		T44	53880		T46	406
all_values[27]	auto[0]	auto[1]	auto[0]	564250	1			T41	6		T44	5864		T46	48
all_values[27]	auto[0]	auto[1]	auto[1]	5175679	1			T41	6		T44	51116		T46	525
all_values[27]	auto[1]	auto[0]	auto[1]	75487	1			T41	6		T44	762		T46	21
all_values[27]	auto[1]	auto[1]	auto[1]	75459	1			T44	783		T46	24		T48	373
all_values[28]	auto[0]	auto[0]	auto[0]	2750433	1			T41	52		T42	354		T43	414
all_values[28]	auto[0]	auto[0]	auto[1]	5152483	1			T41	17		T44	52212		T46	399
all_values[28]	auto[0]	auto[1]	auto[0]	567198	1			T41	4		T44	5822		T46	87
all_values[28]	auto[0]	auto[1]	auto[1]	5181512	1			T41	15		T44	52698		T46	419
all_values[28]	auto[1]	auto[0]	auto[1]	75189	1			T41	3		T44	699		T46	20
all_values[28]	auto[1]	auto[1]	auto[1]	75435	1			T44	721		T46	23		T48	351
all_values[29]	auto[0]	auto[0]	auto[0]	2756465	1			T41	50		T42	354		T43	414
all_values[29]	auto[0]	auto[0]	auto[1]	5183947	1			T41	10		T44	52588		T46	481
all_values[29]	auto[0]	auto[1]	auto[0]	568864	1			T41	14		T44	5880		T46	68
all_values[29]	auto[0]	auto[1]	auto[1]	5142205	1			T41	15		T44	52747		T46	400
all_values[29]	auto[1]	auto[0]	auto[1]	75602	1			T41	2		T44	740		T46	20
all_values[29]	auto[1]	auto[1]	auto[1]	75167	1			T44	771		T46	18		T48	368
all_values[30]	auto[0]	auto[0]	auto[0]	2748298	1			T41	47		T42	354		T43	414
all_values[30]	auto[0]	auto[0]	auto[1]	5159969	1			T41	26		T44	51989		T46	458
all_values[30]	auto[0]	auto[1]	auto[0]	564381	1			T41	7		T44	5582		T46	53
all_values[30]	auto[0]	auto[1]	auto[1]	5178949	1			T41	9		T44	53175		T46	452
all_values[30]	auto[1]	auto[0]	auto[1]	75646	1			T41	2		T44	769		T46	23
all_values[30]	auto[1]	auto[1]	auto[1]	75007	1			T44	722		T46	19		T48	394
all_values[31]	auto[0]	auto[0]	auto[0]	2752651	1			T41	56		T42	354		T43	414
all_values[31]	auto[0]	auto[0]	auto[1]	5207319	1			T41	14		T44	51912		T46	554
all_values[31]	auto[0]	auto[1]	auto[0]	565441	1			T41	16		T44	5686		T46	71
all_values[31]	auto[0]	auto[1]	auto[1]	5125983	1			T44	52981		T46	301		T47	712
all_values[31]	auto[1]	auto[0]	auto[1]	75227	1			T41	5		T44	699		T46	25
all_values[31]	auto[1]	auto[1]	auto[1]	75629	1			T44	801		T46	18		T48	368

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal