Unified Coverage Report :: Group :: gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

Group : gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_gpio_env_0.1/gpio_env_cov.sv

---

Summary for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	192	0	192	100.00

Variables for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_pin	32	0	32	100.00	100	1	1	0
data_in	2	0	2	100.00	100	1	1	2
data_oe	2	0	2	100.00	100	1	1	2
data_out	2	0	2	100.00	100	1	1	2

Crosses for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_cross_all	192	0	192	100.00	100	1	1	0

Summary for Variable cp_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	13550442	1			T41	170		T42	680		T43	696
bins_for_gpio_bits[1]	13550442	1			T41	170		T42	680		T43	696
bins_for_gpio_bits[2]	13550442	1			T41	170		T42	680		T43	696
bins_for_gpio_bits[3]	13550442	1			T41	170		T42	680		T43	696
bins_for_gpio_bits[4]	13550442	1			T41	170		T42	680		T43	696
bins_for_gpio_bits[5]	13550442	1			T41	170		T42	680		T43	696
bins_for_gpio_bits[6]	13550442	1			T41	170		T42	680		T43	696
bins_for_gpio_bits[7]	13550442	1			T41	170		T42	680		T43	696
bins_for_gpio_bits[8]	13550442	1			T41	170		T42	680		T43	696
bins_for_gpio_bits[9]	13550442	1			T41	170		T42	680		T43	696
bins_for_gpio_bits[10]	13550442	1			T41	170		T42	680		T43	696
bins_for_gpio_bits[11]	13550442	1			T41	170		T42	680		T43	696
bins_for_gpio_bits[12]	13550442	1			T41	170		T42	680		T43	696
bins_for_gpio_bits[13]	13550442	1			T41	170		T42	680		T43	696
bins_for_gpio_bits[14]	13550442	1			T41	170		T42	680		T43	696
bins_for_gpio_bits[15]	13550442	1			T41	170		T42	680		T43	696
bins_for_gpio_bits[16]	13550442	1			T41	170		T42	680		T43	696
bins_for_gpio_bits[17]	13550442	1			T41	170		T42	680		T43	696
bins_for_gpio_bits[18]	13550442	1			T41	170		T42	680		T43	696
bins_for_gpio_bits[19]	13550442	1			T41	170		T42	680		T43	696
bins_for_gpio_bits[20]	13550442	1			T41	170		T42	680		T43	696
bins_for_gpio_bits[21]	13550442	1			T41	170		T42	680		T43	696
bins_for_gpio_bits[22]	13550442	1			T41	170		T42	680		T43	696
bins_for_gpio_bits[23]	13550442	1			T41	170		T42	680		T43	696
bins_for_gpio_bits[24]	13550442	1			T41	170		T42	680		T43	696
bins_for_gpio_bits[25]	13550442	1			T41	170		T42	680		T43	696
bins_for_gpio_bits[26]	13550442	1			T41	170		T42	680		T43	696
bins_for_gpio_bits[27]	13550442	1			T41	170		T42	680		T43	696
bins_for_gpio_bits[28]	13550442	1			T41	170		T42	680		T43	696
bins_for_gpio_bits[29]	13550442	1			T41	170		T42	680		T43	696
bins_for_gpio_bits[30]	13550442	1			T41	170		T42	680		T43	696
bins_for_gpio_bits[31]	13550442	1			T41	170		T42	680		T43	696

---

Summary for Variable data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

256020426

1

T41

2936

T42

16097

T43

15579

auto[1]

177593718

1

T41

2504

T42

5663

T43

6693

---

Summary for Variable data_oe

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_oe

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

348748164

1

T41

4232

T42

11398

T43

13172

auto[1]

84865980

1

T41

1208

T42

10362

T43

9100

---

Summary for Variable data_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_out

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

324017825

1

T41

3253

T42

11315

T43

13256

auto[1]

109596319

1

T41

2187

T42

10445

T43

9016

---

Summary for Cross cp_cross_all

Samples crossed: cp_pin data_out data_oe data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	192	0	192	100.00
Automatically Generated Cross Bins	192	0	192	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cp_cross_all

Bins

cp_pin	data_out	data_oe	data_in	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	auto[0]	auto[0]	auto[0]	5017682	1			T41	27		T42	201		T43	241
bins_for_gpio_bits[0]	auto[0]	auto[0]	auto[1]	3773179	1			T41	19		T42	14		T43	60
bins_for_gpio_bits[0]	auto[0]	auto[1]	auto[0]	1337723	1			T41	8		T42	166		T43	175
bins_for_gpio_bits[0]	auto[1]	auto[0]	auto[0]	1649099	1			T41	39		T42	121		T43	102
bins_for_gpio_bits[0]	auto[1]	auto[0]	auto[1]	449749	1			T41	8		T44	1624		T45	20
bins_for_gpio_bits[0]	auto[1]	auto[1]	auto[1]	1323010	1			T41	69		T42	178		T43	118
bins_for_gpio_bits[1]	auto[0]	auto[0]	auto[0]	5014342	1			T41	48		T42	165		T43	183
bins_for_gpio_bits[1]	auto[0]	auto[0]	auto[1]	3773935	1			T41	45		T42	14		T43	62
bins_for_gpio_bits[1]	auto[0]	auto[1]	auto[0]	1337179	1			T41	7		T42	169		T43	128
bins_for_gpio_bits[1]	auto[1]	auto[0]	auto[0]	1652102	1			T41	15		T42	176		T43	127
bins_for_gpio_bits[1]	auto[1]	auto[0]	auto[1]	451538	1			T41	14		T44	1460		T45	19
bins_for_gpio_bits[1]	auto[1]	auto[1]	auto[1]	1321346	1			T41	41		T42	156		T43	196
bins_for_gpio_bits[2]	auto[0]	auto[0]	auto[0]	5018442	1			T41	36		T42	180		T43	225
bins_for_gpio_bits[2]	auto[0]	auto[0]	auto[1]	3774005	1			T41	53		T42	15		T43	68
bins_for_gpio_bits[2]	auto[0]	auto[1]	auto[0]	1335684	1			T42	150		T43	116		T44	12923
bins_for_gpio_bits[2]	auto[1]	auto[0]	auto[0]	1650625	1			T41	16		T42	169		T43	171
bins_for_gpio_bits[2]	auto[1]	auto[0]	auto[1]	451678	1			T41	14		T44	1585		T45	22
bins_for_gpio_bits[2]	auto[1]	auto[1]	auto[1]	1320008	1			T41	51		T42	166		T43	116
bins_for_gpio_bits[3]	auto[0]	auto[0]	auto[0]	5019487	1			T41	53		T42	148		T43	182
bins_for_gpio_bits[3]	auto[0]	auto[0]	auto[1]	3769218	1			T41	17		T42	13		T43	65
bins_for_gpio_bits[3]	auto[0]	auto[1]	auto[0]	1331795	1			T41	9		T42	164		T43	138
bins_for_gpio_bits[3]	auto[1]	auto[0]	auto[0]	1656265	1			T41	28		T42	187		T43	133
bins_for_gpio_bits[3]	auto[1]	auto[0]	auto[1]	451087	1			T41	10		T44	1535		T45	10
bins_for_gpio_bits[3]	auto[1]	auto[1]	auto[1]	1322590	1			T41	53		T42	168		T43	178
bins_for_gpio_bits[4]	auto[0]	auto[0]	auto[0]	5002989	1			T41	37		T42	212		T43	233
bins_for_gpio_bits[4]	auto[0]	auto[0]	auto[1]	3787837	1			T41	55		T42	11		T43	56
bins_for_gpio_bits[4]	auto[0]	auto[1]	auto[0]	1335416	1			T41	7		T42	162		T43	127
bins_for_gpio_bits[4]	auto[1]	auto[0]	auto[0]	1652807	1			T41	15		T42	129		T43	154
bins_for_gpio_bits[4]	auto[1]	auto[0]	auto[1]	448423	1			T41	20		T44	1550		T45	28
bins_for_gpio_bits[4]	auto[1]	auto[1]	auto[1]	1322970	1			T41	36		T42	166		T43	126
bins_for_gpio_bits[5]	auto[0]	auto[0]	auto[0]	5018045	1			T41	62		T42	192		T43	227
bins_for_gpio_bits[5]	auto[0]	auto[0]	auto[1]	3774373	1			T41	39		T42	7		T43	64
bins_for_gpio_bits[5]	auto[0]	auto[1]	auto[0]	1327887	1			T41	16		T42	178		T43	150
bins_for_gpio_bits[5]	auto[1]	auto[0]	auto[0]	1658176	1			T41	29		T42	132		T43	132
bins_for_gpio_bits[5]	auto[1]	auto[0]	auto[1]	451223	1			T41	6		T44	1406		T45	5
bins_for_gpio_bits[5]	auto[1]	auto[1]	auto[1]	1320738	1			T41	18		T42	171		T43	123
bins_for_gpio_bits[6]	auto[0]	auto[0]	auto[0]	5016785	1			T41	26		T42	170		T43	198
bins_for_gpio_bits[6]	auto[0]	auto[0]	auto[1]	3772583	1			T41	40		T42	11		T43	67
bins_for_gpio_bits[6]	auto[0]	auto[1]	auto[0]	1334913	1			T41	7		T42	191		T43	139
bins_for_gpio_bits[6]	auto[1]	auto[0]	auto[0]	1652315	1			T41	8		T42	114		T43	142
bins_for_gpio_bits[6]	auto[1]	auto[0]	auto[1]	451714	1			T41	15		T44	1550		T45	24
bins_for_gpio_bits[6]	auto[1]	auto[1]	auto[1]	1322132	1			T41	74		T42	194		T43	150
bins_for_gpio_bits[7]	auto[0]	auto[0]	auto[0]	5012462	1			T41	47		T42	209		T43	205
bins_for_gpio_bits[7]	auto[0]	auto[0]	auto[1]	3775760	1			T41	45		T42	13		T43	66
bins_for_gpio_bits[7]	auto[0]	auto[1]	auto[0]	1333497	1			T41	5		T42	142		T43	145
bins_for_gpio_bits[7]	auto[1]	auto[0]	auto[0]	1653438	1			T41	40		T42	194		T43	136
bins_for_gpio_bits[7]	auto[1]	auto[0]	auto[1]	449732	1			T41	6		T44	1625		T45	27
bins_for_gpio_bits[7]	auto[1]	auto[1]	auto[1]	1325553	1			T41	27		T42	122		T43	144
bins_for_gpio_bits[8]	auto[0]	auto[0]	auto[0]	5016134	1			T41	46		T42	187		T43	192
bins_for_gpio_bits[8]	auto[0]	auto[0]	auto[1]	3770665	1			T41	29		T42	12		T43	77
bins_for_gpio_bits[8]	auto[0]	auto[1]	auto[0]	1337542	1			T41	14		T42	130		T43	156
bins_for_gpio_bits[8]	auto[1]	auto[0]	auto[0]	1654579	1			T41	32		T42	197		T43	131
bins_for_gpio_bits[8]	auto[1]	auto[0]	auto[1]	450521	1			T41	16		T44	1579		T45	32
bins_for_gpio_bits[8]	auto[1]	auto[1]	auto[1]	1321001	1			T41	33		T42	154		T43	140
bins_for_gpio_bits[9]	auto[0]	auto[0]	auto[0]	5010646	1			T41	57		T42	188		T43	205
bins_for_gpio_bits[9]	auto[0]	auto[0]	auto[1]	3775346	1			T41	43		T42	9		T43	69
bins_for_gpio_bits[9]	auto[0]	auto[1]	auto[0]	1331909	1			T41	5		T42	164		T43	146
bins_for_gpio_bits[9]	auto[1]	auto[0]	auto[0]	1652309	1			T41	19		T42	155		T43	142
bins_for_gpio_bits[9]	auto[1]	auto[0]	auto[1]	451624	1			T41	10		T44	1576		T45	8
bins_for_gpio_bits[9]	auto[1]	auto[1]	auto[1]	1328608	1			T41	36		T42	164		T43	134
bins_for_gpio_bits[10]	auto[0]	auto[0]	auto[0]	5002139	1			T41	39		T42	184		T43	258
bins_for_gpio_bits[10]	auto[0]	auto[0]	auto[1]	3784587	1			T41	24		T42	15		T43	53
bins_for_gpio_bits[10]	auto[0]	auto[1]	auto[0]	1332461	1			T41	3		T42	158		T43	126
bins_for_gpio_bits[10]	auto[1]	auto[0]	auto[0]	1654577	1			T41	45		T42	165		T43	152
bins_for_gpio_bits[10]	auto[1]	auto[0]	auto[1]	450306	1			T41	12		T44	1453		T45	28
bins_for_gpio_bits[10]	auto[1]	auto[1]	auto[1]	1326372	1			T41	47		T42	158		T43	107
bins_for_gpio_bits[11]	auto[0]	auto[0]	auto[0]	5015788	1			T41	79		T42	166		T43	184
bins_for_gpio_bits[11]	auto[0]	auto[0]	auto[1]	3777975	1			T41	13		T42	17		T43	63
bins_for_gpio_bits[11]	auto[0]	auto[1]	auto[0]	1339710	1			T41	17		T42	174		T43	142
bins_for_gpio_bits[11]	auto[1]	auto[0]	auto[0]	1645655	1			T41	47		T42	168		T43	165
bins_for_gpio_bits[11]	auto[1]	auto[0]	auto[1]	450935	1			T41	2		T44	1478		T45	20
bins_for_gpio_bits[11]	auto[1]	auto[1]	auto[1]	1320379	1			T41	12		T42	155		T43	142
bins_for_gpio_bits[12]	auto[0]	auto[0]	auto[0]	5014820	1			T41	61		T42	172		T43	201
bins_for_gpio_bits[12]	auto[0]	auto[0]	auto[1]	3776730	1			T41	23		T42	14		T43	63
bins_for_gpio_bits[12]	auto[0]	auto[1]	auto[0]	1334867	1			T42	170		T43	124		T44	12644
bins_for_gpio_bits[12]	auto[1]	auto[0]	auto[0]	1650830	1			T41	38		T42	142		T43	152
bins_for_gpio_bits[12]	auto[1]	auto[0]	auto[1]	451128	1			T41	7		T44	1510		T45	23
bins_for_gpio_bits[12]	auto[1]	auto[1]	auto[1]	1322067	1			T41	41		T42	182		T43	156
bins_for_gpio_bits[13]	auto[0]	auto[0]	auto[0]	4994604	1			T41	33		T42	193		T43	217
bins_for_gpio_bits[13]	auto[0]	auto[0]	auto[1]	3794905	1			T41	25		T42	11		T43	62
bins_for_gpio_bits[13]	auto[0]	auto[1]	auto[0]	1334149	1			T41	17		T42	148		T43	138
bins_for_gpio_bits[13]	auto[1]	auto[0]	auto[0]	1654067	1			T41	21		T42	180		T43	129
bins_for_gpio_bits[13]	auto[1]	auto[0]	auto[1]	450498	1			T41	29		T44	1664		T45	50
bins_for_gpio_bits[13]	auto[1]	auto[1]	auto[1]	1322219	1			T41	45		T42	148		T43	150
bins_for_gpio_bits[14]	auto[0]	auto[0]	auto[0]	5015095	1			T41	65		T42	208		T43	192
bins_for_gpio_bits[14]	auto[0]	auto[0]	auto[1]	3773128	1			T41	38		T42	17		T43	61
bins_for_gpio_bits[14]	auto[0]	auto[1]	auto[0]	1334639	1			T41	7		T42	159		T43	156
bins_for_gpio_bits[14]	auto[1]	auto[0]	auto[0]	1648185	1			T41	13		T42	150		T43	138
bins_for_gpio_bits[14]	auto[1]	auto[0]	auto[1]	451345	1			T41	12		T44	1410		T45	43
bins_for_gpio_bits[14]	auto[1]	auto[1]	auto[1]	1328050	1			T41	35		T42	146		T43	149
bins_for_gpio_bits[15]	auto[0]	auto[0]	auto[0]	5012205	1			T41	41		T42	152		T43	215
bins_for_gpio_bits[15]	auto[0]	auto[0]	auto[1]	3779346	1			T41	42		T42	21		T43	66
bins_for_gpio_bits[15]	auto[0]	auto[1]	auto[0]	1332260	1			T41	3		T42	163		T43	119
bins_for_gpio_bits[15]	auto[1]	auto[0]	auto[0]	1650668	1			T41	12		T42	174		T43	162
bins_for_gpio_bits[15]	auto[1]	auto[0]	auto[1]	451177	1			T41	23		T44	1571		T45	10
bins_for_gpio_bits[15]	auto[1]	auto[1]	auto[1]	1324786	1			T41	49		T42	170		T43	134
bins_for_gpio_bits[16]	auto[0]	auto[0]	auto[0]	5010775	1			T41	58		T42	167		T43	191
bins_for_gpio_bits[16]	auto[0]	auto[0]	auto[1]	3783371	1			T41	27		T42	18		T43	54
bins_for_gpio_bits[16]	auto[0]	auto[1]	auto[0]	1329861	1			T41	12		T42	156		T43	152
bins_for_gpio_bits[16]	auto[1]	auto[0]	auto[0]	1655560	1			T41	29		T42	155		T43	134
bins_for_gpio_bits[16]	auto[1]	auto[0]	auto[1]	451156	1			T41	9		T44	1602		T45	30
bins_for_gpio_bits[16]	auto[1]	auto[1]	auto[1]	1319719	1			T41	35		T42	184		T43	165
bins_for_gpio_bits[17]	auto[0]	auto[0]	auto[0]	5023328	1			T41	71		T42	183		T43	237
bins_for_gpio_bits[17]	auto[0]	auto[0]	auto[1]	3782361	1			T41	49		T42	12		T43	66
bins_for_gpio_bits[17]	auto[0]	auto[1]	auto[0]	1328553	1			T41	4		T42	122		T43	114
bins_for_gpio_bits[17]	auto[1]	auto[0]	auto[0]	1653918	1			T41	37		T42	181		T43	145
bins_for_gpio_bits[17]	auto[1]	auto[0]	auto[1]	450506	1			T41	5		T44	1626		T45	15
bins_for_gpio_bits[17]	auto[1]	auto[1]	auto[1]	1311776	1			T41	4		T42	182		T43	134
bins_for_gpio_bits[18]	auto[0]	auto[0]	auto[0]	5010264	1			T41	59		T42	194		T43	176
bins_for_gpio_bits[18]	auto[0]	auto[0]	auto[1]	3789382	1			T41	32		T42	13		T43	65
bins_for_gpio_bits[18]	auto[0]	auto[1]	auto[0]	1325489	1			T41	13		T42	162		T43	156
bins_for_gpio_bits[18]	auto[1]	auto[0]	auto[0]	1658430	1			T41	37		T42	157		T43	115
bins_for_gpio_bits[18]	auto[1]	auto[0]	auto[1]	452453	1			T41	4		T44	1563		T45	33
bins_for_gpio_bits[18]	auto[1]	auto[1]	auto[1]	1314424	1			T41	25		T42	154		T43	184
bins_for_gpio_bits[19]	auto[0]	auto[0]	auto[0]	5007468	1			T41	71		T42	165		T43	221
bins_for_gpio_bits[19]	auto[0]	auto[0]	auto[1]	3782781	1			T41	44		T42	12		T43	69
bins_for_gpio_bits[19]	auto[0]	auto[1]	auto[0]	1332884	1			T41	5		T42	163		T43	138
bins_for_gpio_bits[19]	auto[1]	auto[0]	auto[0]	1655992	1			T41	29		T42	166		T43	134
bins_for_gpio_bits[19]	auto[1]	auto[0]	auto[1]	454173	1			T41	19		T44	1466		T45	9
bins_for_gpio_bits[19]	auto[1]	auto[1]	auto[1]	1317144	1			T41	2		T42	174		T43	134
bins_for_gpio_bits[20]	auto[0]	auto[0]	auto[0]	5009199	1			T41	87		T42	189		T43	243
bins_for_gpio_bits[20]	auto[0]	auto[0]	auto[1]	3784621	1			T41	47		T42	14		T43	70
bins_for_gpio_bits[20]	auto[0]	auto[1]	auto[0]	1329422	1			T41	14		T42	166		T43	132
bins_for_gpio_bits[20]	auto[1]	auto[0]	auto[0]	1657397	1			T41	4		T42	140		T43	131
bins_for_gpio_bits[20]	auto[1]	auto[0]	auto[1]	453836	1			T41	17		T44	1556		T45	42
bins_for_gpio_bits[20]	auto[1]	auto[1]	auto[1]	1315967	1			T41	1		T42	171		T43	120
bins_for_gpio_bits[21]	auto[0]	auto[0]	auto[0]	5026036	1			T41	66		T42	150		T43	203
bins_for_gpio_bits[21]	auto[0]	auto[0]	auto[1]	3772862	1			T41	50		T42	13		T43	66
bins_for_gpio_bits[21]	auto[0]	auto[1]	auto[0]	1331948	1			T41	11		T42	158		T43	144
bins_for_gpio_bits[21]	auto[1]	auto[0]	auto[0]	1655409	1			T41	20		T42	181		T43	127
bins_for_gpio_bits[21]	auto[1]	auto[0]	auto[1]	451077	1			T41	11		T44	1666		T45	22
bins_for_gpio_bits[21]	auto[1]	auto[1]	auto[1]	1313110	1			T41	12		T42	178		T43	156
bins_for_gpio_bits[22]	auto[0]	auto[0]	auto[0]	5017332	1			T41	64		T42	174		T43	188
bins_for_gpio_bits[22]	auto[0]	auto[0]	auto[1]	3778737	1			T41	25		T42	11		T43	67
bins_for_gpio_bits[22]	auto[0]	auto[1]	auto[0]	1333374	1			T41	17		T42	180		T43	122
bins_for_gpio_bits[22]	auto[1]	auto[0]	auto[0]	1654705	1			T41	7		T42	162		T43	156
bins_for_gpio_bits[22]	auto[1]	auto[0]	auto[1]	454816	1			T41	14		T44	1660		T45	13
bins_for_gpio_bits[22]	auto[1]	auto[1]	auto[1]	1311478	1			T41	43		T42	153		T43	163
bins_for_gpio_bits[23]	auto[0]	auto[0]	auto[0]	5018571	1			T41	60		T42	165		T43	197
bins_for_gpio_bits[23]	auto[0]	auto[0]	auto[1]	3778884	1			T41	44		T42	12		T43	70
bins_for_gpio_bits[23]	auto[0]	auto[1]	auto[0]	1332506	1			T41	11		T42	180		T43	122
bins_for_gpio_bits[23]	auto[1]	auto[0]	auto[0]	1653121	1			T41	28		T42	178		T43	141
bins_for_gpio_bits[23]	auto[1]	auto[0]	auto[1]	450420	1			T41	18		T44	1600		T45	23
bins_for_gpio_bits[23]	auto[1]	auto[1]	auto[1]	1316940	1			T41	9		T42	145		T43	166
bins_for_gpio_bits[24]	auto[0]	auto[0]	auto[0]	5018505	1			T41	80		T42	204		T43	194
bins_for_gpio_bits[24]	auto[0]	auto[0]	auto[1]	3781119	1			T41	23		T42	15		T43	79
bins_for_gpio_bits[24]	auto[0]	auto[1]	auto[0]	1324881	1			T41	9		T42	149		T43	124
bins_for_gpio_bits[24]	auto[1]	auto[0]	auto[0]	1659053	1			T41	19		T42	172		T43	154
bins_for_gpio_bits[24]	auto[1]	auto[0]	auto[1]	450248	1			T41	5		T44	1592		T45	31
bins_for_gpio_bits[24]	auto[1]	auto[1]	auto[1]	1316636	1			T41	34		T42	140		T43	145
bins_for_gpio_bits[25]	auto[0]	auto[0]	auto[0]	5011662	1			T41	91		T42	182		T43	179
bins_for_gpio_bits[25]	auto[0]	auto[0]	auto[1]	3788769	1			T41	20		T42	10		T43	68
bins_for_gpio_bits[25]	auto[0]	auto[1]	auto[0]	1334039	1			T41	5		T42	156		T43	174
bins_for_gpio_bits[25]	auto[1]	auto[0]	auto[0]	1648512	1			T41	23		T42	160		T43	116
bins_for_gpio_bits[25]	auto[1]	auto[0]	auto[1]	452229	1			T41	14		T44	1601		T45	36
bins_for_gpio_bits[25]	auto[1]	auto[1]	auto[1]	1315231	1			T41	17		T42	172		T43	159
bins_for_gpio_bits[26]	auto[0]	auto[0]	auto[0]	5013575	1			T41	43		T42	190		T43	213
bins_for_gpio_bits[26]	auto[0]	auto[0]	auto[1]	3777671	1			T41	51		T42	15		T43	63
bins_for_gpio_bits[26]	auto[0]	auto[1]	auto[0]	1332823	1			T41	4		T42	124		T43	156
bins_for_gpio_bits[26]	auto[1]	auto[0]	auto[0]	1654621	1			T41	50		T42	206		T43	132
bins_for_gpio_bits[26]	auto[1]	auto[0]	auto[1]	453008	1			T41	15		T44	1529		T45	24
bins_for_gpio_bits[26]	auto[1]	auto[1]	auto[1]	1318744	1			T41	7		T42	145		T43	132
bins_for_gpio_bits[27]	auto[0]	auto[0]	auto[0]	5021324	1			T41	93		T42	169		T43	228
bins_for_gpio_bits[27]	auto[0]	auto[0]	auto[1]	3777070	1			T41	25		T42	14		T43	71
bins_for_gpio_bits[27]	auto[0]	auto[1]	auto[0]	1329401	1			T41	12		T42	146		T43	149
bins_for_gpio_bits[27]	auto[1]	auto[0]	auto[0]	1654320	1			T41	31		T42	169		T43	120
bins_for_gpio_bits[27]	auto[1]	auto[0]	auto[1]	453857	1			T41	7		T44	1416		T45	31
bins_for_gpio_bits[27]	auto[1]	auto[1]	auto[1]	1314470	1			T41	2		T42	182		T43	128
bins_for_gpio_bits[28]	auto[0]	auto[0]	auto[0]	5018784	1			T41	113		T42	193		T43	208
bins_for_gpio_bits[28]	auto[0]	auto[0]	auto[1]	3777355	1			T41	11		T42	11		T43	73
bins_for_gpio_bits[28]	auto[0]	auto[1]	auto[0]	1325520	1			T41	6		T42	172		T43	124
bins_for_gpio_bits[28]	auto[1]	auto[0]	auto[0]	1660029	1			T41	25		T42	140		T43	146
bins_for_gpio_bits[28]	auto[1]	auto[0]	auto[1]	451405	1			T41	12		T44	1451		T45	20
bins_for_gpio_bits[28]	auto[1]	auto[1]	auto[1]	1317349	1			T41	3		T42	164		T43	145
bins_for_gpio_bits[29]	auto[0]	auto[0]	auto[0]	5012817	1			T41	40		T42	170		T43	230
bins_for_gpio_bits[29]	auto[0]	auto[0]	auto[1]	3777642	1			T41	28		T42	13		T43	55
bins_for_gpio_bits[29]	auto[0]	auto[1]	auto[0]	1336812	1			T41	14		T42	157		T43	168
bins_for_gpio_bits[29]	auto[1]	auto[0]	auto[0]	1654615	1			T41	22		T42	164		T43	130
bins_for_gpio_bits[29]	auto[1]	auto[0]	auto[1]	451855	1			T41	18		T44	1534		T45	31
bins_for_gpio_bits[29]	auto[1]	auto[1]	auto[1]	1316701	1			T41	48		T42	176		T43	113
bins_for_gpio_bits[30]	auto[0]	auto[0]	auto[0]	5014619	1			T41	41		T42	171		T43	187
bins_for_gpio_bits[30]	auto[0]	auto[0]	auto[1]	3782738	1			T41	66		T42	12		T43	69
bins_for_gpio_bits[30]	auto[0]	auto[1]	auto[0]	1332880	1			T41	9		T42	182		T43	148
bins_for_gpio_bits[30]	auto[1]	auto[0]	auto[0]	1653294	1			T41	29		T42	153		T43	148
bins_for_gpio_bits[30]	auto[1]	auto[0]	auto[1]	450966	1			T41	16		T44	1515		T45	28
bins_for_gpio_bits[30]	auto[1]	auto[1]	auto[1]	1315945	1			T41	9		T42	162		T43	144
bins_for_gpio_bits[31]	auto[0]	auto[0]	auto[0]	5014421	1			T41	30		T42	177		T43	224
bins_for_gpio_bits[31]	auto[0]	auto[0]	auto[1]	3777082	1			T41	64		T42	14		T43	59
bins_for_gpio_bits[31]	auto[0]	auto[1]	auto[0]	1329439	1			T41	2		T42	161		T43	145
bins_for_gpio_bits[31]	auto[1]	auto[0]	auto[0]	1663945	1			T41	32		T42	168		T43	112
bins_for_gpio_bits[31]	auto[1]	auto[0]	auto[1]	448501	1			T41	25		T44	1517		T45	8
bins_for_gpio_bits[31]	auto[1]	auto[1]	auto[1]	1317054	1			T41	17		T42	160		T43	156

User Defined Cross Bins for cp_cross_all

Excluded/Illegal bins

NAME	COUNT	STATUS
data_oe_1_data_out_0_data_in_1	0	Illegal
data_oe_1_data_out_1_data_in_0	0	Illegal