Unified Coverage Report :: Group :: gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

Group : gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_gpio_env_0.1/gpio_env_cov.sv

---

Summary for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	36	0	36	100.00
Crosses	128	0	128	100.00

Variables for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_pin	32	0	32	100.00	100	1	1	0
data_in	2	0	2	100.00	100	1	1	2
gpio_value	2	0	2	100.00	100	1	1	2

Crosses for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_cross_pins_data_in	128	0	128	100.00	100	1	1	0

Summary for Variable cp_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	13550442	1			T41	170		T42	680		T43	696
bins_for_gpio_bits[1]	13550442	1			T41	170		T42	680		T43	696
bins_for_gpio_bits[2]	13550442	1			T41	170		T42	680		T43	696
bins_for_gpio_bits[3]	13550442	1			T41	170		T42	680		T43	696
bins_for_gpio_bits[4]	13550442	1			T41	170		T42	680		T43	696
bins_for_gpio_bits[5]	13550442	1			T41	170		T42	680		T43	696
bins_for_gpio_bits[6]	13550442	1			T41	170		T42	680		T43	696
bins_for_gpio_bits[7]	13550442	1			T41	170		T42	680		T43	696
bins_for_gpio_bits[8]	13550442	1			T41	170		T42	680		T43	696
bins_for_gpio_bits[9]	13550442	1			T41	170		T42	680		T43	696
bins_for_gpio_bits[10]	13550442	1			T41	170		T42	680		T43	696
bins_for_gpio_bits[11]	13550442	1			T41	170		T42	680		T43	696
bins_for_gpio_bits[12]	13550442	1			T41	170		T42	680		T43	696
bins_for_gpio_bits[13]	13550442	1			T41	170		T42	680		T43	696
bins_for_gpio_bits[14]	13550442	1			T41	170		T42	680		T43	696
bins_for_gpio_bits[15]	13550442	1			T41	170		T42	680		T43	696
bins_for_gpio_bits[16]	13550442	1			T41	170		T42	680		T43	696
bins_for_gpio_bits[17]	13550442	1			T41	170		T42	680		T43	696
bins_for_gpio_bits[18]	13550442	1			T41	170		T42	680		T43	696
bins_for_gpio_bits[19]	13550442	1			T41	170		T42	680		T43	696
bins_for_gpio_bits[20]	13550442	1			T41	170		T42	680		T43	696
bins_for_gpio_bits[21]	13550442	1			T41	170		T42	680		T43	696
bins_for_gpio_bits[22]	13550442	1			T41	170		T42	680		T43	696
bins_for_gpio_bits[23]	13550442	1			T41	170		T42	680		T43	696
bins_for_gpio_bits[24]	13550442	1			T41	170		T42	680		T43	696
bins_for_gpio_bits[25]	13550442	1			T41	170		T42	680		T43	696
bins_for_gpio_bits[26]	13550442	1			T41	170		T42	680		T43	696
bins_for_gpio_bits[27]	13550442	1			T41	170		T42	680		T43	696
bins_for_gpio_bits[28]	13550442	1			T41	170		T42	680		T43	696
bins_for_gpio_bits[29]	13550442	1			T41	170		T42	680		T43	696
bins_for_gpio_bits[30]	13550442	1			T41	170		T42	680		T43	696
bins_for_gpio_bits[31]	13550442	1			T41	170		T42	680		T43	696

---

Summary for Variable data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

256020426

1

T41

2936

T42

16097

T43

15579

auto[1]

177593718

1

T41

2504

T42

5663

T43

6693

---

Summary for Variable gpio_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for gpio_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

256012630

1

T41

2916

T42

16091

T43

15570

auto[1]

177601514

1

T41

2524

T42

5669

T43

6702

---

Summary for Cross cp_cross_pins_data_in

Samples crossed: cp_pin gpio_value data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cp_cross_pins_data_in

Bins

cp_pin	gpio_value	data_in	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	auto[0]	auto[0]	7767452	1			T41	71		T42	447		T43	488
bins_for_gpio_bits[0]	auto[0]	auto[1]	236822	1			T42	41		T43	30		T44	2186
bins_for_gpio_bits[0]	auto[1]	auto[0]	237052	1			T41	3		T42	41		T43	30
bins_for_gpio_bits[0]	auto[1]	auto[1]	5309116	1			T41	96		T42	151		T43	148
bins_for_gpio_bits[1]	auto[0]	auto[0]	7767403	1			T41	70		T42	470		T43	397
bins_for_gpio_bits[1]	auto[0]	auto[1]	235959	1			T42	40		T43	41		T44	2217
bins_for_gpio_bits[1]	auto[1]	auto[0]	236220	1			T42	40		T43	41		T44	2224
bins_for_gpio_bits[1]	auto[1]	auto[1]	5310860	1			T41	100		T42	130		T43	217
bins_for_gpio_bits[2]	auto[0]	auto[0]	7768343	1			T41	51		T42	461		T43	479
bins_for_gpio_bits[2]	auto[0]	auto[1]	236196	1			T42	38		T43	33		T44	2231
bins_for_gpio_bits[2]	auto[1]	auto[0]	236408	1			T41	1		T42	38		T43	33
bins_for_gpio_bits[2]	auto[1]	auto[1]	5309495	1			T41	118		T42	143		T43	151
bins_for_gpio_bits[3]	auto[0]	auto[0]	7771110	1			T41	85		T42	457		T43	411
bins_for_gpio_bits[3]	auto[0]	auto[1]	236183	1			T41	3		T42	42		T43	42
bins_for_gpio_bits[3]	auto[1]	auto[0]	236437	1			T41	5		T42	42		T43	42
bins_for_gpio_bits[3]	auto[1]	auto[1]	5306712	1			T41	77		T42	139		T43	201
bins_for_gpio_bits[4]	auto[0]	auto[0]	7754315	1			T41	59		T42	462		T43	478
bins_for_gpio_bits[4]	auto[0]	auto[1]	236649	1			T42	41		T43	36		T44	2260
bins_for_gpio_bits[4]	auto[1]	auto[0]	236897	1			T42	41		T43	36		T44	2271
bins_for_gpio_bits[4]	auto[1]	auto[1]	5322581	1			T41	111		T42	136		T43	146
bins_for_gpio_bits[5]	auto[0]	auto[0]	7767218	1			T41	106		T42	460		T43	481
bins_for_gpio_bits[5]	auto[0]	auto[1]	236644	1			T42	41		T43	27		T44	2215
bins_for_gpio_bits[5]	auto[1]	auto[0]	236890	1			T41	1		T42	42		T43	28
bins_for_gpio_bits[5]	auto[1]	auto[1]	5309690	1			T41	63		T42	137		T43	160
bins_for_gpio_bits[6]	auto[0]	auto[0]	7766916	1			T41	39		T42	430		T43	447
bins_for_gpio_bits[6]	auto[0]	auto[1]	236862	1			T41	1		T42	45		T43	32
bins_for_gpio_bits[6]	auto[1]	auto[0]	237097	1			T41	2		T42	45		T43	32
bins_for_gpio_bits[6]	auto[1]	auto[1]	5309567	1			T41	128		T42	160		T43	185
bins_for_gpio_bits[7]	auto[0]	auto[0]	7761928	1			T41	89		T42	506		T43	452
bins_for_gpio_bits[7]	auto[0]	auto[1]	237279	1			T41	3		T42	39		T43	34
bins_for_gpio_bits[7]	auto[1]	auto[0]	237469	1			T41	3		T42	39		T43	34
bins_for_gpio_bits[7]	auto[1]	auto[1]	5313766	1			T41	75		T42	96		T43	176
bins_for_gpio_bits[8]	auto[0]	auto[0]	7770684	1			T41	92		T42	473		T43	442
bins_for_gpio_bits[8]	auto[0]	auto[1]	237325	1			T42	41		T43	37		T44	2261
bins_for_gpio_bits[8]	auto[1]	auto[0]	237571	1			T42	41		T43	37		T44	2269
bins_for_gpio_bits[8]	auto[1]	auto[1]	5304862	1			T41	78		T42	125		T43	180
bins_for_gpio_bits[9]	auto[0]	auto[0]	7757557	1			T41	81		T42	463		T43	457
bins_for_gpio_bits[9]	auto[0]	auto[1]	237032	1			T41	1		T42	44		T43	36
bins_for_gpio_bits[9]	auto[1]	auto[0]	237307	1			T42	44		T43	36		T44	2239
bins_for_gpio_bits[9]	auto[1]	auto[1]	5318546	1			T41	88		T42	129		T43	167
bins_for_gpio_bits[10]	auto[0]	auto[0]	7751744	1			T41	85		T42	464		T43	505
bins_for_gpio_bits[10]	auto[0]	auto[1]	237171	1			T42	43		T43	30		T44	2183
bins_for_gpio_bits[10]	auto[1]	auto[0]	237433	1			T41	2		T42	43		T43	31
bins_for_gpio_bits[10]	auto[1]	auto[1]	5324094	1			T41	83		T42	130		T43	130
bins_for_gpio_bits[11]	auto[0]	auto[0]	7764319	1			T41	143		T42	465		T43	455
bins_for_gpio_bits[11]	auto[0]	auto[1]	236613	1			T42	42		T43	36		T44	2223
bins_for_gpio_bits[11]	auto[1]	auto[0]	236834	1			T42	43		T43	36		T44	2228
bins_for_gpio_bits[11]	auto[1]	auto[1]	5312676	1			T41	27		T42	130		T43	169
bins_for_gpio_bits[12]	auto[0]	auto[0]	7763433	1			T41	98		T42	441		T43	440
bins_for_gpio_bits[12]	auto[0]	auto[1]	236842	1			T42	43		T43	37		T44	2227
bins_for_gpio_bits[12]	auto[1]	auto[0]	237084	1			T41	1		T42	43		T43	37
bins_for_gpio_bits[12]	auto[1]	auto[1]	5313083	1			T41	71		T42	153		T43	182
bins_for_gpio_bits[13]	auto[0]	auto[0]	7746288	1			T41	70		T42	474		T43	445
bins_for_gpio_bits[13]	auto[0]	auto[1]	236290	1			T42	47		T43	39		T44	2228
bins_for_gpio_bits[13]	auto[1]	auto[0]	236532	1			T41	1		T42	47		T43	39
bins_for_gpio_bits[13]	auto[1]	auto[1]	5331332	1			T41	99		T42	112		T43	173
bins_for_gpio_bits[14]	auto[0]	auto[0]	7760414	1			T41	84		T42	476		T43	449
bins_for_gpio_bits[14]	auto[0]	auto[1]	237239	1			T41	1		T42	41		T43	36
bins_for_gpio_bits[14]	auto[1]	auto[0]	237505	1			T41	1		T42	41		T43	37
bins_for_gpio_bits[14]	auto[1]	auto[1]	5315284	1			T41	84		T42	122		T43	174
bins_for_gpio_bits[15]	auto[0]	auto[0]	7757808	1			T41	55		T42	442		T43	465
bins_for_gpio_bits[15]	auto[0]	auto[1]	237072	1			T42	47		T43	31		T44	2168
bins_for_gpio_bits[15]	auto[1]	auto[0]	237325	1			T41	1		T42	47		T43	31
bins_for_gpio_bits[15]	auto[1]	auto[1]	5318237	1			T41	114		T42	144		T43	169
bins_for_gpio_bits[16]	auto[0]	auto[0]	7758513	1			T41	96		T42	439		T43	439
bins_for_gpio_bits[16]	auto[0]	auto[1]	237384	1			T41	1		T42	39		T43	37
bins_for_gpio_bits[16]	auto[1]	auto[0]	237683	1			T41	3		T42	39		T43	38
bins_for_gpio_bits[16]	auto[1]	auto[1]	5316862	1			T41	70		T42	163		T43	182
bins_for_gpio_bits[17]	auto[0]	auto[0]	7769161	1			T41	112		T42	439		T43	464
bins_for_gpio_bits[17]	auto[0]	auto[1]	236371	1			T42	47		T43	32		T44	2231
bins_for_gpio_bits[17]	auto[1]	auto[0]	236638	1			T42	47		T43	32		T44	2237
bins_for_gpio_bits[17]	auto[1]	auto[1]	5308272	1			T41	58		T42	147		T43	168
bins_for_gpio_bits[18]	auto[0]	auto[0]	7756978	1			T41	109		T42	476		T43	410
bins_for_gpio_bits[18]	auto[0]	auto[1]	236955	1			T42	37		T43	37		T44	2296
bins_for_gpio_bits[18]	auto[1]	auto[0]	237205	1			T42	37		T43	37		T44	2306
bins_for_gpio_bits[18]	auto[1]	auto[1]	5319304	1			T41	61		T42	130		T43	212
bins_for_gpio_bits[19]	auto[0]	auto[0]	7759349	1			T41	105		T42	454		T43	459
bins_for_gpio_bits[19]	auto[0]	auto[1]	236777	1			T42	40		T43	34		T44	2189
bins_for_gpio_bits[19]	auto[1]	auto[0]	236995	1			T42	40		T43	34		T44	2195
bins_for_gpio_bits[19]	auto[1]	auto[1]	5317321	1			T41	65		T42	146		T43	169
bins_for_gpio_bits[20]	auto[0]	auto[0]	7759084	1			T41	105		T42	452		T43	476
bins_for_gpio_bits[20]	auto[0]	auto[1]	236698	1			T42	42		T43	30		T44	2266
bins_for_gpio_bits[20]	auto[1]	auto[0]	236934	1			T42	43		T43	30		T44	2269
bins_for_gpio_bits[20]	auto[1]	auto[1]	5317726	1			T41	65		T42	143		T43	160
bins_for_gpio_bits[21]	auto[0]	auto[0]	7776476	1			T41	96		T42	446		T43	443
bins_for_gpio_bits[21]	auto[0]	auto[1]	236666	1			T42	43		T43	31		T44	2215
bins_for_gpio_bits[21]	auto[1]	auto[0]	236917	1			T41	1		T42	43		T43	31
bins_for_gpio_bits[21]	auto[1]	auto[1]	5300383	1			T41	73		T42	148		T43	191
bins_for_gpio_bits[22]	auto[0]	auto[0]	7768596	1			T41	86		T42	475		T43	428
bins_for_gpio_bits[22]	auto[0]	auto[1]	236538	1			T41	2		T42	40		T43	37
bins_for_gpio_bits[22]	auto[1]	auto[0]	236815	1			T41	2		T42	41		T43	38
bins_for_gpio_bits[22]	auto[1]	auto[1]	5308493	1			T41	80		T42	124		T43	193
bins_for_gpio_bits[23]	auto[0]	auto[0]	7767437	1			T41	98		T42	479		T43	417
bins_for_gpio_bits[23]	auto[0]	auto[1]	236506	1			T42	43		T43	43		T44	2250
bins_for_gpio_bits[23]	auto[1]	auto[0]	236761	1			T41	1		T42	44		T43	43
bins_for_gpio_bits[23]	auto[1]	auto[1]	5309738	1			T41	71		T42	114		T43	193
bins_for_gpio_bits[24]	auto[0]	auto[0]	7765559	1			T41	108		T42	487		T43	436
bins_for_gpio_bits[24]	auto[0]	auto[1]	236672	1			T42	38		T43	35		T44	2252
bins_for_gpio_bits[24]	auto[1]	auto[0]	236880	1			T42	38		T43	36		T44	2259
bins_for_gpio_bits[24]	auto[1]	auto[1]	5311331	1			T41	62		T42	117		T43	189
bins_for_gpio_bits[25]	auto[0]	auto[0]	7757882	1			T41	119		T42	456		T43	433
bins_for_gpio_bits[25]	auto[0]	auto[1]	236112	1			T42	42		T43	35		T44	2253
bins_for_gpio_bits[25]	auto[1]	auto[0]	236331	1			T42	42		T43	36		T44	2257
bins_for_gpio_bits[25]	auto[1]	auto[1]	5320117	1			T41	51		T42	140		T43	192
bins_for_gpio_bits[26]	auto[0]	auto[0]	7764159	1			T41	96		T42	483		T43	467
bins_for_gpio_bits[26]	auto[0]	auto[1]	236608	1			T42	36		T43	34		T44	2245
bins_for_gpio_bits[26]	auto[1]	auto[0]	236860	1			T41	1		T42	37		T43	34
bins_for_gpio_bits[26]	auto[1]	auto[1]	5312815	1			T41	73		T42	124		T43	161
bins_for_gpio_bits[27]	auto[0]	auto[0]	7768048	1			T41	136		T42	438		T43	461
bins_for_gpio_bits[27]	auto[0]	auto[1]	236756	1			T42	46		T43	36		T44	2287
bins_for_gpio_bits[27]	auto[1]	auto[0]	236997	1			T42	46		T43	36		T44	2291
bins_for_gpio_bits[27]	auto[1]	auto[1]	5308641	1			T41	34		T42	150		T43	163
bins_for_gpio_bits[28]	auto[0]	auto[0]	7766884	1			T41	143		T42	465		T43	437
bins_for_gpio_bits[28]	auto[0]	auto[1]	237239	1			T42	40		T43	40		T44	2232
bins_for_gpio_bits[28]	auto[1]	auto[0]	237449	1			T41	1		T42	40		T43	41
bins_for_gpio_bits[28]	auto[1]	auto[1]	5308870	1			T41	26		T42	135		T43	178
bins_for_gpio_bits[29]	auto[0]	auto[0]	7767567	1			T41	74		T42	449		T43	490
bins_for_gpio_bits[29]	auto[0]	auto[1]	236452	1			T41	1		T42	42		T43	37
bins_for_gpio_bits[29]	auto[1]	auto[0]	236677	1			T41	2		T42	42		T43	38
bins_for_gpio_bits[29]	auto[1]	auto[1]	5309746	1			T41	93		T42	147		T43	131
bins_for_gpio_bits[30]	auto[0]	auto[0]	7763983	1			T41	79		T42	463		T43	444
bins_for_gpio_bits[30]	auto[0]	auto[1]	236564	1			T42	43		T43	39		T44	2246
bins_for_gpio_bits[30]	auto[1]	auto[0]	236810	1			T42	43		T43	39		T44	2251
bins_for_gpio_bits[30]	auto[1]	auto[1]	5313085	1			T41	91		T42	131		T43	174
bins_for_gpio_bits[31]	auto[0]	auto[0]	7770532	1			T41	63		T42	465		T43	447
bins_for_gpio_bits[31]	auto[0]	auto[1]	237014	1			T42	41		T43	34		T44	2185
bins_for_gpio_bits[31]	auto[1]	auto[0]	237273	1			T41	1		T42	41		T43	34
bins_for_gpio_bits[31]	auto[1]	auto[1]	5305623	1			T41	106		T42	133		T43	181