Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7983099 |
1 |
|
|
T41 |
85 |
|
T42 |
354 |
|
T43 |
414 |
| auto[1] |
5819151 |
1 |
|
|
T41 |
6 |
|
T44 |
59060 |
|
T46 |
524 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13059825 |
1 |
|
|
T41 |
90 |
|
T42 |
354 |
|
T43 |
414 |
| auto[1] |
742425 |
1 |
|
|
T41 |
1 |
|
T44 |
7533 |
|
T46 |
31 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8008271 |
1 |
|
|
T41 |
69 |
|
T42 |
354 |
|
T43 |
414 |
| auto[1] |
5793979 |
1 |
|
|
T41 |
22 |
|
T44 |
58014 |
|
T46 |
579 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2515292 |
1 |
|
|
T41 |
16 |
|
T44 |
25743 |
|
T46 |
248 |
| auto[1] |
auto[0] |
auto[1] |
367982 |
1 |
|
|
T41 |
1 |
|
T44 |
3789 |
|
T46 |
14 |
| auto[1] |
auto[1] |
auto[0] |
2536262 |
1 |
|
|
T41 |
5 |
|
T44 |
24738 |
|
T46 |
300 |
| auto[1] |
auto[1] |
auto[1] |
374443 |
1 |
|
|
T44 |
3744 |
|
T46 |
17 |
|
T47 |
94 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7990680 |
1 |
|
|
T41 |
65 |
|
T42 |
354 |
|
T43 |
414 |
| auto[1] |
5811570 |
1 |
|
|
T41 |
26 |
|
T44 |
57379 |
|
T46 |
511 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13061103 |
1 |
|
|
T41 |
91 |
|
T42 |
354 |
|
T43 |
414 |
| auto[1] |
741147 |
1 |
|
|
T44 |
7762 |
|
T46 |
24 |
|
T47 |
187 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8007656 |
1 |
|
|
T41 |
88 |
|
T42 |
354 |
|
T43 |
414 |
| auto[1] |
5794594 |
1 |
|
|
T41 |
3 |
|
T44 |
59049 |
|
T46 |
632 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2525533 |
1 |
|
|
T44 |
25852 |
|
T46 |
315 |
|
T47 |
343 |
| auto[1] |
auto[0] |
auto[1] |
370157 |
1 |
|
|
T44 |
3953 |
|
T46 |
10 |
|
T47 |
80 |
| auto[1] |
auto[1] |
auto[0] |
2527914 |
1 |
|
|
T41 |
3 |
|
T44 |
25435 |
|
T46 |
293 |
| auto[1] |
auto[1] |
auto[1] |
370990 |
1 |
|
|
T44 |
3809 |
|
T46 |
14 |
|
T47 |
107 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7997838 |
1 |
|
|
T41 |
75 |
|
T42 |
354 |
|
T43 |
414 |
| auto[1] |
5804412 |
1 |
|
|
T41 |
16 |
|
T44 |
58875 |
|
T46 |
644 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13060346 |
1 |
|
|
T41 |
91 |
|
T42 |
354 |
|
T43 |
414 |
| auto[1] |
741904 |
1 |
|
|
T44 |
7606 |
|
T46 |
25 |
|
T47 |
233 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8015782 |
1 |
|
|
T41 |
80 |
|
T42 |
354 |
|
T43 |
414 |
| auto[1] |
5786468 |
1 |
|
|
T41 |
11 |
|
T44 |
58587 |
|
T46 |
581 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2523998 |
1 |
|
|
T41 |
11 |
|
T44 |
25468 |
|
T46 |
247 |
| auto[1] |
auto[0] |
auto[1] |
369999 |
1 |
|
|
T44 |
3784 |
|
T46 |
7 |
|
T47 |
121 |
| auto[1] |
auto[1] |
auto[0] |
2520566 |
1 |
|
|
T44 |
25513 |
|
T46 |
309 |
|
T47 |
483 |
| auto[1] |
auto[1] |
auto[1] |
371905 |
1 |
|
|
T44 |
3822 |
|
T46 |
18 |
|
T47 |
112 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7993154 |
1 |
|
|
T41 |
58 |
|
T42 |
354 |
|
T43 |
414 |
| auto[1] |
5809096 |
1 |
|
|
T41 |
33 |
|
T44 |
59469 |
|
T46 |
441 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13057789 |
1 |
|
|
T41 |
91 |
|
T42 |
354 |
|
T43 |
414 |
| auto[1] |
744461 |
1 |
|
|
T44 |
7785 |
|
T46 |
27 |
|
T47 |
237 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7996123 |
1 |
|
|
T41 |
72 |
|
T42 |
354 |
|
T43 |
414 |
| auto[1] |
5806127 |
1 |
|
|
T41 |
19 |
|
T44 |
58816 |
|
T46 |
617 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2524247 |
1 |
|
|
T41 |
7 |
|
T44 |
25192 |
|
T46 |
381 |
| auto[1] |
auto[0] |
auto[1] |
371554 |
1 |
|
|
T44 |
3818 |
|
T46 |
17 |
|
T47 |
127 |
| auto[1] |
auto[1] |
auto[0] |
2537419 |
1 |
|
|
T41 |
12 |
|
T44 |
25839 |
|
T46 |
209 |
| auto[1] |
auto[1] |
auto[1] |
372907 |
1 |
|
|
T44 |
3967 |
|
T46 |
10 |
|
T47 |
110 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7999271 |
1 |
|
|
T41 |
84 |
|
T42 |
354 |
|
T43 |
414 |
| auto[1] |
5802979 |
1 |
|
|
T41 |
7 |
|
T44 |
59606 |
|
T46 |
520 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13056186 |
1 |
|
|
T41 |
91 |
|
T42 |
354 |
|
T43 |
414 |
| auto[1] |
746064 |
1 |
|
|
T44 |
7751 |
|
T46 |
17 |
|
T47 |
199 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7982139 |
1 |
|
|
T41 |
69 |
|
T42 |
354 |
|
T43 |
414 |
| auto[1] |
5820111 |
1 |
|
|
T41 |
22 |
|
T44 |
58745 |
|
T46 |
439 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2523915 |
1 |
|
|
T41 |
22 |
|
T44 |
25351 |
|
T46 |
230 |
| auto[1] |
auto[0] |
auto[1] |
370491 |
1 |
|
|
T44 |
3870 |
|
T46 |
7 |
|
T47 |
117 |
| auto[1] |
auto[1] |
auto[0] |
2550132 |
1 |
|
|
T44 |
25643 |
|
T46 |
192 |
|
T47 |
323 |
| auto[1] |
auto[1] |
auto[1] |
375573 |
1 |
|
|
T44 |
3881 |
|
T46 |
10 |
|
T47 |
82 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8019205 |
1 |
|
|
T41 |
78 |
|
T42 |
354 |
|
T43 |
414 |
| auto[1] |
5783045 |
1 |
|
|
T41 |
13 |
|
T44 |
59454 |
|
T46 |
554 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13059047 |
1 |
|
|
T41 |
91 |
|
T42 |
354 |
|
T43 |
414 |
| auto[1] |
743203 |
1 |
|
|
T44 |
7835 |
|
T46 |
30 |
|
T47 |
170 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7996303 |
1 |
|
|
T41 |
80 |
|
T42 |
354 |
|
T43 |
414 |
| auto[1] |
5805947 |
1 |
|
|
T41 |
11 |
|
T44 |
59490 |
|
T46 |
625 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2538951 |
1 |
|
|
T41 |
11 |
|
T44 |
26123 |
|
T46 |
294 |
| auto[1] |
auto[0] |
auto[1] |
372879 |
1 |
|
|
T44 |
3861 |
|
T46 |
17 |
|
T47 |
73 |
| auto[1] |
auto[1] |
auto[0] |
2523793 |
1 |
|
|
T44 |
25532 |
|
T46 |
301 |
|
T47 |
385 |
| auto[1] |
auto[1] |
auto[1] |
370324 |
1 |
|
|
T44 |
3974 |
|
T46 |
13 |
|
T47 |
97 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8005512 |
1 |
|
|
T41 |
65 |
|
T42 |
354 |
|
T43 |
414 |
| auto[1] |
5796738 |
1 |
|
|
T41 |
26 |
|
T44 |
57939 |
|
T46 |
548 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13059673 |
1 |
|
|
T41 |
91 |
|
T42 |
354 |
|
T43 |
414 |
| auto[1] |
742577 |
1 |
|
|
T44 |
7882 |
|
T46 |
30 |
|
T47 |
170 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8012069 |
1 |
|
|
T41 |
85 |
|
T42 |
354 |
|
T43 |
414 |
| auto[1] |
5790181 |
1 |
|
|
T41 |
6 |
|
T44 |
59196 |
|
T46 |
648 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2544935 |
1 |
|
|
T41 |
3 |
|
T44 |
26159 |
|
T46 |
284 |
| auto[1] |
auto[0] |
auto[1] |
375219 |
1 |
|
|
T44 |
3983 |
|
T46 |
19 |
|
T47 |
95 |
| auto[1] |
auto[1] |
auto[0] |
2502669 |
1 |
|
|
T41 |
3 |
|
T44 |
25155 |
|
T46 |
334 |
| auto[1] |
auto[1] |
auto[1] |
367358 |
1 |
|
|
T44 |
3899 |
|
T46 |
11 |
|
T47 |
75 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7983406 |
1 |
|
|
T41 |
52 |
|
T42 |
354 |
|
T43 |
414 |
| auto[1] |
5818844 |
1 |
|
|
T41 |
39 |
|
T44 |
59279 |
|
T46 |
547 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13058708 |
1 |
|
|
T41 |
91 |
|
T42 |
354 |
|
T43 |
414 |
| auto[1] |
743542 |
1 |
|
|
T44 |
7810 |
|
T46 |
29 |
|
T47 |
191 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7996479 |
1 |
|
|
T41 |
80 |
|
T42 |
354 |
|
T43 |
414 |
| auto[1] |
5805771 |
1 |
|
|
T41 |
11 |
|
T44 |
59528 |
|
T46 |
713 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2532145 |
1 |
|
|
T41 |
6 |
|
T44 |
26314 |
|
T46 |
368 |
| auto[1] |
auto[0] |
auto[1] |
371133 |
1 |
|
|
T44 |
4005 |
|
T46 |
18 |
|
T47 |
102 |
| auto[1] |
auto[1] |
auto[0] |
2530084 |
1 |
|
|
T41 |
5 |
|
T44 |
25404 |
|
T46 |
316 |
| auto[1] |
auto[1] |
auto[1] |
372409 |
1 |
|
|
T44 |
3805 |
|
T46 |
11 |
|
T47 |
89 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7994705 |
1 |
|
|
T41 |
68 |
|
T42 |
354 |
|
T43 |
414 |
| auto[1] |
5807545 |
1 |
|
|
T41 |
23 |
|
T44 |
58700 |
|
T46 |
497 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13058020 |
1 |
|
|
T41 |
90 |
|
T42 |
354 |
|
T43 |
414 |
| auto[1] |
744230 |
1 |
|
|
T41 |
1 |
|
T44 |
7761 |
|
T46 |
23 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8006352 |
1 |
|
|
T41 |
67 |
|
T42 |
354 |
|
T43 |
414 |
| auto[1] |
5795898 |
1 |
|
|
T41 |
24 |
|
T44 |
58159 |
|
T46 |
645 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2518026 |
1 |
|
|
T41 |
18 |
|
T44 |
25445 |
|
T46 |
331 |
| auto[1] |
auto[0] |
auto[1] |
369689 |
1 |
|
|
T41 |
1 |
|
T44 |
3927 |
|
T46 |
13 |
| auto[1] |
auto[1] |
auto[0] |
2533642 |
1 |
|
|
T41 |
5 |
|
T44 |
24953 |
|
T46 |
291 |
| auto[1] |
auto[1] |
auto[1] |
374541 |
1 |
|
|
T44 |
3834 |
|
T46 |
10 |
|
T47 |
94 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7980750 |
1 |
|
|
T41 |
91 |
|
T42 |
354 |
|
T43 |
414 |
| auto[1] |
5821500 |
1 |
|
|
T44 |
59707 |
|
T46 |
460 |
|
T47 |
1068 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13061850 |
1 |
|
|
T41 |
91 |
|
T42 |
354 |
|
T43 |
414 |
| auto[1] |
740400 |
1 |
|
|
T44 |
7898 |
|
T46 |
17 |
|
T47 |
206 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8013511 |
1 |
|
|
T41 |
80 |
|
T42 |
354 |
|
T43 |
414 |
| auto[1] |
5788739 |
1 |
|
|
T41 |
11 |
|
T44 |
59545 |
|
T46 |
449 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2531875 |
1 |
|
|
T41 |
11 |
|
T44 |
26141 |
|
T46 |
270 |
| auto[1] |
auto[0] |
auto[1] |
370543 |
1 |
|
|
T44 |
3974 |
|
T46 |
7 |
|
T47 |
83 |
| auto[1] |
auto[1] |
auto[0] |
2516464 |
1 |
|
|
T44 |
25506 |
|
T46 |
162 |
|
T47 |
526 |
| auto[1] |
auto[1] |
auto[1] |
369857 |
1 |
|
|
T44 |
3924 |
|
T46 |
10 |
|
T47 |
123 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8000905 |
1 |
|
|
T41 |
69 |
|
T42 |
354 |
|
T43 |
414 |
| auto[1] |
5801345 |
1 |
|
|
T41 |
22 |
|
T44 |
58483 |
|
T46 |
541 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13061050 |
1 |
|
|
T41 |
91 |
|
T42 |
354 |
|
T43 |
414 |
| auto[1] |
741200 |
1 |
|
|
T44 |
7682 |
|
T46 |
23 |
|
T47 |
148 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8010943 |
1 |
|
|
T41 |
69 |
|
T42 |
354 |
|
T43 |
414 |
| auto[1] |
5791307 |
1 |
|
|
T41 |
22 |
|
T44 |
58268 |
|
T46 |
677 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2510828 |
1 |
|
|
T41 |
17 |
|
T44 |
25691 |
|
T46 |
303 |
| auto[1] |
auto[0] |
auto[1] |
368599 |
1 |
|
|
T44 |
3830 |
|
T46 |
10 |
|
T47 |
54 |
| auto[1] |
auto[1] |
auto[0] |
2539279 |
1 |
|
|
T41 |
5 |
|
T44 |
24895 |
|
T46 |
351 |
| auto[1] |
auto[1] |
auto[1] |
372601 |
1 |
|
|
T44 |
3852 |
|
T46 |
13 |
|
T47 |
94 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8030705 |
1 |
|
|
T41 |
91 |
|
T42 |
354 |
|
T43 |
414 |
| auto[1] |
5771545 |
1 |
|
|
T44 |
57751 |
|
T46 |
594 |
|
T47 |
560 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13060586 |
1 |
|
|
T41 |
90 |
|
T42 |
354 |
|
T43 |
414 |
| auto[1] |
741664 |
1 |
|
|
T41 |
1 |
|
T44 |
7563 |
|
T46 |
27 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8008471 |
1 |
|
|
T41 |
67 |
|
T42 |
354 |
|
T43 |
414 |
| auto[1] |
5793779 |
1 |
|
|
T41 |
24 |
|
T44 |
58414 |
|
T46 |
588 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2540709 |
1 |
|
|
T41 |
23 |
|
T44 |
26551 |
|
T46 |
246 |
| auto[1] |
auto[0] |
auto[1] |
373584 |
1 |
|
|
T41 |
1 |
|
T44 |
4007 |
|
T46 |
14 |
| auto[1] |
auto[1] |
auto[0] |
2511406 |
1 |
|
|
T44 |
24300 |
|
T46 |
315 |
|
T47 |
215 |
| auto[1] |
auto[1] |
auto[1] |
368080 |
1 |
|
|
T44 |
3556 |
|
T46 |
13 |
|
T47 |
50 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8021753 |
1 |
|
|
T41 |
59 |
|
T42 |
354 |
|
T43 |
414 |
| auto[1] |
5780497 |
1 |
|
|
T41 |
32 |
|
T44 |
59868 |
|
T46 |
590 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13057797 |
1 |
|
|
T41 |
91 |
|
T42 |
354 |
|
T43 |
414 |
| auto[1] |
744453 |
1 |
|
|
T44 |
7420 |
|
T46 |
25 |
|
T47 |
222 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7997367 |
1 |
|
|
T41 |
72 |
|
T42 |
354 |
|
T43 |
414 |
| auto[1] |
5804883 |
1 |
|
|
T41 |
19 |
|
T44 |
56911 |
|
T46 |
690 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2532291 |
1 |
|
|
T41 |
4 |
|
T44 |
24384 |
|
T46 |
263 |
| auto[1] |
auto[0] |
auto[1] |
372468 |
1 |
|
|
T44 |
3641 |
|
T46 |
9 |
|
T47 |
124 |
| auto[1] |
auto[1] |
auto[0] |
2528139 |
1 |
|
|
T41 |
15 |
|
T44 |
25107 |
|
T46 |
402 |
| auto[1] |
auto[1] |
auto[1] |
371985 |
1 |
|
|
T44 |
3779 |
|
T46 |
16 |
|
T47 |
98 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7995597 |
1 |
|
|
T41 |
71 |
|
T42 |
354 |
|
T43 |
414 |
| auto[1] |
5806653 |
1 |
|
|
T41 |
20 |
|
T44 |
58652 |
|
T46 |
370 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13063826 |
1 |
|
|
T41 |
91 |
|
T42 |
354 |
|
T43 |
414 |
| auto[1] |
738424 |
1 |
|
|
T44 |
7605 |
|
T46 |
19 |
|
T47 |
177 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8030142 |
1 |
|
|
T41 |
69 |
|
T42 |
354 |
|
T43 |
414 |
| auto[1] |
5772108 |
1 |
|
|
T41 |
22 |
|
T44 |
57270 |
|
T46 |
437 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2518923 |
1 |
|
|
T41 |
12 |
|
T44 |
25230 |
|
T46 |
285 |
| auto[1] |
auto[0] |
auto[1] |
369489 |
1 |
|
|
T44 |
3878 |
|
T46 |
15 |
|
T47 |
107 |
| auto[1] |
auto[1] |
auto[0] |
2514761 |
1 |
|
|
T41 |
10 |
|
T44 |
24435 |
|
T46 |
133 |
| auto[1] |
auto[1] |
auto[1] |
368935 |
1 |
|
|
T44 |
3727 |
|
T46 |
4 |
|
T47 |
70 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7989968 |
1 |
|
|
T41 |
78 |
|
T42 |
354 |
|
T43 |
414 |
| auto[1] |
5812282 |
1 |
|
|
T41 |
13 |
|
T44 |
59828 |
|
T46 |
550 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13062585 |
1 |
|
|
T41 |
90 |
|
T42 |
354 |
|
T43 |
414 |
| auto[1] |
739665 |
1 |
|
|
T41 |
1 |
|
T44 |
7439 |
|
T46 |
31 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8025212 |
1 |
|
|
T41 |
75 |
|
T42 |
354 |
|
T43 |
414 |
| auto[1] |
5777038 |
1 |
|
|
T41 |
16 |
|
T44 |
56668 |
|
T46 |
674 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2532443 |
1 |
|
|
T41 |
15 |
|
T44 |
25073 |
|
T46 |
335 |
| auto[1] |
auto[0] |
auto[1] |
371595 |
1 |
|
|
T41 |
1 |
|
T44 |
3812 |
|
T46 |
14 |
| auto[1] |
auto[1] |
auto[0] |
2504930 |
1 |
|
|
T44 |
24156 |
|
T46 |
308 |
|
T47 |
509 |
| auto[1] |
auto[1] |
auto[1] |
368070 |
1 |
|
|
T44 |
3627 |
|
T46 |
17 |
|
T47 |
120 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8004577 |
1 |
|
|
T41 |
68 |
|
T42 |
354 |
|
T43 |
414 |
| auto[1] |
5797673 |
1 |
|
|
T41 |
23 |
|
T44 |
60184 |
|
T46 |
521 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13062568 |
1 |
|
|
T41 |
91 |
|
T42 |
354 |
|
T43 |
414 |
| auto[1] |
739682 |
1 |
|
|
T44 |
8077 |
|
T46 |
20 |
|
T47 |
168 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8016934 |
1 |
|
|
T41 |
80 |
|
T42 |
354 |
|
T43 |
414 |
| auto[1] |
5785316 |
1 |
|
|
T41 |
11 |
|
T44 |
60077 |
|
T46 |
518 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2526969 |
1 |
|
|
T41 |
11 |
|
T44 |
25223 |
|
T46 |
218 |
| auto[1] |
auto[0] |
auto[1] |
369670 |
1 |
|
|
T44 |
3913 |
|
T46 |
9 |
|
T47 |
120 |
| auto[1] |
auto[1] |
auto[0] |
2518665 |
1 |
|
|
T44 |
26777 |
|
T46 |
280 |
|
T47 |
214 |
| auto[1] |
auto[1] |
auto[1] |
370012 |
1 |
|
|
T44 |
4164 |
|
T46 |
11 |
|
T47 |
48 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7993140 |
1 |
|
|
T41 |
85 |
|
T42 |
354 |
|
T43 |
414 |
| auto[1] |
5809110 |
1 |
|
|
T41 |
6 |
|
T44 |
60093 |
|
T46 |
598 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13059926 |
1 |
|
|
T41 |
91 |
|
T42 |
354 |
|
T43 |
414 |
| auto[1] |
742324 |
1 |
|
|
T44 |
7575 |
|
T46 |
25 |
|
T47 |
142 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8001103 |
1 |
|
|
T41 |
80 |
|
T42 |
354 |
|
T43 |
414 |
| auto[1] |
5801147 |
1 |
|
|
T41 |
11 |
|
T44 |
57771 |
|
T46 |
628 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2519784 |
1 |
|
|
T41 |
11 |
|
T44 |
24252 |
|
T46 |
266 |
| auto[1] |
auto[0] |
auto[1] |
369146 |
1 |
|
|
T44 |
3666 |
|
T46 |
10 |
|
T47 |
64 |
| auto[1] |
auto[1] |
auto[0] |
2539039 |
1 |
|
|
T44 |
25944 |
|
T46 |
337 |
|
T47 |
321 |
| auto[1] |
auto[1] |
auto[1] |
373178 |
1 |
|
|
T44 |
3909 |
|
T46 |
15 |
|
T47 |
78 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8037203 |
1 |
|
|
T41 |
78 |
|
T42 |
354 |
|
T43 |
414 |
| auto[1] |
5765047 |
1 |
|
|
T41 |
13 |
|
T44 |
58858 |
|
T46 |
455 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13061104 |
1 |
|
|
T41 |
91 |
|
T42 |
354 |
|
T43 |
414 |
| auto[1] |
741146 |
1 |
|
|
T44 |
7811 |
|
T46 |
19 |
|
T47 |
241 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8018449 |
1 |
|
|
T41 |
71 |
|
T42 |
354 |
|
T43 |
414 |
| auto[1] |
5783801 |
1 |
|
|
T41 |
20 |
|
T44 |
59936 |
|
T46 |
448 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2536836 |
1 |
|
|
T41 |
20 |
|
T44 |
25671 |
|
T46 |
251 |
| auto[1] |
auto[0] |
auto[1] |
373448 |
1 |
|
|
T44 |
3827 |
|
T46 |
11 |
|
T47 |
93 |
| auto[1] |
auto[1] |
auto[0] |
2505819 |
1 |
|
|
T44 |
26454 |
|
T46 |
178 |
|
T47 |
574 |
| auto[1] |
auto[1] |
auto[1] |
367698 |
1 |
|
|
T44 |
3984 |
|
T46 |
8 |
|
T47 |
148 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8009147 |
1 |
|
|
T41 |
52 |
|
T42 |
354 |
|
T43 |
414 |
| auto[1] |
5793103 |
1 |
|
|
T41 |
39 |
|
T44 |
59493 |
|
T46 |
526 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13058840 |
1 |
|
|
T41 |
91 |
|
T42 |
354 |
|
T43 |
414 |
| auto[1] |
743410 |
1 |
|
|
T44 |
7599 |
|
T46 |
27 |
|
T47 |
165 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7996899 |
1 |
|
|
T41 |
64 |
|
T42 |
354 |
|
T43 |
414 |
| auto[1] |
5805351 |
1 |
|
|
T41 |
27 |
|
T44 |
58335 |
|
T46 |
599 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2547384 |
1 |
|
|
T41 |
10 |
|
T44 |
25674 |
|
T46 |
317 |
| auto[1] |
auto[0] |
auto[1] |
374707 |
1 |
|
|
T44 |
3855 |
|
T46 |
16 |
|
T47 |
90 |
| auto[1] |
auto[1] |
auto[0] |
2514557 |
1 |
|
|
T41 |
17 |
|
T44 |
25062 |
|
T46 |
255 |
| auto[1] |
auto[1] |
auto[1] |
368703 |
1 |
|
|
T44 |
3744 |
|
T46 |
11 |
|
T47 |
75 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8030679 |
1 |
|
|
T41 |
68 |
|
T42 |
354 |
|
T43 |
414 |
| auto[1] |
5771571 |
1 |
|
|
T41 |
23 |
|
T44 |
58409 |
|
T46 |
528 |