Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8001792 |
1 |
|
|
T41 |
75 |
|
T42 |
354 |
|
T43 |
414 |
| auto[1] |
5800458 |
1 |
|
|
T41 |
16 |
|
T44 |
57467 |
|
T46 |
422 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13058529 |
1 |
|
|
T41 |
91 |
|
T42 |
354 |
|
T43 |
414 |
| auto[1] |
743721 |
1 |
|
|
T44 |
7687 |
|
T46 |
25 |
|
T47 |
150 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7999119 |
1 |
|
|
T41 |
78 |
|
T42 |
354 |
|
T43 |
414 |
| auto[1] |
5803131 |
1 |
|
|
T41 |
13 |
|
T44 |
57857 |
|
T46 |
601 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2540816 |
1 |
|
|
T41 |
8 |
|
T44 |
25601 |
|
T46 |
355 |
| auto[1] |
auto[0] |
auto[1] |
374112 |
1 |
|
|
T44 |
3916 |
|
T46 |
17 |
|
T47 |
96 |
| auto[1] |
auto[1] |
auto[0] |
2518594 |
1 |
|
|
T41 |
5 |
|
T44 |
24569 |
|
T46 |
221 |
| auto[1] |
auto[1] |
auto[1] |
369609 |
1 |
|
|
T44 |
3771 |
|
T46 |
8 |
|
T47 |
54 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |