Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8002511 |
1 |
|
|
T41 |
85 |
|
T42 |
354 |
|
T43 |
414 |
| auto[1] |
5799739 |
1 |
|
|
T41 |
6 |
|
T44 |
58580 |
|
T46 |
605 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13054093 |
1 |
|
|
T41 |
91 |
|
T42 |
354 |
|
T43 |
414 |
| auto[1] |
748157 |
1 |
|
|
T44 |
7723 |
|
T46 |
14 |
|
T47 |
195 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7980618 |
1 |
|
|
T41 |
83 |
|
T42 |
354 |
|
T43 |
414 |
| auto[1] |
5821632 |
1 |
|
|
T41 |
8 |
|
T44 |
58345 |
|
T46 |
525 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2534419 |
1 |
|
|
T41 |
3 |
|
T44 |
25332 |
|
T46 |
266 |
| auto[1] |
auto[0] |
auto[1] |
372981 |
1 |
|
|
T44 |
3726 |
|
T46 |
7 |
|
T47 |
110 |
| auto[1] |
auto[1] |
auto[0] |
2539056 |
1 |
|
|
T41 |
5 |
|
T44 |
25290 |
|
T46 |
245 |
| auto[1] |
auto[1] |
auto[1] |
375176 |
1 |
|
|
T44 |
3997 |
|
T46 |
7 |
|
T47 |
85 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |