Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8023728 |
1 |
|
|
T41 |
58 |
|
T42 |
354 |
|
T43 |
414 |
| auto[1] |
5778522 |
1 |
|
|
T41 |
33 |
|
T44 |
59058 |
|
T46 |
467 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13055834 |
1 |
|
|
T41 |
91 |
|
T42 |
354 |
|
T43 |
414 |
| auto[1] |
746416 |
1 |
|
|
T44 |
7630 |
|
T46 |
19 |
|
T47 |
140 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7984360 |
1 |
|
|
T41 |
69 |
|
T42 |
354 |
|
T43 |
414 |
| auto[1] |
5817890 |
1 |
|
|
T41 |
22 |
|
T44 |
58276 |
|
T46 |
495 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2552937 |
1 |
|
|
T41 |
10 |
|
T44 |
25713 |
|
T46 |
291 |
| auto[1] |
auto[0] |
auto[1] |
376696 |
1 |
|
|
T44 |
3860 |
|
T46 |
11 |
|
T47 |
69 |
| auto[1] |
auto[1] |
auto[0] |
2518537 |
1 |
|
|
T41 |
12 |
|
T44 |
24933 |
|
T46 |
185 |
| auto[1] |
auto[1] |
auto[1] |
369720 |
1 |
|
|
T44 |
3770 |
|
T46 |
8 |
|
T47 |
71 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |