Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7994749 |
1 |
|
|
T41 |
74 |
|
T42 |
354 |
|
T43 |
414 |
| auto[1] |
5807501 |
1 |
|
|
T41 |
17 |
|
T44 |
58808 |
|
T46 |
621 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13061252 |
1 |
|
|
T41 |
91 |
|
T42 |
354 |
|
T43 |
414 |
| auto[1] |
740998 |
1 |
|
|
T44 |
7752 |
|
T46 |
19 |
|
T47 |
233 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8016516 |
1 |
|
|
T41 |
80 |
|
T42 |
354 |
|
T43 |
414 |
| auto[1] |
5785734 |
1 |
|
|
T41 |
11 |
|
T44 |
59388 |
|
T46 |
560 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2523890 |
1 |
|
|
T41 |
8 |
|
T44 |
25878 |
|
T46 |
257 |
| auto[1] |
auto[0] |
auto[1] |
370080 |
1 |
|
|
T44 |
3839 |
|
T46 |
15 |
|
T47 |
140 |
| auto[1] |
auto[1] |
auto[0] |
2520846 |
1 |
|
|
T41 |
3 |
|
T44 |
25758 |
|
T46 |
284 |
| auto[1] |
auto[1] |
auto[1] |
370918 |
1 |
|
|
T44 |
3913 |
|
T46 |
4 |
|
T47 |
93 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |