Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8002464 |
1 |
|
|
T41 |
52 |
|
T42 |
354 |
|
T43 |
414 |
| auto[1] |
5799786 |
1 |
|
|
T41 |
39 |
|
T44 |
60533 |
|
T46 |
519 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13058351 |
1 |
|
|
T41 |
90 |
|
T42 |
354 |
|
T43 |
414 |
| auto[1] |
743899 |
1 |
|
|
T41 |
1 |
|
T44 |
7663 |
|
T46 |
16 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7997542 |
1 |
|
|
T41 |
69 |
|
T42 |
354 |
|
T43 |
414 |
| auto[1] |
5804708 |
1 |
|
|
T41 |
22 |
|
T44 |
58444 |
|
T46 |
470 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2544104 |
1 |
|
|
T41 |
7 |
|
T44 |
25158 |
|
T46 |
235 |
| auto[1] |
auto[0] |
auto[1] |
374677 |
1 |
|
|
T44 |
3910 |
|
T46 |
9 |
|
T47 |
65 |
| auto[1] |
auto[1] |
auto[0] |
2516705 |
1 |
|
|
T41 |
14 |
|
T44 |
25623 |
|
T46 |
219 |
| auto[1] |
auto[1] |
auto[1] |
369222 |
1 |
|
|
T41 |
1 |
|
T44 |
3753 |
|
T46 |
7 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |