Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13056124 |
1 |
|
|
T41 |
91 |
|
T42 |
354 |
|
T43 |
414 |
| auto[1] |
746126 |
1 |
|
|
T44 |
7996 |
|
T46 |
22 |
|
T47 |
199 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7992594 |
1 |
|
|
T41 |
69 |
|
T42 |
354 |
|
T43 |
414 |
| auto[1] |
5809656 |
1 |
|
|
T41 |
22 |
|
T44 |
59462 |
|
T46 |
543 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2545836 |
1 |
|
|
T41 |
15 |
|
T44 |
26156 |
|
T46 |
284 |
| auto[1] |
auto[0] |
auto[1] |
375776 |
1 |
|
|
T44 |
4064 |
|
T46 |
16 |
|
T47 |
94 |
| auto[1] |
auto[1] |
auto[0] |
2517694 |
1 |
|
|
T41 |
7 |
|
T44 |
25310 |
|
T46 |
237 |
| auto[1] |
auto[1] |
auto[1] |
370350 |
1 |
|
|
T44 |
3932 |
|
T46 |
6 |
|
T47 |
105 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |