Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7994705 |
1 |
|
|
T41 |
68 |
|
T42 |
354 |
|
T43 |
414 |
| auto[1] |
5807545 |
1 |
|
|
T41 |
23 |
|
T44 |
58700 |
|
T46 |
497 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11377563 |
1 |
|
|
T41 |
84 |
|
T42 |
354 |
|
T43 |
414 |
| auto[1] |
2424687 |
1 |
|
|
T41 |
7 |
|
T44 |
22707 |
|
T46 |
113 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8019808 |
1 |
|
|
T41 |
72 |
|
T42 |
354 |
|
T43 |
414 |
| auto[1] |
5782442 |
1 |
|
|
T41 |
19 |
|
T44 |
56596 |
|
T46 |
476 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1680684 |
1 |
|
|
T41 |
8 |
|
T44 |
17076 |
|
T46 |
192 |
| auto[1] |
auto[0] |
auto[1] |
1212339 |
1 |
|
|
T41 |
6 |
|
T44 |
11537 |
|
T46 |
42 |
| auto[1] |
auto[1] |
auto[0] |
1677071 |
1 |
|
|
T41 |
4 |
|
T44 |
16813 |
|
T46 |
171 |
| auto[1] |
auto[1] |
auto[1] |
1212348 |
1 |
|
|
T41 |
1 |
|
T44 |
11170 |
|
T46 |
71 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |