Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8000905 |
1 |
|
|
T41 |
69 |
|
T42 |
354 |
|
T43 |
414 |
| auto[1] |
5801345 |
1 |
|
|
T41 |
22 |
|
T44 |
58483 |
|
T46 |
541 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11373975 |
1 |
|
|
T41 |
78 |
|
T42 |
354 |
|
T43 |
414 |
| auto[1] |
2428275 |
1 |
|
|
T41 |
13 |
|
T44 |
23628 |
|
T46 |
121 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7989777 |
1 |
|
|
T41 |
60 |
|
T42 |
354 |
|
T43 |
414 |
| auto[1] |
5812473 |
1 |
|
|
T41 |
31 |
|
T44 |
57675 |
|
T46 |
648 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1691562 |
1 |
|
|
T41 |
17 |
|
T44 |
17091 |
|
T46 |
278 |
| auto[1] |
auto[0] |
auto[1] |
1219239 |
1 |
|
|
T41 |
8 |
|
T44 |
11873 |
|
T46 |
54 |
| auto[1] |
auto[1] |
auto[0] |
1692636 |
1 |
|
|
T41 |
1 |
|
T44 |
16956 |
|
T46 |
249 |
| auto[1] |
auto[1] |
auto[1] |
1209036 |
1 |
|
|
T41 |
5 |
|
T44 |
11755 |
|
T46 |
67 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |