Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7986862 |
1 |
|
|
T41 |
79 |
|
T42 |
354 |
|
T43 |
414 |
| auto[1] |
5815388 |
1 |
|
|
T41 |
12 |
|
T44 |
57763 |
|
T46 |
597 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13055782 |
1 |
|
|
T41 |
90 |
|
T42 |
354 |
|
T43 |
414 |
| auto[1] |
746468 |
1 |
|
|
T41 |
1 |
|
T44 |
7657 |
|
T46 |
24 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7974746 |
1 |
|
|
T41 |
80 |
|
T42 |
354 |
|
T43 |
414 |
| auto[1] |
5827504 |
1 |
|
|
T41 |
11 |
|
T44 |
57477 |
|
T46 |
576 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2546375 |
1 |
|
|
T41 |
10 |
|
T44 |
25349 |
|
T46 |
242 |
| auto[1] |
auto[0] |
auto[1] |
373936 |
1 |
|
|
T41 |
1 |
|
T44 |
3891 |
|
T46 |
13 |
| auto[1] |
auto[1] |
auto[0] |
2534661 |
1 |
|
|
T44 |
24471 |
|
T46 |
310 |
|
T47 |
439 |
| auto[1] |
auto[1] |
auto[1] |
372532 |
1 |
|
|
T44 |
3766 |
|
T46 |
11 |
|
T47 |
91 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |