Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7993140 |
1 |
|
|
T41 |
85 |
|
T42 |
354 |
|
T43 |
414 |
| auto[1] |
5809110 |
1 |
|
|
T41 |
6 |
|
T44 |
60093 |
|
T46 |
598 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11375930 |
1 |
|
|
T41 |
89 |
|
T42 |
354 |
|
T43 |
414 |
| auto[1] |
2426320 |
1 |
|
|
T41 |
2 |
|
T44 |
23456 |
|
T46 |
101 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7992328 |
1 |
|
|
T41 |
79 |
|
T42 |
354 |
|
T43 |
414 |
| auto[1] |
5809922 |
1 |
|
|
T41 |
12 |
|
T44 |
58191 |
|
T46 |
413 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1688859 |
1 |
|
|
T41 |
10 |
|
T44 |
17053 |
|
T46 |
139 |
| auto[1] |
auto[0] |
auto[1] |
1209167 |
1 |
|
|
T41 |
2 |
|
T44 |
11455 |
|
T46 |
51 |
| auto[1] |
auto[1] |
auto[0] |
1694743 |
1 |
|
|
T44 |
17682 |
|
T46 |
173 |
|
T47 |
169 |
| auto[1] |
auto[1] |
auto[1] |
1217153 |
1 |
|
|
T44 |
12001 |
|
T46 |
50 |
|
T47 |
206 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |