Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8035197 |
1 |
|
|
T41 |
75 |
|
T42 |
354 |
|
T43 |
414 |
| auto[1] |
5767053 |
1 |
|
|
T41 |
16 |
|
T44 |
59468 |
|
T46 |
390 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13054697 |
1 |
|
|
T41 |
91 |
|
T42 |
354 |
|
T43 |
414 |
| auto[1] |
747553 |
1 |
|
|
T44 |
7978 |
|
T46 |
21 |
|
T47 |
163 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7973751 |
1 |
|
|
T41 |
78 |
|
T42 |
354 |
|
T43 |
414 |
| auto[1] |
5828499 |
1 |
|
|
T41 |
13 |
|
T44 |
60046 |
|
T46 |
480 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2557008 |
1 |
|
|
T41 |
5 |
|
T44 |
26152 |
|
T46 |
295 |
| auto[1] |
auto[0] |
auto[1] |
377238 |
1 |
|
|
T44 |
4025 |
|
T46 |
13 |
|
T47 |
94 |
| auto[1] |
auto[1] |
auto[0] |
2523938 |
1 |
|
|
T41 |
8 |
|
T44 |
25916 |
|
T46 |
164 |
| auto[1] |
auto[1] |
auto[1] |
370315 |
1 |
|
|
T44 |
3953 |
|
T46 |
8 |
|
T47 |
69 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |