Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.63 99.06 99.24 100.00 99.80 99.68 99.99


Total test records in report: 942
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html
T120 /workspace/coverage/cover_reg_top/11.gpio_csr_rw.1589534485 Apr 21 12:37:44 PM PDT 24 Apr 21 12:37:45 PM PDT 24 35387606 ps
T135 /workspace/coverage/cover_reg_top/18.gpio_same_csr_outstanding.2209435030 Apr 21 12:37:45 PM PDT 24 Apr 21 12:37:46 PM PDT 24 13858913 ps
T766 /workspace/coverage/cover_reg_top/1.gpio_intr_test.1685900159 Apr 21 12:37:56 PM PDT 24 Apr 21 12:37:57 PM PDT 24 29714835 ps
T767 /workspace/coverage/cover_reg_top/3.gpio_tl_errors.1193694471 Apr 21 12:37:34 PM PDT 24 Apr 21 12:37:36 PM PDT 24 162965313 ps
T768 /workspace/coverage/cover_reg_top/37.gpio_intr_test.849688231 Apr 21 12:38:18 PM PDT 24 Apr 21 12:38:19 PM PDT 24 33896307 ps
T769 /workspace/coverage/cover_reg_top/6.gpio_csr_mem_rw_with_rand_reset.1356932415 Apr 21 12:37:55 PM PDT 24 Apr 21 12:37:57 PM PDT 24 27252231 ps
T770 /workspace/coverage/cover_reg_top/40.gpio_intr_test.4092526105 Apr 21 12:38:13 PM PDT 24 Apr 21 12:38:15 PM PDT 24 41892824 ps
T140 /workspace/coverage/cover_reg_top/8.gpio_tl_intg_err.781447243 Apr 21 12:37:52 PM PDT 24 Apr 21 12:37:53 PM PDT 24 50787175 ps
T68 /workspace/coverage/cover_reg_top/12.gpio_tl_intg_err.1564895609 Apr 21 12:38:00 PM PDT 24 Apr 21 12:38:01 PM PDT 24 173539486 ps
T771 /workspace/coverage/cover_reg_top/24.gpio_intr_test.1501926503 Apr 21 12:38:11 PM PDT 24 Apr 21 12:38:12 PM PDT 24 23925180 ps
T772 /workspace/coverage/cover_reg_top/18.gpio_csr_mem_rw_with_rand_reset.3372687924 Apr 21 12:38:16 PM PDT 24 Apr 21 12:38:18 PM PDT 24 23149326 ps
T773 /workspace/coverage/cover_reg_top/7.gpio_csr_rw.261103870 Apr 21 12:37:58 PM PDT 24 Apr 21 12:37:59 PM PDT 24 45439700 ps
T774 /workspace/coverage/cover_reg_top/44.gpio_intr_test.879466937 Apr 21 12:38:08 PM PDT 24 Apr 21 12:38:09 PM PDT 24 10995377 ps
T775 /workspace/coverage/cover_reg_top/17.gpio_tl_errors.1366606731 Apr 21 12:37:46 PM PDT 24 Apr 21 12:37:48 PM PDT 24 107124373 ps
T65 /workspace/coverage/cover_reg_top/19.gpio_tl_intg_err.4134647025 Apr 21 12:38:12 PM PDT 24 Apr 21 12:38:14 PM PDT 24 297491772 ps
T776 /workspace/coverage/cover_reg_top/0.gpio_same_csr_outstanding.2367290733 Apr 21 12:37:48 PM PDT 24 Apr 21 12:37:49 PM PDT 24 93592810 ps
T777 /workspace/coverage/cover_reg_top/10.gpio_csr_rw.2337069377 Apr 21 12:37:40 PM PDT 24 Apr 21 12:37:41 PM PDT 24 16015096 ps
T778 /workspace/coverage/cover_reg_top/38.gpio_intr_test.438932638 Apr 21 12:38:08 PM PDT 24 Apr 21 12:38:09 PM PDT 24 83280148 ps
T779 /workspace/coverage/cover_reg_top/12.gpio_tl_errors.234753139 Apr 21 12:37:55 PM PDT 24 Apr 21 12:37:57 PM PDT 24 193037573 ps
T69 /workspace/coverage/cover_reg_top/7.gpio_tl_intg_err.2490958512 Apr 21 12:37:37 PM PDT 24 Apr 21 12:37:39 PM PDT 24 120469709 ps
T121 /workspace/coverage/cover_reg_top/16.gpio_csr_rw.3580907301 Apr 21 12:37:57 PM PDT 24 Apr 21 12:37:58 PM PDT 24 14833060 ps
T780 /workspace/coverage/cover_reg_top/6.gpio_same_csr_outstanding.512530831 Apr 21 12:37:40 PM PDT 24 Apr 21 12:37:41 PM PDT 24 48728223 ps
T781 /workspace/coverage/cover_reg_top/15.gpio_csr_mem_rw_with_rand_reset.2777994351 Apr 21 12:37:49 PM PDT 24 Apr 21 12:37:51 PM PDT 24 16093549 ps
T122 /workspace/coverage/cover_reg_top/18.gpio_csr_rw.23085212 Apr 21 12:38:15 PM PDT 24 Apr 21 12:38:16 PM PDT 24 47046404 ps
T782 /workspace/coverage/cover_reg_top/2.gpio_csr_mem_rw_with_rand_reset.733136012 Apr 21 12:37:49 PM PDT 24 Apr 21 12:37:51 PM PDT 24 97496495 ps
T783 /workspace/coverage/cover_reg_top/9.gpio_tl_errors.2037362448 Apr 21 12:37:49 PM PDT 24 Apr 21 12:37:53 PM PDT 24 292453577 ps
T784 /workspace/coverage/cover_reg_top/34.gpio_intr_test.849752886 Apr 21 12:38:13 PM PDT 24 Apr 21 12:38:14 PM PDT 24 51316460 ps
T785 /workspace/coverage/cover_reg_top/0.gpio_csr_bit_bash.2061969837 Apr 21 12:37:45 PM PDT 24 Apr 21 12:37:48 PM PDT 24 91245408 ps
T786 /workspace/coverage/cover_reg_top/23.gpio_intr_test.1127847037 Apr 21 12:38:15 PM PDT 24 Apr 21 12:38:17 PM PDT 24 15184204 ps
T787 /workspace/coverage/cover_reg_top/17.gpio_csr_mem_rw_with_rand_reset.205962777 Apr 21 12:37:55 PM PDT 24 Apr 21 12:37:57 PM PDT 24 40587280 ps
T788 /workspace/coverage/cover_reg_top/14.gpio_tl_errors.3954336901 Apr 21 12:38:10 PM PDT 24 Apr 21 12:38:13 PM PDT 24 285305766 ps
T789 /workspace/coverage/cover_reg_top/11.gpio_csr_mem_rw_with_rand_reset.584942302 Apr 21 12:37:44 PM PDT 24 Apr 21 12:37:46 PM PDT 24 84173123 ps
T790 /workspace/coverage/cover_reg_top/47.gpio_intr_test.174122130 Apr 21 12:38:49 PM PDT 24 Apr 21 12:38:51 PM PDT 24 13536671 ps
T791 /workspace/coverage/cover_reg_top/3.gpio_csr_hw_reset.1977801646 Apr 21 12:37:53 PM PDT 24 Apr 21 12:37:54 PM PDT 24 15302082 ps
T792 /workspace/coverage/cover_reg_top/13.gpio_csr_rw.398805655 Apr 21 12:37:46 PM PDT 24 Apr 21 12:37:48 PM PDT 24 16315605 ps
T793 /workspace/coverage/cover_reg_top/22.gpio_intr_test.144750790 Apr 21 12:38:14 PM PDT 24 Apr 21 12:38:15 PM PDT 24 42472163 ps
T66 /workspace/coverage/cover_reg_top/9.gpio_tl_intg_err.1513579359 Apr 21 12:37:45 PM PDT 24 Apr 21 12:37:47 PM PDT 24 332770389 ps
T794 /workspace/coverage/cover_reg_top/0.gpio_tl_errors.115571453 Apr 21 12:37:46 PM PDT 24 Apr 21 12:37:49 PM PDT 24 97623789 ps
T795 /workspace/coverage/cover_reg_top/5.gpio_intr_test.2520806349 Apr 21 12:37:51 PM PDT 24 Apr 21 12:37:52 PM PDT 24 15656360 ps
T123 /workspace/coverage/cover_reg_top/4.gpio_csr_aliasing.232682808 Apr 21 12:37:44 PM PDT 24 Apr 21 12:37:45 PM PDT 24 91958121 ps
T796 /workspace/coverage/cover_reg_top/32.gpio_intr_test.2971795380 Apr 21 12:38:18 PM PDT 24 Apr 21 12:38:19 PM PDT 24 94972076 ps
T797 /workspace/coverage/cover_reg_top/9.gpio_intr_test.3596084113 Apr 21 12:38:05 PM PDT 24 Apr 21 12:38:07 PM PDT 24 26678217 ps
T798 /workspace/coverage/cover_reg_top/19.gpio_csr_rw.298505647 Apr 21 12:38:00 PM PDT 24 Apr 21 12:38:06 PM PDT 24 15733584 ps
T799 /workspace/coverage/cover_reg_top/4.gpio_tl_errors.1017666636 Apr 21 12:37:59 PM PDT 24 Apr 21 12:38:01 PM PDT 24 42249456 ps
T800 /workspace/coverage/cover_reg_top/6.gpio_intr_test.852622700 Apr 21 12:37:39 PM PDT 24 Apr 21 12:37:40 PM PDT 24 31649626 ps
T801 /workspace/coverage/cover_reg_top/2.gpio_csr_rw.2733134797 Apr 21 12:37:52 PM PDT 24 Apr 21 12:37:53 PM PDT 24 32515504 ps
T802 /workspace/coverage/cover_reg_top/39.gpio_intr_test.1702684720 Apr 21 12:37:54 PM PDT 24 Apr 21 12:37:55 PM PDT 24 41799543 ps
T124 /workspace/coverage/cover_reg_top/1.gpio_csr_bit_bash.4176533352 Apr 21 12:37:57 PM PDT 24 Apr 21 12:38:00 PM PDT 24 1090315406 ps
T803 /workspace/coverage/cover_reg_top/14.gpio_same_csr_outstanding.807846121 Apr 21 12:38:20 PM PDT 24 Apr 21 12:38:22 PM PDT 24 138650215 ps
T804 /workspace/coverage/cover_reg_top/0.gpio_csr_rw.2017235837 Apr 21 12:37:39 PM PDT 24 Apr 21 12:37:40 PM PDT 24 42684307 ps
T805 /workspace/coverage/cover_reg_top/12.gpio_intr_test.180537329 Apr 21 12:37:58 PM PDT 24 Apr 21 12:37:59 PM PDT 24 96061634 ps
T806 /workspace/coverage/cover_reg_top/16.gpio_csr_mem_rw_with_rand_reset.2817068907 Apr 21 12:37:47 PM PDT 24 Apr 21 12:37:48 PM PDT 24 87313053 ps
T807 /workspace/coverage/cover_reg_top/9.gpio_same_csr_outstanding.1245755473 Apr 21 12:38:00 PM PDT 24 Apr 21 12:38:02 PM PDT 24 56160740 ps
T808 /workspace/coverage/cover_reg_top/1.gpio_csr_rw.2177151646 Apr 21 12:37:37 PM PDT 24 Apr 21 12:37:38 PM PDT 24 31465220 ps
T67 /workspace/coverage/cover_reg_top/10.gpio_tl_intg_err.2695308007 Apr 21 12:38:05 PM PDT 24 Apr 21 12:38:06 PM PDT 24 161700313 ps
T809 /workspace/coverage/cover_reg_top/18.gpio_tl_errors.170222540 Apr 21 12:38:15 PM PDT 24 Apr 21 12:38:17 PM PDT 24 582440172 ps
T810 /workspace/coverage/cover_reg_top/2.gpio_same_csr_outstanding.3642875432 Apr 21 12:37:46 PM PDT 24 Apr 21 12:37:47 PM PDT 24 57602646 ps
T811 /workspace/coverage/cover_reg_top/35.gpio_intr_test.1476159992 Apr 21 12:38:17 PM PDT 24 Apr 21 12:38:18 PM PDT 24 15177911 ps
T812 /workspace/coverage/cover_reg_top/16.gpio_tl_errors.1389883157 Apr 21 12:38:17 PM PDT 24 Apr 21 12:38:30 PM PDT 24 517153820 ps
T813 /workspace/coverage/cover_reg_top/31.gpio_intr_test.2704618274 Apr 21 12:38:02 PM PDT 24 Apr 21 12:38:04 PM PDT 24 33178356 ps
T125 /workspace/coverage/cover_reg_top/0.gpio_csr_aliasing.2435959368 Apr 21 12:37:56 PM PDT 24 Apr 21 12:37:57 PM PDT 24 34888505 ps
T814 /workspace/coverage/cover_reg_top/45.gpio_intr_test.3086178551 Apr 21 12:37:54 PM PDT 24 Apr 21 12:37:55 PM PDT 24 24446949 ps
T126 /workspace/coverage/cover_reg_top/6.gpio_csr_rw.233820259 Apr 21 12:38:05 PM PDT 24 Apr 21 12:38:06 PM PDT 24 19784018 ps
T815 /workspace/coverage/cover_reg_top/3.gpio_csr_aliasing.2826684371 Apr 21 12:37:46 PM PDT 24 Apr 21 12:37:48 PM PDT 24 19763283 ps
T816 /workspace/coverage/cover_reg_top/7.gpio_intr_test.4183722448 Apr 21 12:37:56 PM PDT 24 Apr 21 12:37:57 PM PDT 24 11828314 ps
T817 /workspace/coverage/cover_reg_top/8.gpio_tl_errors.3437531405 Apr 21 12:37:41 PM PDT 24 Apr 21 12:37:43 PM PDT 24 46626017 ps
T818 /workspace/coverage/cover_reg_top/11.gpio_same_csr_outstanding.3429778438 Apr 21 12:37:45 PM PDT 24 Apr 21 12:37:47 PM PDT 24 29384088 ps
T819 /workspace/coverage/cover_reg_top/3.gpio_same_csr_outstanding.3291313283 Apr 21 12:37:53 PM PDT 24 Apr 21 12:37:54 PM PDT 24 216954176 ps
T820 /workspace/coverage/cover_reg_top/5.gpio_tl_errors.3589275894 Apr 21 12:37:49 PM PDT 24 Apr 21 12:37:51 PM PDT 24 65494865 ps
T821 /workspace/coverage/cover_reg_top/17.gpio_same_csr_outstanding.2131576853 Apr 21 12:38:04 PM PDT 24 Apr 21 12:38:05 PM PDT 24 35856092 ps
T822 /workspace/coverage/cover_reg_top/15.gpio_intr_test.3813606310 Apr 21 12:38:10 PM PDT 24 Apr 21 12:38:11 PM PDT 24 18148751 ps
T823 /workspace/coverage/cover_reg_top/13.gpio_tl_errors.4210910054 Apr 21 12:37:41 PM PDT 24 Apr 21 12:37:43 PM PDT 24 43777294 ps
T824 /workspace/coverage/cover_reg_top/4.gpio_same_csr_outstanding.1264505621 Apr 21 12:37:53 PM PDT 24 Apr 21 12:37:54 PM PDT 24 21219275 ps
T825 /workspace/coverage/cover_reg_top/19.gpio_same_csr_outstanding.452804179 Apr 21 12:37:55 PM PDT 24 Apr 21 12:37:56 PM PDT 24 31567100 ps
T826 /workspace/coverage/cover_reg_top/42.gpio_intr_test.3356058539 Apr 21 12:37:49 PM PDT 24 Apr 21 12:37:50 PM PDT 24 16470437 ps
T827 /workspace/coverage/cover_reg_top/13.gpio_tl_intg_err.2999885507 Apr 21 12:38:14 PM PDT 24 Apr 21 12:38:21 PM PDT 24 90078640 ps
T828 /workspace/coverage/cover_reg_top/15.gpio_tl_errors.1493495426 Apr 21 12:38:11 PM PDT 24 Apr 21 12:38:14 PM PDT 24 326566959 ps
T829 /workspace/coverage/cover_reg_top/4.gpio_csr_bit_bash.4147550270 Apr 21 12:37:51 PM PDT 24 Apr 21 12:37:55 PM PDT 24 394647513 ps
T830 /workspace/coverage/cover_reg_top/14.gpio_intr_test.4127969269 Apr 21 12:38:11 PM PDT 24 Apr 21 12:38:17 PM PDT 24 91461697 ps
T127 /workspace/coverage/cover_reg_top/8.gpio_csr_rw.3814084125 Apr 21 12:38:09 PM PDT 24 Apr 21 12:38:15 PM PDT 24 19103436 ps
T831 /workspace/coverage/cover_reg_top/1.gpio_csr_mem_rw_with_rand_reset.2224914538 Apr 21 12:37:50 PM PDT 24 Apr 21 12:37:52 PM PDT 24 28186213 ps
T832 /workspace/coverage/cover_reg_top/12.gpio_csr_rw.135503910 Apr 21 12:37:50 PM PDT 24 Apr 21 12:37:51 PM PDT 24 27434141 ps
T833 /workspace/coverage/cover_reg_top/1.gpio_tl_intg_err.108438361 Apr 21 12:37:56 PM PDT 24 Apr 21 12:37:58 PM PDT 24 280636532 ps
T834 /workspace/coverage/cover_reg_top/26.gpio_intr_test.2564638954 Apr 21 12:38:02 PM PDT 24 Apr 21 12:38:04 PM PDT 24 39580132 ps
T835 /workspace/coverage/cover_reg_top/15.gpio_tl_intg_err.3822659787 Apr 21 12:37:56 PM PDT 24 Apr 21 12:38:02 PM PDT 24 298838632 ps
T836 /workspace/coverage/cover_reg_top/0.gpio_intr_test.1977053156 Apr 21 12:37:45 PM PDT 24 Apr 21 12:37:57 PM PDT 24 16307925 ps
T837 /workspace/coverage/cover_reg_top/14.gpio_tl_intg_err.3454103627 Apr 21 12:38:17 PM PDT 24 Apr 21 12:38:19 PM PDT 24 324480781 ps
T838 /workspace/coverage/cover_reg_top/3.gpio_intr_test.1804863953 Apr 21 12:37:54 PM PDT 24 Apr 21 12:37:55 PM PDT 24 12496540 ps
T839 /workspace/coverage/cover_reg_top/2.gpio_intr_test.524643136 Apr 21 12:37:58 PM PDT 24 Apr 21 12:37:59 PM PDT 24 98054000 ps
T840 /workspace/coverage/cover_reg_top/11.gpio_tl_errors.2967658375 Apr 21 12:37:57 PM PDT 24 Apr 21 12:38:00 PM PDT 24 601623815 ps
T841 /workspace/coverage/cover_reg_top/6.gpio_tl_intg_err.3280542365 Apr 21 12:37:52 PM PDT 24 Apr 21 12:37:54 PM PDT 24 185723877 ps
T842 /workspace/coverage/cover_reg_top/10.gpio_tl_errors.3474800238 Apr 21 12:37:49 PM PDT 24 Apr 21 12:37:51 PM PDT 24 132438725 ps
T843 /workspace/coverage/en_cdc_prims/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4122397016 Apr 21 12:22:33 PM PDT 24 Apr 21 12:22:34 PM PDT 24 111030834 ps
T844 /workspace/coverage/en_cdc_prims/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2679703723 Apr 21 12:21:44 PM PDT 24 Apr 21 12:21:46 PM PDT 24 109015918 ps
T845 /workspace/coverage/en_cdc_prims/35.gpio_smoke_en_cdc_prim.696797719 Apr 21 12:22:41 PM PDT 24 Apr 21 12:22:43 PM PDT 24 65016385 ps
T846 /workspace/coverage/en_cdc_prims/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3865168523 Apr 21 12:22:50 PM PDT 24 Apr 21 12:22:51 PM PDT 24 46123095 ps
T847 /workspace/coverage/en_cdc_prims/23.gpio_smoke_en_cdc_prim.2590919261 Apr 21 12:19:44 PM PDT 24 Apr 21 12:19:45 PM PDT 24 102611714 ps
T848 /workspace/coverage/en_cdc_prims/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2712318872 Apr 21 12:22:33 PM PDT 24 Apr 21 12:22:34 PM PDT 24 43628603 ps
T849 /workspace/coverage/en_cdc_prims/6.gpio_smoke_en_cdc_prim.2648413340 Apr 21 12:21:37 PM PDT 24 Apr 21 12:21:39 PM PDT 24 335832514 ps
T850 /workspace/coverage/en_cdc_prims/30.gpio_smoke_en_cdc_prim.165193956 Apr 21 12:22:49 PM PDT 24 Apr 21 12:22:52 PM PDT 24 393330792 ps
T851 /workspace/coverage/en_cdc_prims/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2602686938 Apr 21 12:17:46 PM PDT 24 Apr 21 12:17:48 PM PDT 24 51883341 ps
T852 /workspace/coverage/en_cdc_prims/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1923810534 Apr 21 12:22:34 PM PDT 24 Apr 21 12:22:36 PM PDT 24 238052393 ps
T853 /workspace/coverage/en_cdc_prims/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1437632487 Apr 21 12:23:02 PM PDT 24 Apr 21 12:23:03 PM PDT 24 452155763 ps
T854 /workspace/coverage/en_cdc_prims/44.gpio_smoke_en_cdc_prim.212943837 Apr 21 12:18:54 PM PDT 24 Apr 21 12:18:55 PM PDT 24 193925124 ps
T855 /workspace/coverage/en_cdc_prims/40.gpio_smoke_en_cdc_prim.3608553271 Apr 21 12:23:48 PM PDT 24 Apr 21 12:23:49 PM PDT 24 492778228 ps
T856 /workspace/coverage/en_cdc_prims/43.gpio_smoke_en_cdc_prim.719216775 Apr 21 12:22:50 PM PDT 24 Apr 21 12:22:52 PM PDT 24 138537833 ps
T857 /workspace/coverage/en_cdc_prims/15.gpio_smoke_en_cdc_prim.2376004001 Apr 21 12:20:52 PM PDT 24 Apr 21 12:20:53 PM PDT 24 341910518 ps
T858 /workspace/coverage/en_cdc_prims/27.gpio_smoke_en_cdc_prim.3964693680 Apr 21 12:20:51 PM PDT 24 Apr 21 12:20:53 PM PDT 24 38888974 ps
T859 /workspace/coverage/en_cdc_prims/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3999680351 Apr 21 12:23:44 PM PDT 24 Apr 21 12:23:45 PM PDT 24 45855246 ps
T860 /workspace/coverage/en_cdc_prims/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim.717835246 Apr 21 12:22:34 PM PDT 24 Apr 21 12:22:36 PM PDT 24 906317489 ps
T861 /workspace/coverage/en_cdc_prims/36.gpio_smoke_en_cdc_prim.1952461112 Apr 21 12:18:40 PM PDT 24 Apr 21 12:18:42 PM PDT 24 65408731 ps
T862 /workspace/coverage/en_cdc_prims/41.gpio_smoke_en_cdc_prim.2398375698 Apr 21 12:20:30 PM PDT 24 Apr 21 12:20:32 PM PDT 24 136237727 ps
T863 /workspace/coverage/en_cdc_prims/28.gpio_smoke_en_cdc_prim.298660656 Apr 21 12:23:44 PM PDT 24 Apr 21 12:23:46 PM PDT 24 135613346 ps
T864 /workspace/coverage/en_cdc_prims/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4234690186 Apr 21 12:17:45 PM PDT 24 Apr 21 12:17:47 PM PDT 24 100197757 ps
T865 /workspace/coverage/en_cdc_prims/25.gpio_smoke_en_cdc_prim.224913985 Apr 21 12:23:44 PM PDT 24 Apr 21 12:23:46 PM PDT 24 50517608 ps
T866 /workspace/coverage/en_cdc_prims/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2849154968 Apr 21 12:20:51 PM PDT 24 Apr 21 12:20:53 PM PDT 24 56968132 ps
T867 /workspace/coverage/en_cdc_prims/11.gpio_smoke_en_cdc_prim.527770714 Apr 21 12:21:19 PM PDT 24 Apr 21 12:21:20 PM PDT 24 37090856 ps
T868 /workspace/coverage/en_cdc_prims/7.gpio_smoke_en_cdc_prim.2942098874 Apr 21 12:17:53 PM PDT 24 Apr 21 12:17:55 PM PDT 24 261403482 ps
T869 /workspace/coverage/en_cdc_prims/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1414256670 Apr 21 12:21:30 PM PDT 24 Apr 21 12:21:31 PM PDT 24 93670198 ps
T870 /workspace/coverage/en_cdc_prims/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim.21717686 Apr 21 12:22:42 PM PDT 24 Apr 21 12:22:43 PM PDT 24 18170124 ps
T871 /workspace/coverage/en_cdc_prims/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1618295488 Apr 21 12:19:30 PM PDT 24 Apr 21 12:19:31 PM PDT 24 31654923 ps
T872 /workspace/coverage/en_cdc_prims/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2021673141 Apr 21 12:17:46 PM PDT 24 Apr 21 12:17:48 PM PDT 24 78921109 ps
T873 /workspace/coverage/en_cdc_prims/4.gpio_smoke_en_cdc_prim.3036163715 Apr 21 12:22:31 PM PDT 24 Apr 21 12:22:32 PM PDT 24 25389621 ps
T874 /workspace/coverage/en_cdc_prims/22.gpio_smoke_en_cdc_prim.2332836159 Apr 21 12:18:24 PM PDT 24 Apr 21 12:18:26 PM PDT 24 53673346 ps
T875 /workspace/coverage/en_cdc_prims/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1286270685 Apr 21 12:22:33 PM PDT 24 Apr 21 12:22:34 PM PDT 24 51910292 ps
T876 /workspace/coverage/en_cdc_prims/33.gpio_smoke_en_cdc_prim.2881977459 Apr 21 12:23:44 PM PDT 24 Apr 21 12:23:46 PM PDT 24 44568905 ps
T877 /workspace/coverage/en_cdc_prims/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1892291697 Apr 21 12:22:41 PM PDT 24 Apr 21 12:22:43 PM PDT 24 145250029 ps
T878 /workspace/coverage/en_cdc_prims/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3008997375 Apr 21 12:17:49 PM PDT 24 Apr 21 12:17:51 PM PDT 24 115612741 ps
T879 /workspace/coverage/en_cdc_prims/46.gpio_smoke_en_cdc_prim.31089882 Apr 21 12:22:33 PM PDT 24 Apr 21 12:22:35 PM PDT 24 409290794 ps
T880 /workspace/coverage/en_cdc_prims/34.gpio_smoke_en_cdc_prim.4138224929 Apr 21 12:23:44 PM PDT 24 Apr 21 12:23:46 PM PDT 24 170548459 ps
T881 /workspace/coverage/en_cdc_prims/32.gpio_smoke_en_cdc_prim.2817881804 Apr 21 12:21:48 PM PDT 24 Apr 21 12:21:50 PM PDT 24 207816990 ps
T882 /workspace/coverage/en_cdc_prims/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2746589500 Apr 21 12:19:30 PM PDT 24 Apr 21 12:19:31 PM PDT 24 121630863 ps
T883 /workspace/coverage/en_cdc_prims/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2778448899 Apr 21 12:22:33 PM PDT 24 Apr 21 12:22:35 PM PDT 24 133282852 ps
T884 /workspace/coverage/en_cdc_prims/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4170071237 Apr 21 12:21:14 PM PDT 24 Apr 21 12:21:16 PM PDT 24 65746590 ps
T885 /workspace/coverage/en_cdc_prims/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3313570791 Apr 21 12:23:29 PM PDT 24 Apr 21 12:23:30 PM PDT 24 27843471 ps
T886 /workspace/coverage/en_cdc_prims/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2596966437 Apr 21 12:18:30 PM PDT 24 Apr 21 12:18:33 PM PDT 24 49744273 ps
T887 /workspace/coverage/en_cdc_prims/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim.572332482 Apr 21 12:23:44 PM PDT 24 Apr 21 12:23:45 PM PDT 24 30829974 ps
T888 /workspace/coverage/en_cdc_prims/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1623325754 Apr 21 12:17:45 PM PDT 24 Apr 21 12:17:47 PM PDT 24 54475712 ps
T889 /workspace/coverage/en_cdc_prims/31.gpio_smoke_en_cdc_prim.1213545140 Apr 21 12:20:32 PM PDT 24 Apr 21 12:20:33 PM PDT 24 75853364 ps
T890 /workspace/coverage/en_cdc_prims/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3146983434 Apr 21 12:17:53 PM PDT 24 Apr 21 12:17:55 PM PDT 24 166952307 ps
T891 /workspace/coverage/en_cdc_prims/9.gpio_smoke_en_cdc_prim.641000510 Apr 21 12:17:52 PM PDT 24 Apr 21 12:17:54 PM PDT 24 159839377 ps
T892 /workspace/coverage/en_cdc_prims/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3800116506 Apr 21 12:20:30 PM PDT 24 Apr 21 12:20:31 PM PDT 24 46373448 ps
T893 /workspace/coverage/en_cdc_prims/47.gpio_smoke_en_cdc_prim.1181612639 Apr 21 12:17:48 PM PDT 24 Apr 21 12:17:50 PM PDT 24 68558956 ps
T894 /workspace/coverage/en_cdc_prims/29.gpio_smoke_en_cdc_prim.3915537383 Apr 21 12:22:42 PM PDT 24 Apr 21 12:22:44 PM PDT 24 476070631 ps
T895 /workspace/coverage/en_cdc_prims/14.gpio_smoke_en_cdc_prim.2417106235 Apr 21 12:18:55 PM PDT 24 Apr 21 12:18:56 PM PDT 24 294285830 ps
T896 /workspace/coverage/en_cdc_prims/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3840791903 Apr 21 12:22:40 PM PDT 24 Apr 21 12:22:42 PM PDT 24 41555619 ps
T897 /workspace/coverage/en_cdc_prims/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2535414130 Apr 21 12:19:43 PM PDT 24 Apr 21 12:19:45 PM PDT 24 235872743 ps
T898 /workspace/coverage/en_cdc_prims/16.gpio_smoke_en_cdc_prim.3497108455 Apr 21 12:22:51 PM PDT 24 Apr 21 12:22:53 PM PDT 24 161873276 ps
T899 /workspace/coverage/en_cdc_prims/8.gpio_smoke_en_cdc_prim.1742367183 Apr 21 12:22:52 PM PDT 24 Apr 21 12:22:54 PM PDT 24 75943114 ps
T900 /workspace/coverage/en_cdc_prims/26.gpio_smoke_en_cdc_prim.3976623925 Apr 21 12:22:50 PM PDT 24 Apr 21 12:22:51 PM PDT 24 65245118 ps
T901 /workspace/coverage/en_cdc_prims/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4120975003 Apr 21 12:18:26 PM PDT 24 Apr 21 12:18:28 PM PDT 24 39224027 ps
T902 /workspace/coverage/en_cdc_prims/3.gpio_smoke_en_cdc_prim.919585903 Apr 21 12:21:44 PM PDT 24 Apr 21 12:21:45 PM PDT 24 58849067 ps
T903 /workspace/coverage/en_cdc_prims/0.gpio_smoke_en_cdc_prim.3965844679 Apr 21 12:22:28 PM PDT 24 Apr 21 12:22:29 PM PDT 24 37656649 ps
T904 /workspace/coverage/en_cdc_prims/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim.130496099 Apr 21 12:19:00 PM PDT 24 Apr 21 12:19:01 PM PDT 24 112484161 ps
T905 /workspace/coverage/en_cdc_prims/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1664253744 Apr 21 12:22:49 PM PDT 24 Apr 21 12:22:52 PM PDT 24 247261085 ps
T906 /workspace/coverage/en_cdc_prims/1.gpio_smoke_en_cdc_prim.3232800157 Apr 21 12:20:48 PM PDT 24 Apr 21 12:20:49 PM PDT 24 62006792 ps
T907 /workspace/coverage/en_cdc_prims/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3371069851 Apr 21 12:23:33 PM PDT 24 Apr 21 12:23:34 PM PDT 24 55777761 ps
T908 /workspace/coverage/en_cdc_prims/42.gpio_smoke_en_cdc_prim.3484193240 Apr 21 12:19:24 PM PDT 24 Apr 21 12:19:25 PM PDT 24 509849437 ps
T909 /workspace/coverage/en_cdc_prims/17.gpio_smoke_en_cdc_prim.2090466479 Apr 21 12:19:14 PM PDT 24 Apr 21 12:19:15 PM PDT 24 27938580 ps
T910 /workspace/coverage/en_cdc_prims/19.gpio_smoke_en_cdc_prim.1447126207 Apr 21 12:17:52 PM PDT 24 Apr 21 12:17:54 PM PDT 24 42402780 ps
T911 /workspace/coverage/en_cdc_prims/49.gpio_smoke_en_cdc_prim.14863540 Apr 21 12:22:33 PM PDT 24 Apr 21 12:22:35 PM PDT 24 65404888 ps
T912 /workspace/coverage/en_cdc_prims/20.gpio_smoke_en_cdc_prim.3403355765 Apr 21 12:23:33 PM PDT 24 Apr 21 12:23:34 PM PDT 24 184804326 ps
T913 /workspace/coverage/en_cdc_prims/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2790617202 Apr 21 12:22:52 PM PDT 24 Apr 21 12:22:54 PM PDT 24 211327031 ps
T914 /workspace/coverage/en_cdc_prims/45.gpio_smoke_en_cdc_prim.3961215835 Apr 21 12:18:50 PM PDT 24 Apr 21 12:18:52 PM PDT 24 40173030 ps
T915 /workspace/coverage/en_cdc_prims/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1886222014 Apr 21 12:20:30 PM PDT 24 Apr 21 12:20:32 PM PDT 24 34771441 ps
T916 /workspace/coverage/en_cdc_prims/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2679707245 Apr 21 12:22:33 PM PDT 24 Apr 21 12:22:35 PM PDT 24 78335253 ps
T917 /workspace/coverage/en_cdc_prims/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim.350199011 Apr 21 12:18:30 PM PDT 24 Apr 21 12:18:33 PM PDT 24 102441233 ps
T918 /workspace/coverage/en_cdc_prims/13.gpio_smoke_en_cdc_prim.1301721143 Apr 21 12:22:54 PM PDT 24 Apr 21 12:22:56 PM PDT 24 53775130 ps
T919 /workspace/coverage/en_cdc_prims/21.gpio_smoke_en_cdc_prim.1696245321 Apr 21 12:22:41 PM PDT 24 Apr 21 12:22:43 PM PDT 24 36695306 ps
T920 /workspace/coverage/en_cdc_prims/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1407995030 Apr 21 12:17:45 PM PDT 24 Apr 21 12:17:47 PM PDT 24 56435716 ps
T921 /workspace/coverage/en_cdc_prims/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1400975533 Apr 21 12:22:28 PM PDT 24 Apr 21 12:22:29 PM PDT 24 177990777 ps
T922 /workspace/coverage/en_cdc_prims/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim.529985074 Apr 21 12:20:30 PM PDT 24 Apr 21 12:20:32 PM PDT 24 233351886 ps
T923 /workspace/coverage/en_cdc_prims/38.gpio_smoke_en_cdc_prim.618442829 Apr 21 12:23:44 PM PDT 24 Apr 21 12:23:46 PM PDT 24 174822745 ps
T924 /workspace/coverage/en_cdc_prims/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2638981375 Apr 21 12:20:30 PM PDT 24 Apr 21 12:20:32 PM PDT 24 45409826 ps
T925 /workspace/coverage/en_cdc_prims/5.gpio_smoke_en_cdc_prim.1173461753 Apr 21 12:17:53 PM PDT 24 Apr 21 12:17:55 PM PDT 24 76642147 ps
T926 /workspace/coverage/en_cdc_prims/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3238471651 Apr 21 12:21:16 PM PDT 24 Apr 21 12:21:18 PM PDT 24 254144969 ps
T927 /workspace/coverage/en_cdc_prims/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4260099755 Apr 21 12:22:33 PM PDT 24 Apr 21 12:22:35 PM PDT 24 57137568 ps
T928 /workspace/coverage/en_cdc_prims/24.gpio_smoke_en_cdc_prim.1895840429 Apr 21 12:18:24 PM PDT 24 Apr 21 12:18:26 PM PDT 24 280110495 ps
T929 /workspace/coverage/en_cdc_prims/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3811899353 Apr 21 12:22:51 PM PDT 24 Apr 21 12:22:53 PM PDT 24 67642434 ps
T930 /workspace/coverage/en_cdc_prims/48.gpio_smoke_en_cdc_prim.3608282272 Apr 21 12:20:30 PM PDT 24 Apr 21 12:20:31 PM PDT 24 257957247 ps
T931 /workspace/coverage/en_cdc_prims/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim.631209426 Apr 21 12:20:30 PM PDT 24 Apr 21 12:20:31 PM PDT 24 30068567 ps
T932 /workspace/coverage/en_cdc_prims/12.gpio_smoke_en_cdc_prim.1434978751 Apr 21 12:22:33 PM PDT 24 Apr 21 12:22:35 PM PDT 24 44750424 ps
T933 /workspace/coverage/en_cdc_prims/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3063835810 Apr 21 12:20:30 PM PDT 24 Apr 21 12:20:32 PM PDT 24 142003335 ps
T934 /workspace/coverage/en_cdc_prims/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2807460355 Apr 21 12:20:30 PM PDT 24 Apr 21 12:20:32 PM PDT 24 634523715 ps
T935 /workspace/coverage/en_cdc_prims/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim.229193037 Apr 21 12:20:32 PM PDT 24 Apr 21 12:20:34 PM PDT 24 139144500 ps
T936 /workspace/coverage/en_cdc_prims/10.gpio_smoke_en_cdc_prim.678808192 Apr 21 12:22:33 PM PDT 24 Apr 21 12:22:35 PM PDT 24 190827345 ps
T937 /workspace/coverage/en_cdc_prims/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim.183531529 Apr 21 12:18:30 PM PDT 24 Apr 21 12:18:33 PM PDT 24 45519442 ps
T938 /workspace/coverage/en_cdc_prims/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2437355195 Apr 21 12:22:46 PM PDT 24 Apr 21 12:22:49 PM PDT 24 70845689 ps
T939 /workspace/coverage/en_cdc_prims/37.gpio_smoke_en_cdc_prim.2437883273 Apr 21 12:23:27 PM PDT 24 Apr 21 12:23:29 PM PDT 24 33925083 ps
T940 /workspace/coverage/en_cdc_prims/18.gpio_smoke_en_cdc_prim.2023842732 Apr 21 12:18:40 PM PDT 24 Apr 21 12:18:42 PM PDT 24 72252826 ps
T941 /workspace/coverage/en_cdc_prims/39.gpio_smoke_en_cdc_prim.563174338 Apr 21 12:21:29 PM PDT 24 Apr 21 12:21:31 PM PDT 24 1038753688 ps
T942 /workspace/coverage/en_cdc_prims/2.gpio_smoke_en_cdc_prim.4048992197 Apr 21 12:17:48 PM PDT 24 Apr 21 12:17:49 PM PDT 24 384134598 ps

Test location /workspace/coverage/default/5.gpio_random_long_reg_writes_reg_reads.820474102
Short name T46
Test name
Test status
Simulation time 248094036 ps
CPU time 2.94 seconds
Started Apr 21 12:46:03 PM PDT 24
Finished Apr 21 12:46:08 PM PDT 24
Peak memory 198172 kb
Host smart-9dad4577-9cce-4abc-afb6-9f217afe2ac0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=820474102 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_rand
om_long_reg_writes_reg_reads.820474102
Directory /workspace/5.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/42.gpio_intr_with_filter_rand_intr_event.464904167
Short name T75
Test name
Test status
Simulation time 121080708 ps
CPU time 2.47 seconds
Started Apr 21 12:47:34 PM PDT 24
Finished Apr 21 12:47:37 PM PDT 24
Peak memory 196668 kb
Host smart-11b7254e-3dc8-4c19-8a3b-17408076c1d9
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=464904167 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 42.gpio_intr_with_filter_rand_intr_event.464904167
Directory /workspace/42.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/7.gpio_stress_all_with_rand_reset.2109786008
Short name T53
Test name
Test status
Simulation time 476086068374 ps
CPU time 2493.91 seconds
Started Apr 21 12:46:17 PM PDT 24
Finished Apr 21 01:27:52 PM PDT 24
Peak memory 198372 kb
Host smart-ea7669d7-db4b-4731-aa30-dae2490b76c8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2109786008 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_stress_all_with_rand_reset.2109786008
Directory /workspace/7.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.gpio_sec_cm.895049283
Short name T59
Test name
Test status
Simulation time 36570755 ps
CPU time 0.8 seconds
Started Apr 21 12:45:58 PM PDT 24
Finished Apr 21 12:46:00 PM PDT 24
Peak memory 213720 kb
Host smart-c230ddce-1f2a-4fec-a337-0ea55828ff14
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=895049283 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_sec_cm.895049283
Directory /workspace/4.gpio_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_hw_reset.3636113385
Short name T104
Test name
Test status
Simulation time 23127467 ps
CPU time 0.63 seconds
Started Apr 21 12:37:48 PM PDT 24
Finished Apr 21 12:37:49 PM PDT 24
Peak memory 194644 kb
Host smart-69de56da-298b-454b-857e-3e65f29d4ef4
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3636113385 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_hw_reset.3636113385
Directory /workspace/1.gpio_csr_hw_reset/latest

Test location /workspace/coverage/default/0.gpio_stress_all.373488413
Short name T9
Test name
Test status
Simulation time 62045817459 ps
CPU time 190.48 seconds
Started Apr 21 12:45:47 PM PDT 24
Finished Apr 21 12:48:58 PM PDT 24
Peak memory 198268 kb
Host smart-b3102808-e87d-4284-a41e-3054cbd650fe
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=373488413 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gp
io_stress_all.373488413
Directory /workspace/0.gpio_stress_all/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_tl_intg_err.1341072170
Short name T71
Test name
Test status
Simulation time 982566061 ps
CPU time 1.12 seconds
Started Apr 21 12:38:03 PM PDT 24
Finished Apr 21 12:38:05 PM PDT 24
Peak memory 198124 kb
Host smart-a2603039-71bd-493b-80e6-4a8efb8d80d9
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1341072170 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 11.gpio_tl_intg_err.1341072170
Directory /workspace/11.gpio_tl_intg_err/latest

Test location /workspace/coverage/default/19.gpio_alert_test.385628117
Short name T61
Test name
Test status
Simulation time 37173138 ps
CPU time 0.61 seconds
Started Apr 21 12:46:43 PM PDT 24
Finished Apr 21 12:46:44 PM PDT 24
Peak memory 193980 kb
Host smart-42de38a6-b3b0-4e9f-a364-96c52566fa30
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=385628117 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_alert_test.385628117
Directory /workspace/19.gpio_alert_test/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_tl_intg_err.1513579359
Short name T66
Test name
Test status
Simulation time 332770389 ps
CPU time 1.11 seconds
Started Apr 21 12:37:45 PM PDT 24
Finished Apr 21 12:37:47 PM PDT 24
Peak memory 198128 kb
Host smart-d2c9e7ef-fc5d-4822-9098-884a6be3fd53
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1513579359 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 9.gpio_tl_intg_err.1513579359
Directory /workspace/9.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_same_csr_outstanding.1885296387
Short name T129
Test name
Test status
Simulation time 16886006 ps
CPU time 0.9 seconds
Started Apr 21 12:37:56 PM PDT 24
Finished Apr 21 12:37:59 PM PDT 24
Peak memory 195596 kb
Host smart-560ddc76-baf9-4182-83bf-918db30476f6
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1885296387 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 1.gpio_same_csr_outstanding.1885296387
Directory /workspace/1.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_tl_intg_err.2695308007
Short name T67
Test name
Test status
Simulation time 161700313 ps
CPU time 1.18 seconds
Started Apr 21 12:38:05 PM PDT 24
Finished Apr 21 12:38:06 PM PDT 24
Peak memory 198128 kb
Host smart-754f7e21-ac87-48d6-92b6-582163e72e94
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2695308007 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 10.gpio_tl_intg_err.2695308007
Directory /workspace/10.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_aliasing.2435959368
Short name T125
Test name
Test status
Simulation time 34888505 ps
CPU time 0.85 seconds
Started Apr 21 12:37:56 PM PDT 24
Finished Apr 21 12:37:57 PM PDT 24
Peak memory 196952 kb
Host smart-4b79262e-cc45-411f-aaae-2a04064e7194
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2435959368 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
0.gpio_csr_aliasing.2435959368
Directory /workspace/0.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_bit_bash.2061969837
Short name T785
Test name
Test status
Simulation time 91245408 ps
CPU time 1.48 seconds
Started Apr 21 12:37:45 PM PDT 24
Finished Apr 21 12:37:48 PM PDT 24
Peak memory 197180 kb
Host smart-bb601f6b-5331-4bba-8a2d-fbdf0c830190
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2061969837 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_bit_bash.2061969837
Directory /workspace/0.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_hw_reset.1983124182
Short name T103
Test name
Test status
Simulation time 39009905 ps
CPU time 0.64 seconds
Started Apr 21 12:37:38 PM PDT 24
Finished Apr 21 12:37:39 PM PDT 24
Peak memory 195008 kb
Host smart-5c1f86a3-c0bd-4b99-bdd5-85e8bd80aa97
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1983124182 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_hw_reset.1983124182
Directory /workspace/0.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_mem_rw_with_rand_reset.4084315003
Short name T743
Test name
Test status
Simulation time 36100497 ps
CPU time 0.91 seconds
Started Apr 21 12:37:57 PM PDT 24
Finished Apr 21 12:37:58 PM PDT 24
Peak memory 197888 kb
Host smart-1451ea35-215a-4c13-a6e4-555435745d95
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4084315003 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_mem_rw_with_rand_reset.4084315003
Directory /workspace/0.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_rw.2017235837
Short name T804
Test name
Test status
Simulation time 42684307 ps
CPU time 0.63 seconds
Started Apr 21 12:37:39 PM PDT 24
Finished Apr 21 12:37:40 PM PDT 24
Peak memory 195216 kb
Host smart-d49f75df-16c3-4ba4-8995-c385b17d8f94
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2017235837 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio
_csr_rw.2017235837
Directory /workspace/0.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_intr_test.1977053156
Short name T836
Test name
Test status
Simulation time 16307925 ps
CPU time 0.57 seconds
Started Apr 21 12:37:45 PM PDT 24
Finished Apr 21 12:37:57 PM PDT 24
Peak memory 194664 kb
Host smart-2add2ccb-3834-4fa8-9567-02c7245bc10d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1977053156 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_intr_test.1977053156
Directory /workspace/0.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_same_csr_outstanding.2367290733
Short name T776
Test name
Test status
Simulation time 93592810 ps
CPU time 0.62 seconds
Started Apr 21 12:37:48 PM PDT 24
Finished Apr 21 12:37:49 PM PDT 24
Peak memory 194424 kb
Host smart-e85cabd3-b816-4bc9-9934-73859a95a7f5
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2367290733 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 0.gpio_same_csr_outstanding.2367290733
Directory /workspace/0.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_tl_errors.115571453
Short name T794
Test name
Test status
Simulation time 97623789 ps
CPU time 2.17 seconds
Started Apr 21 12:37:46 PM PDT 24
Finished Apr 21 12:37:49 PM PDT 24
Peak memory 197196 kb
Host smart-92583b4c-d230-4deb-8a85-da2454d6918e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115571453 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_tl_errors.115571453
Directory /workspace/0.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_tl_intg_err.2792349161
Short name T139
Test name
Test status
Simulation time 83626513 ps
CPU time 1.15 seconds
Started Apr 21 12:38:01 PM PDT 24
Finished Apr 21 12:38:03 PM PDT 24
Peak memory 198132 kb
Host smart-cf06c4ef-bf70-497c-b28a-1c052bcbafea
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2792349161 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 0.gpio_tl_intg_err.2792349161
Directory /workspace/0.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_aliasing.599228731
Short name T738
Test name
Test status
Simulation time 43924613 ps
CPU time 0.68 seconds
Started Apr 21 12:38:06 PM PDT 24
Finished Apr 21 12:38:07 PM PDT 24
Peak memory 195636 kb
Host smart-fc9e129f-5b2f-4429-a8db-7b31019e7d09
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=599228731 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1
.gpio_csr_aliasing.599228731
Directory /workspace/1.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_bit_bash.4176533352
Short name T124
Test name
Test status
Simulation time 1090315406 ps
CPU time 2.52 seconds
Started Apr 21 12:37:57 PM PDT 24
Finished Apr 21 12:38:00 PM PDT 24
Peak memory 197276 kb
Host smart-73028d43-0e97-488c-b082-8e3e0b71345c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4176533352 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_bit_bash.4176533352
Directory /workspace/1.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_mem_rw_with_rand_reset.2224914538
Short name T831
Test name
Test status
Simulation time 28186213 ps
CPU time 1.38 seconds
Started Apr 21 12:37:50 PM PDT 24
Finished Apr 21 12:37:52 PM PDT 24
Peak memory 198108 kb
Host smart-8e7d52ff-1de1-437f-8f43-09ca34f591d0
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2224914538 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_mem_rw_with_rand_reset.2224914538
Directory /workspace/1.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_rw.2177151646
Short name T808
Test name
Test status
Simulation time 31465220 ps
CPU time 0.56 seconds
Started Apr 21 12:37:37 PM PDT 24
Finished Apr 21 12:37:38 PM PDT 24
Peak memory 193412 kb
Host smart-c29ee9e2-f3cf-49b3-8bf8-09bf3ef2fce6
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2177151646 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio
_csr_rw.2177151646
Directory /workspace/1.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_intr_test.1685900159
Short name T766
Test name
Test status
Simulation time 29714835 ps
CPU time 0.61 seconds
Started Apr 21 12:37:56 PM PDT 24
Finished Apr 21 12:37:57 PM PDT 24
Peak memory 194504 kb
Host smart-9201dbf8-9eb1-4bed-8d75-618c38969139
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1685900159 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_intr_test.1685900159
Directory /workspace/1.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_tl_errors.4017757793
Short name T754
Test name
Test status
Simulation time 197631632 ps
CPU time 2.62 seconds
Started Apr 21 12:37:43 PM PDT 24
Finished Apr 21 12:37:46 PM PDT 24
Peak memory 198244 kb
Host smart-ad673696-3e47-416c-b7e4-a840fb5beedc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4017757793 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_tl_errors.4017757793
Directory /workspace/1.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_tl_intg_err.108438361
Short name T833
Test name
Test status
Simulation time 280636532 ps
CPU time 1.47 seconds
Started Apr 21 12:37:56 PM PDT 24
Finished Apr 21 12:37:58 PM PDT 24
Peak memory 198076 kb
Host smart-a3d09d85-455c-4c99-9732-6891f1c954a1
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108438361 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 1.gpio_tl_intg_err.108438361
Directory /workspace/1.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_csr_mem_rw_with_rand_reset.709683899
Short name T736
Test name
Test status
Simulation time 33332419 ps
CPU time 0.86 seconds
Started Apr 21 12:38:03 PM PDT 24
Finished Apr 21 12:38:04 PM PDT 24
Peak memory 197932 kb
Host smart-6244f778-5cad-4ce4-8a61-c03acd44596e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=709683899 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_csr_mem_rw_with_rand_reset.709683899
Directory /workspace/10.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_csr_rw.2337069377
Short name T777
Test name
Test status
Simulation time 16015096 ps
CPU time 0.61 seconds
Started Apr 21 12:37:40 PM PDT 24
Finished Apr 21 12:37:41 PM PDT 24
Peak memory 194592 kb
Host smart-8f8c14a9-1f71-497d-9b3b-8cba41d284d9
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2337069377 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpi
o_csr_rw.2337069377
Directory /workspace/10.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_intr_test.3460050470
Short name T765
Test name
Test status
Simulation time 33277848 ps
CPU time 0.59 seconds
Started Apr 21 12:38:00 PM PDT 24
Finished Apr 21 12:38:01 PM PDT 24
Peak memory 193824 kb
Host smart-8e727ed6-728e-4d1a-96bb-dbd6bb122848
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3460050470 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_intr_test.3460050470
Directory /workspace/10.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_same_csr_outstanding.2176374868
Short name T134
Test name
Test status
Simulation time 314925841 ps
CPU time 0.96 seconds
Started Apr 21 12:37:51 PM PDT 24
Finished Apr 21 12:37:52 PM PDT 24
Peak memory 198108 kb
Host smart-2ab49c8e-ae7e-4696-9718-99e6f3edf5e4
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2176374868 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 10.gpio_same_csr_outstanding.2176374868
Directory /workspace/10.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_tl_errors.3474800238
Short name T842
Test name
Test status
Simulation time 132438725 ps
CPU time 1.9 seconds
Started Apr 21 12:37:49 PM PDT 24
Finished Apr 21 12:37:51 PM PDT 24
Peak memory 198144 kb
Host smart-df257e08-458f-4f52-a934-7383285ad73c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3474800238 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_tl_errors.3474800238
Directory /workspace/10.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_csr_mem_rw_with_rand_reset.584942302
Short name T789
Test name
Test status
Simulation time 84173123 ps
CPU time 0.75 seconds
Started Apr 21 12:37:44 PM PDT 24
Finished Apr 21 12:37:46 PM PDT 24
Peak memory 198060 kb
Host smart-ad4ba6fd-4b1b-4f84-84c4-e68075b32886
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=584942302 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_csr_mem_rw_with_rand_reset.584942302
Directory /workspace/11.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_csr_rw.1589534485
Short name T120
Test name
Test status
Simulation time 35387606 ps
CPU time 0.59 seconds
Started Apr 21 12:37:44 PM PDT 24
Finished Apr 21 12:37:45 PM PDT 24
Peak memory 194472 kb
Host smart-6e4f5ab8-b20c-461e-a07e-1560aa8bb6b5
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1589534485 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpi
o_csr_rw.1589534485
Directory /workspace/11.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_intr_test.2924004916
Short name T759
Test name
Test status
Simulation time 57259295 ps
CPU time 0.56 seconds
Started Apr 21 12:37:52 PM PDT 24
Finished Apr 21 12:37:53 PM PDT 24
Peak memory 193784 kb
Host smart-b6bec7c9-3cb7-4eb0-a022-25ce9b88fc8c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2924004916 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_intr_test.2924004916
Directory /workspace/11.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_same_csr_outstanding.3429778438
Short name T818
Test name
Test status
Simulation time 29384088 ps
CPU time 0.71 seconds
Started Apr 21 12:37:45 PM PDT 24
Finished Apr 21 12:37:47 PM PDT 24
Peak memory 194816 kb
Host smart-5a923e0c-277e-4a62-98f2-a95b16746934
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3429778438 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 11.gpio_same_csr_outstanding.3429778438
Directory /workspace/11.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_tl_errors.2967658375
Short name T840
Test name
Test status
Simulation time 601623815 ps
CPU time 2.67 seconds
Started Apr 21 12:37:57 PM PDT 24
Finished Apr 21 12:38:00 PM PDT 24
Peak memory 198024 kb
Host smart-9f1857ff-50e1-42fa-9f8d-741f7aae46b7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2967658375 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_tl_errors.2967658375
Directory /workspace/11.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_csr_mem_rw_with_rand_reset.1264181825
Short name T748
Test name
Test status
Simulation time 160660262 ps
CPU time 0.75 seconds
Started Apr 21 12:38:00 PM PDT 24
Finished Apr 21 12:38:01 PM PDT 24
Peak memory 198064 kb
Host smart-a0d1dfe3-136f-4059-97ed-5d5fac8e2b1a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1264181825 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_csr_mem_rw_with_rand_reset.1264181825
Directory /workspace/12.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_csr_rw.135503910
Short name T832
Test name
Test status
Simulation time 27434141 ps
CPU time 0.62 seconds
Started Apr 21 12:37:50 PM PDT 24
Finished Apr 21 12:37:51 PM PDT 24
Peak memory 194904 kb
Host smart-c3033a35-c24c-4eda-99f4-27f62a822e23
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=135503910 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio
_csr_rw.135503910
Directory /workspace/12.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_intr_test.180537329
Short name T805
Test name
Test status
Simulation time 96061634 ps
CPU time 0.62 seconds
Started Apr 21 12:37:58 PM PDT 24
Finished Apr 21 12:37:59 PM PDT 24
Peak memory 193872 kb
Host smart-5d1ca69c-9d8f-4d35-9ab6-ea898eb83704
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=180537329 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_intr_test.180537329
Directory /workspace/12.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_same_csr_outstanding.2399667281
Short name T130
Test name
Test status
Simulation time 17483683 ps
CPU time 0.71 seconds
Started Apr 21 12:37:44 PM PDT 24
Finished Apr 21 12:37:45 PM PDT 24
Peak memory 196112 kb
Host smart-0a24fdc9-4228-4669-9a08-64ffd917ff97
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2399667281 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 12.gpio_same_csr_outstanding.2399667281
Directory /workspace/12.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_tl_errors.234753139
Short name T779
Test name
Test status
Simulation time 193037573 ps
CPU time 1.15 seconds
Started Apr 21 12:37:55 PM PDT 24
Finished Apr 21 12:37:57 PM PDT 24
Peak memory 198204 kb
Host smart-dd10f56d-500a-4968-8706-424b4c58d10d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=234753139 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_tl_errors.234753139
Directory /workspace/12.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_tl_intg_err.1564895609
Short name T68
Test name
Test status
Simulation time 173539486 ps
CPU time 0.86 seconds
Started Apr 21 12:38:00 PM PDT 24
Finished Apr 21 12:38:01 PM PDT 24
Peak memory 197096 kb
Host smart-0cecbb74-5a39-4cbb-a455-a9fd07c79abc
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1564895609 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 12.gpio_tl_intg_err.1564895609
Directory /workspace/12.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_csr_mem_rw_with_rand_reset.1300322915
Short name T749
Test name
Test status
Simulation time 206467054 ps
CPU time 0.93 seconds
Started Apr 21 12:37:51 PM PDT 24
Finished Apr 21 12:37:52 PM PDT 24
Peak memory 198184 kb
Host smart-200645b1-099c-438b-87d8-cdd49a1371fa
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1300322915 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_csr_mem_rw_with_rand_reset.1300322915
Directory /workspace/13.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_csr_rw.398805655
Short name T792
Test name
Test status
Simulation time 16315605 ps
CPU time 0.6 seconds
Started Apr 21 12:37:46 PM PDT 24
Finished Apr 21 12:37:48 PM PDT 24
Peak memory 194924 kb
Host smart-7c1bcbe0-44d7-440b-ad85-6d956086c217
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=398805655 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio
_csr_rw.398805655
Directory /workspace/13.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_intr_test.3413606651
Short name T751
Test name
Test status
Simulation time 13496758 ps
CPU time 0.59 seconds
Started Apr 21 12:38:04 PM PDT 24
Finished Apr 21 12:38:05 PM PDT 24
Peak memory 194564 kb
Host smart-cad4f111-4142-445c-8e0a-59978fdcf499
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3413606651 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_intr_test.3413606651
Directory /workspace/13.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_same_csr_outstanding.531832536
Short name T133
Test name
Test status
Simulation time 108962003 ps
CPU time 0.74 seconds
Started Apr 21 12:37:48 PM PDT 24
Finished Apr 21 12:37:49 PM PDT 24
Peak memory 196088 kb
Host smart-95b83976-7f54-4f02-87ed-28fc55481cae
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=531832536 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 13.gpio_same_csr_outstanding.531832536
Directory /workspace/13.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_tl_errors.4210910054
Short name T823
Test name
Test status
Simulation time 43777294 ps
CPU time 1.17 seconds
Started Apr 21 12:37:41 PM PDT 24
Finished Apr 21 12:37:43 PM PDT 24
Peak memory 198000 kb
Host smart-c6f979e1-00e5-4780-b915-e4af8cb4bb74
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4210910054 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_tl_errors.4210910054
Directory /workspace/13.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_tl_intg_err.2999885507
Short name T827
Test name
Test status
Simulation time 90078640 ps
CPU time 0.88 seconds
Started Apr 21 12:38:14 PM PDT 24
Finished Apr 21 12:38:21 PM PDT 24
Peak memory 198064 kb
Host smart-42fa8421-e0a9-414f-bcc4-70cf76deb3c5
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2999885507 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 13.gpio_tl_intg_err.2999885507
Directory /workspace/13.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_csr_mem_rw_with_rand_reset.3255824343
Short name T730
Test name
Test status
Simulation time 431215012 ps
CPU time 0.81 seconds
Started Apr 21 12:38:07 PM PDT 24
Finished Apr 21 12:38:13 PM PDT 24
Peak memory 197708 kb
Host smart-7e0d8c25-cccf-4375-856f-8b0c4af3ca52
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3255824343 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_csr_mem_rw_with_rand_reset.3255824343
Directory /workspace/14.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_csr_rw.1218091269
Short name T105
Test name
Test status
Simulation time 37867024 ps
CPU time 0.55 seconds
Started Apr 21 12:37:59 PM PDT 24
Finished Apr 21 12:38:00 PM PDT 24
Peak memory 193836 kb
Host smart-0544cdc0-85e0-41c9-aeb8-b0624bf5509a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1218091269 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpi
o_csr_rw.1218091269
Directory /workspace/14.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_intr_test.4127969269
Short name T830
Test name
Test status
Simulation time 91461697 ps
CPU time 0.59 seconds
Started Apr 21 12:38:11 PM PDT 24
Finished Apr 21 12:38:17 PM PDT 24
Peak memory 194588 kb
Host smart-27209b3c-c395-47df-999c-fdd23e19e4bb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4127969269 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_intr_test.4127969269
Directory /workspace/14.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_same_csr_outstanding.807846121
Short name T803
Test name
Test status
Simulation time 138650215 ps
CPU time 0.77 seconds
Started Apr 21 12:38:20 PM PDT 24
Finished Apr 21 12:38:22 PM PDT 24
Peak memory 196072 kb
Host smart-ed6c3e2b-62ee-4c39-8479-428a4930fe55
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=807846121 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 14.gpio_same_csr_outstanding.807846121
Directory /workspace/14.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_tl_errors.3954336901
Short name T788
Test name
Test status
Simulation time 285305766 ps
CPU time 2.6 seconds
Started Apr 21 12:38:10 PM PDT 24
Finished Apr 21 12:38:13 PM PDT 24
Peak memory 198112 kb
Host smart-be2526a6-5355-478d-8747-184a6004a30f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3954336901 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_tl_errors.3954336901
Directory /workspace/14.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_tl_intg_err.3454103627
Short name T837
Test name
Test status
Simulation time 324480781 ps
CPU time 1.2 seconds
Started Apr 21 12:38:17 PM PDT 24
Finished Apr 21 12:38:19 PM PDT 24
Peak memory 198192 kb
Host smart-a2e8e379-7a69-41c2-a878-a2972e82aada
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3454103627 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 14.gpio_tl_intg_err.3454103627
Directory /workspace/14.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_csr_mem_rw_with_rand_reset.2777994351
Short name T781
Test name
Test status
Simulation time 16093549 ps
CPU time 0.75 seconds
Started Apr 21 12:37:49 PM PDT 24
Finished Apr 21 12:37:51 PM PDT 24
Peak memory 198124 kb
Host smart-90a4825a-3e41-4451-a2b7-f59999a769f0
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2777994351 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_csr_mem_rw_with_rand_reset.2777994351
Directory /workspace/15.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_csr_rw.3746624057
Short name T106
Test name
Test status
Simulation time 16841416 ps
CPU time 0.54 seconds
Started Apr 21 12:38:06 PM PDT 24
Finished Apr 21 12:38:07 PM PDT 24
Peak memory 193480 kb
Host smart-4765e208-85eb-4fc0-92ae-1f685d8254a7
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3746624057 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpi
o_csr_rw.3746624057
Directory /workspace/15.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_intr_test.3813606310
Short name T822
Test name
Test status
Simulation time 18148751 ps
CPU time 0.61 seconds
Started Apr 21 12:38:10 PM PDT 24
Finished Apr 21 12:38:11 PM PDT 24
Peak memory 193896 kb
Host smart-5c95667b-1919-4192-9a40-c5e9294b8021
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3813606310 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_intr_test.3813606310
Directory /workspace/15.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_same_csr_outstanding.2509909651
Short name T128
Test name
Test status
Simulation time 15989569 ps
CPU time 0.63 seconds
Started Apr 21 12:38:15 PM PDT 24
Finished Apr 21 12:38:17 PM PDT 24
Peak memory 194656 kb
Host smart-cb4816ab-a996-4a12-9297-38281b952cf8
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2509909651 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 15.gpio_same_csr_outstanding.2509909651
Directory /workspace/15.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_tl_errors.1493495426
Short name T828
Test name
Test status
Simulation time 326566959 ps
CPU time 1.9 seconds
Started Apr 21 12:38:11 PM PDT 24
Finished Apr 21 12:38:14 PM PDT 24
Peak memory 198168 kb
Host smart-9e0d6f7b-a83b-4168-b5f9-3e38f66b4974
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1493495426 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_tl_errors.1493495426
Directory /workspace/15.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_tl_intg_err.3822659787
Short name T835
Test name
Test status
Simulation time 298838632 ps
CPU time 1.2 seconds
Started Apr 21 12:37:56 PM PDT 24
Finished Apr 21 12:38:02 PM PDT 24
Peak memory 197724 kb
Host smart-06e1cbae-4e11-4ad1-88cf-1f31e80b635b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3822659787 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 15.gpio_tl_intg_err.3822659787
Directory /workspace/15.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_csr_mem_rw_with_rand_reset.2817068907
Short name T806
Test name
Test status
Simulation time 87313053 ps
CPU time 0.96 seconds
Started Apr 21 12:37:47 PM PDT 24
Finished Apr 21 12:37:48 PM PDT 24
Peak memory 197984 kb
Host smart-2c9ace2a-fdbc-4f7e-8517-15e4fb389801
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2817068907 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_csr_mem_rw_with_rand_reset.2817068907
Directory /workspace/16.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_csr_rw.3580907301
Short name T121
Test name
Test status
Simulation time 14833060 ps
CPU time 0.6 seconds
Started Apr 21 12:37:57 PM PDT 24
Finished Apr 21 12:37:58 PM PDT 24
Peak memory 195008 kb
Host smart-9daf1b05-0174-4f95-affa-3aa6dea1217d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3580907301 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpi
o_csr_rw.3580907301
Directory /workspace/16.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_intr_test.3116956814
Short name T723
Test name
Test status
Simulation time 17247988 ps
CPU time 0.56 seconds
Started Apr 21 12:38:04 PM PDT 24
Finished Apr 21 12:38:10 PM PDT 24
Peak memory 193880 kb
Host smart-14b9ca6e-803b-4333-ab73-bc264b3e3bcd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3116956814 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_intr_test.3116956814
Directory /workspace/16.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_same_csr_outstanding.3481403229
Short name T131
Test name
Test status
Simulation time 17704426 ps
CPU time 0.72 seconds
Started Apr 21 12:38:01 PM PDT 24
Finished Apr 21 12:38:02 PM PDT 24
Peak memory 195788 kb
Host smart-c0b21846-d9e2-45dc-8408-84093b537035
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3481403229 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 16.gpio_same_csr_outstanding.3481403229
Directory /workspace/16.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_tl_errors.1389883157
Short name T812
Test name
Test status
Simulation time 517153820 ps
CPU time 2.51 seconds
Started Apr 21 12:38:17 PM PDT 24
Finished Apr 21 12:38:30 PM PDT 24
Peak memory 198124 kb
Host smart-8a144fb2-a26f-41e4-9891-5e556b59ffd6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1389883157 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_tl_errors.1389883157
Directory /workspace/16.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_tl_intg_err.2216480629
Short name T56
Test name
Test status
Simulation time 88240345 ps
CPU time 0.89 seconds
Started Apr 21 12:38:15 PM PDT 24
Finished Apr 21 12:38:16 PM PDT 24
Peak memory 198000 kb
Host smart-25598001-af06-4dac-a491-8779c21a3501
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2216480629 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 16.gpio_tl_intg_err.2216480629
Directory /workspace/16.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_csr_mem_rw_with_rand_reset.205962777
Short name T787
Test name
Test status
Simulation time 40587280 ps
CPU time 1.33 seconds
Started Apr 21 12:37:55 PM PDT 24
Finished Apr 21 12:37:57 PM PDT 24
Peak memory 198272 kb
Host smart-5bbd23f0-d34a-4771-a555-a53490dc715e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=205962777 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_csr_mem_rw_with_rand_reset.205962777
Directory /workspace/17.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_csr_rw.4255133035
Short name T755
Test name
Test status
Simulation time 41139463 ps
CPU time 0.55 seconds
Started Apr 21 12:37:55 PM PDT 24
Finished Apr 21 12:37:56 PM PDT 24
Peak memory 193464 kb
Host smart-96f58607-3ca1-41fa-83bf-b8a68d1425ea
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4255133035 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpi
o_csr_rw.4255133035
Directory /workspace/17.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_intr_test.2475864657
Short name T761
Test name
Test status
Simulation time 14241098 ps
CPU time 0.58 seconds
Started Apr 21 12:38:07 PM PDT 24
Finished Apr 21 12:38:08 PM PDT 24
Peak memory 194368 kb
Host smart-37517a65-2fe7-4222-8abc-a444b5e77d9d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2475864657 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_intr_test.2475864657
Directory /workspace/17.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_same_csr_outstanding.2131576853
Short name T821
Test name
Test status
Simulation time 35856092 ps
CPU time 0.86 seconds
Started Apr 21 12:38:04 PM PDT 24
Finished Apr 21 12:38:05 PM PDT 24
Peak memory 197108 kb
Host smart-4f1d0a49-b6f6-453e-9966-e2a336658a33
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2131576853 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 17.gpio_same_csr_outstanding.2131576853
Directory /workspace/17.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_tl_errors.1366606731
Short name T775
Test name
Test status
Simulation time 107124373 ps
CPU time 1.45 seconds
Started Apr 21 12:37:46 PM PDT 24
Finished Apr 21 12:37:48 PM PDT 24
Peak memory 198080 kb
Host smart-93260b07-5bc3-41fb-b53e-d2397f0130fc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1366606731 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_tl_errors.1366606731
Directory /workspace/17.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_tl_intg_err.1804215218
Short name T70
Test name
Test status
Simulation time 51230348 ps
CPU time 0.92 seconds
Started Apr 21 12:37:43 PM PDT 24
Finished Apr 21 12:37:45 PM PDT 24
Peak memory 197284 kb
Host smart-eec86f5c-d0aa-4775-b1bd-61923aae7aec
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1804215218 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 17.gpio_tl_intg_err.1804215218
Directory /workspace/17.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_csr_mem_rw_with_rand_reset.3372687924
Short name T772
Test name
Test status
Simulation time 23149326 ps
CPU time 1.12 seconds
Started Apr 21 12:38:16 PM PDT 24
Finished Apr 21 12:38:18 PM PDT 24
Peak memory 198012 kb
Host smart-3482d0ad-eec6-4802-bf9d-1aabae0679a6
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3372687924 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_csr_mem_rw_with_rand_reset.3372687924
Directory /workspace/18.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_csr_rw.23085212
Short name T122
Test name
Test status
Simulation time 47046404 ps
CPU time 0.61 seconds
Started Apr 21 12:38:15 PM PDT 24
Finished Apr 21 12:38:16 PM PDT 24
Peak memory 195172 kb
Host smart-270e4ff9-9b64-4e86-80ad-ed5fd0dfa345
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23085212 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SE
Q=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_
csr_rw.23085212
Directory /workspace/18.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_intr_test.1921510530
Short name T757
Test name
Test status
Simulation time 13101439 ps
CPU time 0.59 seconds
Started Apr 21 12:38:02 PM PDT 24
Finished Apr 21 12:38:03 PM PDT 24
Peak memory 193948 kb
Host smart-94405fa7-dffd-477e-a508-bd51c72419dc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1921510530 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_intr_test.1921510530
Directory /workspace/18.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_same_csr_outstanding.2209435030
Short name T135
Test name
Test status
Simulation time 13858913 ps
CPU time 0.62 seconds
Started Apr 21 12:37:45 PM PDT 24
Finished Apr 21 12:37:46 PM PDT 24
Peak memory 194588 kb
Host smart-0e537c13-5e15-4da1-9a53-ec1fe490efce
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2209435030 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 18.gpio_same_csr_outstanding.2209435030
Directory /workspace/18.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_tl_errors.170222540
Short name T809
Test name
Test status
Simulation time 582440172 ps
CPU time 1.31 seconds
Started Apr 21 12:38:15 PM PDT 24
Finished Apr 21 12:38:17 PM PDT 24
Peak memory 198228 kb
Host smart-d7c840b9-bc27-453e-8400-b3f2d0251d9a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=170222540 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_tl_errors.170222540
Directory /workspace/18.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_tl_intg_err.3203558035
Short name T64
Test name
Test status
Simulation time 50004780 ps
CPU time 0.9 seconds
Started Apr 21 12:38:00 PM PDT 24
Finished Apr 21 12:38:02 PM PDT 24
Peak memory 197400 kb
Host smart-8b9c1cbc-e9f6-4068-aba8-e1c7bc1ade9c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3203558035 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 18.gpio_tl_intg_err.3203558035
Directory /workspace/18.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_csr_mem_rw_with_rand_reset.2575664837
Short name T741
Test name
Test status
Simulation time 75727026 ps
CPU time 1.1 seconds
Started Apr 21 12:38:02 PM PDT 24
Finished Apr 21 12:38:03 PM PDT 24
Peak memory 198300 kb
Host smart-c7a5740a-53a4-4941-ac34-175e7d0cba6e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2575664837 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_csr_mem_rw_with_rand_reset.2575664837
Directory /workspace/19.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_csr_rw.298505647
Short name T798
Test name
Test status
Simulation time 15733584 ps
CPU time 0.63 seconds
Started Apr 21 12:38:00 PM PDT 24
Finished Apr 21 12:38:06 PM PDT 24
Peak memory 195624 kb
Host smart-aaa040db-9cc8-4a42-95a3-ad82c49087b1
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=298505647 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio
_csr_rw.298505647
Directory /workspace/19.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_intr_test.793045819
Short name T722
Test name
Test status
Simulation time 12471857 ps
CPU time 0.6 seconds
Started Apr 21 12:38:12 PM PDT 24
Finished Apr 21 12:38:13 PM PDT 24
Peak memory 193956 kb
Host smart-0edd29df-4c87-4704-945d-5305f9d18063
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=793045819 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_intr_test.793045819
Directory /workspace/19.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_same_csr_outstanding.452804179
Short name T825
Test name
Test status
Simulation time 31567100 ps
CPU time 0.77 seconds
Started Apr 21 12:37:55 PM PDT 24
Finished Apr 21 12:37:56 PM PDT 24
Peak memory 196264 kb
Host smart-aa96fad0-45fc-48bc-9673-fb606cfaf553
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=452804179 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 19.gpio_same_csr_outstanding.452804179
Directory /workspace/19.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_tl_errors.42548034
Short name T760
Test name
Test status
Simulation time 16961777 ps
CPU time 0.89 seconds
Started Apr 21 12:38:11 PM PDT 24
Finished Apr 21 12:38:13 PM PDT 24
Peak memory 197952 kb
Host smart-e0c9d876-b094-4d4d-9a34-96b4d1182c8a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42548034 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_tl_errors.42548034
Directory /workspace/19.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_tl_intg_err.4134647025
Short name T65
Test name
Test status
Simulation time 297491772 ps
CPU time 1.16 seconds
Started Apr 21 12:38:12 PM PDT 24
Finished Apr 21 12:38:14 PM PDT 24
Peak memory 198296 kb
Host smart-b7883d16-ce68-403c-8cda-45fd5fcc0c0a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4134647025 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 19.gpio_tl_intg_err.4134647025
Directory /workspace/19.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_aliasing.729654761
Short name T729
Test name
Test status
Simulation time 125515907 ps
CPU time 0.68 seconds
Started Apr 21 12:37:36 PM PDT 24
Finished Apr 21 12:37:37 PM PDT 24
Peak memory 194784 kb
Host smart-3f40fa51-816b-4c89-ace7-26c3806e22a4
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=729654761 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2
.gpio_csr_aliasing.729654761
Directory /workspace/2.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_bit_bash.3856329902
Short name T138
Test name
Test status
Simulation time 35297471 ps
CPU time 1.33 seconds
Started Apr 21 12:37:56 PM PDT 24
Finished Apr 21 12:37:58 PM PDT 24
Peak memory 197048 kb
Host smart-7b6d0923-3cd4-4d55-9b37-12722c841c00
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3856329902 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_bit_bash.3856329902
Directory /workspace/2.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_hw_reset.227107434
Short name T137
Test name
Test status
Simulation time 13356941 ps
CPU time 0.62 seconds
Started Apr 21 12:37:51 PM PDT 24
Finished Apr 21 12:37:52 PM PDT 24
Peak memory 195544 kb
Host smart-bf97b4e4-fcd9-4cab-92ec-ef394ad3687b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=227107434 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_hw_reset.227107434
Directory /workspace/2.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_mem_rw_with_rand_reset.733136012
Short name T782
Test name
Test status
Simulation time 97496495 ps
CPU time 1.18 seconds
Started Apr 21 12:37:49 PM PDT 24
Finished Apr 21 12:37:51 PM PDT 24
Peak memory 197916 kb
Host smart-a8f492d1-26e6-4f46-a378-4cbcaa74b20a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=733136012 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_mem_rw_with_rand_reset.733136012
Directory /workspace/2.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_rw.2733134797
Short name T801
Test name
Test status
Simulation time 32515504 ps
CPU time 0.64 seconds
Started Apr 21 12:37:52 PM PDT 24
Finished Apr 21 12:37:53 PM PDT 24
Peak memory 195496 kb
Host smart-f0cc2261-8e05-4401-95ee-c016cdc4515f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2733134797 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio
_csr_rw.2733134797
Directory /workspace/2.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_intr_test.524643136
Short name T839
Test name
Test status
Simulation time 98054000 ps
CPU time 0.57 seconds
Started Apr 21 12:37:58 PM PDT 24
Finished Apr 21 12:37:59 PM PDT 24
Peak memory 193724 kb
Host smart-90c7445a-9ba2-4bc5-8bfc-0d115452aa07
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=524643136 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_intr_test.524643136
Directory /workspace/2.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_same_csr_outstanding.3642875432
Short name T810
Test name
Test status
Simulation time 57602646 ps
CPU time 0.75 seconds
Started Apr 21 12:37:46 PM PDT 24
Finished Apr 21 12:37:47 PM PDT 24
Peak memory 196380 kb
Host smart-e18379db-2604-483a-9322-9adf5670a2db
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3642875432 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 2.gpio_same_csr_outstanding.3642875432
Directory /workspace/2.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_tl_errors.3587122802
Short name T750
Test name
Test status
Simulation time 102104985 ps
CPU time 1.8 seconds
Started Apr 21 12:37:50 PM PDT 24
Finished Apr 21 12:37:52 PM PDT 24
Peak memory 198088 kb
Host smart-72893a58-cb68-455e-bbea-fabf2629a793
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3587122802 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_tl_errors.3587122802
Directory /workspace/2.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_tl_intg_err.3674764837
Short name T57
Test name
Test status
Simulation time 314211531 ps
CPU time 1.16 seconds
Started Apr 21 12:37:53 PM PDT 24
Finished Apr 21 12:37:55 PM PDT 24
Peak memory 198104 kb
Host smart-dcc1a9de-907f-4a02-bea8-c9d0be2fccce
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3674764837 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 2.gpio_tl_intg_err.3674764837
Directory /workspace/2.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.gpio_intr_test.2334580620
Short name T758
Test name
Test status
Simulation time 12076735 ps
CPU time 0.6 seconds
Started Apr 21 12:38:03 PM PDT 24
Finished Apr 21 12:38:04 PM PDT 24
Peak memory 193984 kb
Host smart-b089f641-cfe6-4344-bb6d-81e72321afe3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2334580620 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.gpio_intr_test.2334580620
Directory /workspace/20.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.gpio_intr_test.3780866017
Short name T742
Test name
Test status
Simulation time 43268680 ps
CPU time 0.6 seconds
Started Apr 21 12:38:18 PM PDT 24
Finished Apr 21 12:38:20 PM PDT 24
Peak memory 193848 kb
Host smart-43cc6d5f-6978-4c6e-80f6-9c25f55d5ece
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3780866017 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.gpio_intr_test.3780866017
Directory /workspace/21.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.gpio_intr_test.144750790
Short name T793
Test name
Test status
Simulation time 42472163 ps
CPU time 0.62 seconds
Started Apr 21 12:38:14 PM PDT 24
Finished Apr 21 12:38:15 PM PDT 24
Peak memory 193948 kb
Host smart-694e5f03-9ac1-4498-8f49-65e0b75c4434
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=144750790 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.gpio_intr_test.144750790
Directory /workspace/22.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.gpio_intr_test.1127847037
Short name T786
Test name
Test status
Simulation time 15184204 ps
CPU time 0.6 seconds
Started Apr 21 12:38:15 PM PDT 24
Finished Apr 21 12:38:17 PM PDT 24
Peak memory 194688 kb
Host smart-cb7b4cb3-c3a1-4ad2-8c81-d46c5277c26f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1127847037 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.gpio_intr_test.1127847037
Directory /workspace/23.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.gpio_intr_test.1501926503
Short name T771
Test name
Test status
Simulation time 23925180 ps
CPU time 0.6 seconds
Started Apr 21 12:38:11 PM PDT 24
Finished Apr 21 12:38:12 PM PDT 24
Peak memory 194376 kb
Host smart-81bcf302-c632-455d-8ab4-2e22ea08c656
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1501926503 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.gpio_intr_test.1501926503
Directory /workspace/24.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.gpio_intr_test.3386919642
Short name T726
Test name
Test status
Simulation time 53331594 ps
CPU time 0.6 seconds
Started Apr 21 12:38:13 PM PDT 24
Finished Apr 21 12:38:15 PM PDT 24
Peak memory 193912 kb
Host smart-6db4554b-5ff5-403f-8de2-b6b4d4efe836
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3386919642 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.gpio_intr_test.3386919642
Directory /workspace/25.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.gpio_intr_test.2564638954
Short name T834
Test name
Test status
Simulation time 39580132 ps
CPU time 0.58 seconds
Started Apr 21 12:38:02 PM PDT 24
Finished Apr 21 12:38:04 PM PDT 24
Peak memory 193920 kb
Host smart-19ce39c9-59df-425a-836f-17782b8aa4c0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2564638954 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.gpio_intr_test.2564638954
Directory /workspace/26.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.gpio_intr_test.334384383
Short name T764
Test name
Test status
Simulation time 45682143 ps
CPU time 0.6 seconds
Started Apr 21 12:37:55 PM PDT 24
Finished Apr 21 12:37:56 PM PDT 24
Peak memory 193900 kb
Host smart-24466410-0722-439a-8843-33db497ba624
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=334384383 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.gpio_intr_test.334384383
Directory /workspace/27.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.gpio_intr_test.3693660382
Short name T732
Test name
Test status
Simulation time 25417087 ps
CPU time 0.56 seconds
Started Apr 21 12:38:07 PM PDT 24
Finished Apr 21 12:38:08 PM PDT 24
Peak memory 193920 kb
Host smart-75c85a41-13c1-444c-934b-2695c6fdef9c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3693660382 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.gpio_intr_test.3693660382
Directory /workspace/28.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.gpio_intr_test.4227175019
Short name T734
Test name
Test status
Simulation time 38108476 ps
CPU time 0.64 seconds
Started Apr 21 12:38:31 PM PDT 24
Finished Apr 21 12:38:33 PM PDT 24
Peak memory 194428 kb
Host smart-7d2dcac0-4613-4e54-8c49-866ac2470bc9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4227175019 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.gpio_intr_test.4227175019
Directory /workspace/29.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_aliasing.2826684371
Short name T815
Test name
Test status
Simulation time 19763283 ps
CPU time 0.82 seconds
Started Apr 21 12:37:46 PM PDT 24
Finished Apr 21 12:37:48 PM PDT 24
Peak memory 196244 kb
Host smart-6ab73b50-9e88-40c7-ac61-fdf0a60575d1
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2826684371 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
3.gpio_csr_aliasing.2826684371
Directory /workspace/3.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_bit_bash.2646056048
Short name T731
Test name
Test status
Simulation time 1547263099 ps
CPU time 3.41 seconds
Started Apr 21 12:37:42 PM PDT 24
Finished Apr 21 12:37:46 PM PDT 24
Peak memory 196856 kb
Host smart-8e466efa-0a6a-4fcf-aea0-7dbd86f37ec9
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2646056048 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_bit_bash.2646056048
Directory /workspace/3.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_hw_reset.1977801646
Short name T791
Test name
Test status
Simulation time 15302082 ps
CPU time 0.6 seconds
Started Apr 21 12:37:53 PM PDT 24
Finished Apr 21 12:37:54 PM PDT 24
Peak memory 194428 kb
Host smart-2f88de25-0cd6-4782-b426-b381b23c898a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1977801646 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_hw_reset.1977801646
Directory /workspace/3.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_mem_rw_with_rand_reset.2915603348
Short name T721
Test name
Test status
Simulation time 136108101 ps
CPU time 1.04 seconds
Started Apr 21 12:37:45 PM PDT 24
Finished Apr 21 12:37:47 PM PDT 24
Peak memory 198104 kb
Host smart-e7052a50-4eac-495f-82c1-ae5ef6ff8f7b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2915603348 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_mem_rw_with_rand_reset.2915603348
Directory /workspace/3.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_rw.3614926427
Short name T756
Test name
Test status
Simulation time 14415098 ps
CPU time 0.59 seconds
Started Apr 21 12:37:45 PM PDT 24
Finished Apr 21 12:37:46 PM PDT 24
Peak memory 194496 kb
Host smart-50355cb0-9995-4aed-8fa2-bb2084fa1cb6
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3614926427 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio
_csr_rw.3614926427
Directory /workspace/3.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_intr_test.1804863953
Short name T838
Test name
Test status
Simulation time 12496540 ps
CPU time 0.55 seconds
Started Apr 21 12:37:54 PM PDT 24
Finished Apr 21 12:37:55 PM PDT 24
Peak memory 193924 kb
Host smart-b7d425cd-16e3-4ce3-b46b-808888067c4a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1804863953 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_intr_test.1804863953
Directory /workspace/3.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_same_csr_outstanding.3291313283
Short name T819
Test name
Test status
Simulation time 216954176 ps
CPU time 0.9 seconds
Started Apr 21 12:37:53 PM PDT 24
Finished Apr 21 12:37:54 PM PDT 24
Peak memory 197240 kb
Host smart-130723bf-e495-40f0-9aea-7a70a56fc615
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3291313283 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 3.gpio_same_csr_outstanding.3291313283
Directory /workspace/3.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_tl_errors.1193694471
Short name T767
Test name
Test status
Simulation time 162965313 ps
CPU time 2.11 seconds
Started Apr 21 12:37:34 PM PDT 24
Finished Apr 21 12:37:36 PM PDT 24
Peak memory 198176 kb
Host smart-3c7b2562-b406-4709-865a-9b26b28b5cc5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1193694471 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_tl_errors.1193694471
Directory /workspace/3.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_tl_intg_err.3353056151
Short name T55
Test name
Test status
Simulation time 86123728 ps
CPU time 0.9 seconds
Started Apr 21 12:38:01 PM PDT 24
Finished Apr 21 12:38:03 PM PDT 24
Peak memory 197868 kb
Host smart-b2688fae-004d-4016-814d-814b2314cc9c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3353056151 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 3.gpio_tl_intg_err.3353056151
Directory /workspace/3.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.gpio_intr_test.1597223071
Short name T727
Test name
Test status
Simulation time 73203905 ps
CPU time 0.61 seconds
Started Apr 21 12:38:02 PM PDT 24
Finished Apr 21 12:38:04 PM PDT 24
Peak memory 194612 kb
Host smart-5bc55d3e-813d-4e5e-aedf-242da81ccbf8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1597223071 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.gpio_intr_test.1597223071
Directory /workspace/30.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.gpio_intr_test.2704618274
Short name T813
Test name
Test status
Simulation time 33178356 ps
CPU time 0.55 seconds
Started Apr 21 12:38:02 PM PDT 24
Finished Apr 21 12:38:04 PM PDT 24
Peak memory 193656 kb
Host smart-d15c7168-0e7a-4888-a45c-075a2ff1d0de
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2704618274 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.gpio_intr_test.2704618274
Directory /workspace/31.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.gpio_intr_test.2971795380
Short name T796
Test name
Test status
Simulation time 94972076 ps
CPU time 0.58 seconds
Started Apr 21 12:38:18 PM PDT 24
Finished Apr 21 12:38:19 PM PDT 24
Peak memory 193868 kb
Host smart-ca63ca34-45a0-439f-aaed-906487d7e351
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2971795380 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.gpio_intr_test.2971795380
Directory /workspace/32.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.gpio_intr_test.3920017381
Short name T762
Test name
Test status
Simulation time 36282479 ps
CPU time 0.57 seconds
Started Apr 21 12:37:49 PM PDT 24
Finished Apr 21 12:37:50 PM PDT 24
Peak memory 193908 kb
Host smart-e98bc02c-71ff-45b3-9b41-21a341a63d4a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3920017381 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.gpio_intr_test.3920017381
Directory /workspace/33.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.gpio_intr_test.849752886
Short name T784
Test name
Test status
Simulation time 51316460 ps
CPU time 0.63 seconds
Started Apr 21 12:38:13 PM PDT 24
Finished Apr 21 12:38:14 PM PDT 24
Peak memory 193860 kb
Host smart-18756c25-b358-4b82-a3aa-cfae4948befd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=849752886 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.gpio_intr_test.849752886
Directory /workspace/34.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.gpio_intr_test.1476159992
Short name T811
Test name
Test status
Simulation time 15177911 ps
CPU time 0.57 seconds
Started Apr 21 12:38:17 PM PDT 24
Finished Apr 21 12:38:18 PM PDT 24
Peak memory 194424 kb
Host smart-201cd5da-83df-4ac2-ae69-673f685001d5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1476159992 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.gpio_intr_test.1476159992
Directory /workspace/35.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.gpio_intr_test.3927444559
Short name T747
Test name
Test status
Simulation time 17958034 ps
CPU time 0.6 seconds
Started Apr 21 12:38:10 PM PDT 24
Finished Apr 21 12:38:11 PM PDT 24
Peak memory 193808 kb
Host smart-b306f811-bff5-4a9c-b62f-996546ea86ba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3927444559 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.gpio_intr_test.3927444559
Directory /workspace/36.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.gpio_intr_test.849688231
Short name T768
Test name
Test status
Simulation time 33896307 ps
CPU time 0.61 seconds
Started Apr 21 12:38:18 PM PDT 24
Finished Apr 21 12:38:19 PM PDT 24
Peak memory 193852 kb
Host smart-a2de0be7-d41f-4186-890f-ac3ee04c032f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=849688231 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.gpio_intr_test.849688231
Directory /workspace/37.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.gpio_intr_test.438932638
Short name T778
Test name
Test status
Simulation time 83280148 ps
CPU time 0.59 seconds
Started Apr 21 12:38:08 PM PDT 24
Finished Apr 21 12:38:09 PM PDT 24
Peak memory 193908 kb
Host smart-7bf85b04-0402-44f1-8f62-d3ff48dbb710
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=438932638 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.gpio_intr_test.438932638
Directory /workspace/38.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.gpio_intr_test.1702684720
Short name T802
Test name
Test status
Simulation time 41799543 ps
CPU time 0.56 seconds
Started Apr 21 12:37:54 PM PDT 24
Finished Apr 21 12:37:55 PM PDT 24
Peak memory 193852 kb
Host smart-15f8d666-9cdf-43f3-af55-7b1dbc2b3a11
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1702684720 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.gpio_intr_test.1702684720
Directory /workspace/39.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_aliasing.232682808
Short name T123
Test name
Test status
Simulation time 91958121 ps
CPU time 0.75 seconds
Started Apr 21 12:37:44 PM PDT 24
Finished Apr 21 12:37:45 PM PDT 24
Peak memory 195508 kb
Host smart-0b18677e-8ba5-4482-9c67-cebaf7668652
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=232682808 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4
.gpio_csr_aliasing.232682808
Directory /workspace/4.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_bit_bash.4147550270
Short name T829
Test name
Test status
Simulation time 394647513 ps
CPU time 3.07 seconds
Started Apr 21 12:37:51 PM PDT 24
Finished Apr 21 12:37:55 PM PDT 24
Peak memory 197252 kb
Host smart-7b103df8-235d-4315-a5a5-1a565fd352cb
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4147550270 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_bit_bash.4147550270
Directory /workspace/4.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_hw_reset.1069066901
Short name T101
Test name
Test status
Simulation time 15735067 ps
CPU time 0.58 seconds
Started Apr 21 12:37:46 PM PDT 24
Finished Apr 21 12:37:47 PM PDT 24
Peak memory 194560 kb
Host smart-0e35c4bb-3fbd-45be-9a24-6826def158dc
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1069066901 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_hw_reset.1069066901
Directory /workspace/4.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_mem_rw_with_rand_reset.3718441620
Short name T737
Test name
Test status
Simulation time 31405730 ps
CPU time 0.9 seconds
Started Apr 21 12:37:38 PM PDT 24
Finished Apr 21 12:37:39 PM PDT 24
Peak memory 198132 kb
Host smart-ad035cca-5df9-4233-81de-d1365d124d18
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3718441620 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_mem_rw_with_rand_reset.3718441620
Directory /workspace/4.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_rw.1744092392
Short name T119
Test name
Test status
Simulation time 43332420 ps
CPU time 0.6 seconds
Started Apr 21 12:37:43 PM PDT 24
Finished Apr 21 12:37:44 PM PDT 24
Peak memory 194904 kb
Host smart-c2c59893-ddb9-4a5f-b5b3-1d371adf2051
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1744092392 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio
_csr_rw.1744092392
Directory /workspace/4.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_intr_test.2652618680
Short name T744
Test name
Test status
Simulation time 21116877 ps
CPU time 0.59 seconds
Started Apr 21 12:37:51 PM PDT 24
Finished Apr 21 12:37:52 PM PDT 24
Peak memory 193840 kb
Host smart-a7a023ff-e1d8-413a-ba43-72021dfce083
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2652618680 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_intr_test.2652618680
Directory /workspace/4.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_same_csr_outstanding.1264505621
Short name T824
Test name
Test status
Simulation time 21219275 ps
CPU time 0.8 seconds
Started Apr 21 12:37:53 PM PDT 24
Finished Apr 21 12:37:54 PM PDT 24
Peak memory 196524 kb
Host smart-270e2b5a-ecb9-4ebb-b1ec-0956fe833ad1
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1264505621 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 4.gpio_same_csr_outstanding.1264505621
Directory /workspace/4.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_tl_errors.1017666636
Short name T799
Test name
Test status
Simulation time 42249456 ps
CPU time 2.04 seconds
Started Apr 21 12:37:59 PM PDT 24
Finished Apr 21 12:38:01 PM PDT 24
Peak memory 198128 kb
Host smart-b3d6b460-ece3-4ac8-ad35-98d916564be7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1017666636 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_tl_errors.1017666636
Directory /workspace/4.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_tl_intg_err.1002409577
Short name T752
Test name
Test status
Simulation time 665792831 ps
CPU time 0.89 seconds
Started Apr 21 12:37:37 PM PDT 24
Finished Apr 21 12:37:38 PM PDT 24
Peak memory 197348 kb
Host smart-dc6c6679-54e5-466c-afaa-f6580890cee5
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1002409577 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 4.gpio_tl_intg_err.1002409577
Directory /workspace/4.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.gpio_intr_test.4092526105
Short name T770
Test name
Test status
Simulation time 41892824 ps
CPU time 0.59 seconds
Started Apr 21 12:38:13 PM PDT 24
Finished Apr 21 12:38:15 PM PDT 24
Peak memory 194656 kb
Host smart-b337a277-98e5-4455-8182-cb03557e494d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4092526105 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.gpio_intr_test.4092526105
Directory /workspace/40.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.gpio_intr_test.2650643799
Short name T740
Test name
Test status
Simulation time 18274122 ps
CPU time 0.61 seconds
Started Apr 21 12:37:54 PM PDT 24
Finished Apr 21 12:37:55 PM PDT 24
Peak memory 193948 kb
Host smart-feb11839-34ed-49d1-8d7f-db89a412307d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2650643799 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.gpio_intr_test.2650643799
Directory /workspace/41.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.gpio_intr_test.3356058539
Short name T826
Test name
Test status
Simulation time 16470437 ps
CPU time 0.6 seconds
Started Apr 21 12:37:49 PM PDT 24
Finished Apr 21 12:37:50 PM PDT 24
Peak memory 193860 kb
Host smart-68b76feb-3aa1-48d8-8862-3b55ca2caac2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3356058539 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.gpio_intr_test.3356058539
Directory /workspace/42.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.gpio_intr_test.1446007114
Short name T735
Test name
Test status
Simulation time 14590513 ps
CPU time 0.6 seconds
Started Apr 21 12:37:44 PM PDT 24
Finished Apr 21 12:37:45 PM PDT 24
Peak memory 194480 kb
Host smart-8c5a155d-0a1c-480e-a353-33c6ab988ff5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1446007114 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.gpio_intr_test.1446007114
Directory /workspace/43.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.gpio_intr_test.879466937
Short name T774
Test name
Test status
Simulation time 10995377 ps
CPU time 0.69 seconds
Started Apr 21 12:38:08 PM PDT 24
Finished Apr 21 12:38:09 PM PDT 24
Peak memory 194516 kb
Host smart-5d3c3b71-c750-4fd5-96e0-fe920768f47e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=879466937 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.gpio_intr_test.879466937
Directory /workspace/44.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.gpio_intr_test.3086178551
Short name T814
Test name
Test status
Simulation time 24446949 ps
CPU time 0.58 seconds
Started Apr 21 12:37:54 PM PDT 24
Finished Apr 21 12:37:55 PM PDT 24
Peak memory 193720 kb
Host smart-76e1e953-4621-4b56-86c2-e81fc11e0f96
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3086178551 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.gpio_intr_test.3086178551
Directory /workspace/45.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.gpio_intr_test.2885599934
Short name T746
Test name
Test status
Simulation time 41703842 ps
CPU time 0.57 seconds
Started Apr 21 12:38:13 PM PDT 24
Finished Apr 21 12:38:14 PM PDT 24
Peak memory 194488 kb
Host smart-71f520b1-367f-4faf-98f9-c126019aafca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2885599934 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.gpio_intr_test.2885599934
Directory /workspace/46.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.gpio_intr_test.174122130
Short name T790
Test name
Test status
Simulation time 13536671 ps
CPU time 0.58 seconds
Started Apr 21 12:38:49 PM PDT 24
Finished Apr 21 12:38:51 PM PDT 24
Peak memory 193724 kb
Host smart-94fe0f2f-08b6-44f7-b7a1-5a0c3bcdc4d2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=174122130 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.gpio_intr_test.174122130
Directory /workspace/47.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.gpio_intr_test.804562254
Short name T739
Test name
Test status
Simulation time 53442762 ps
CPU time 0.56 seconds
Started Apr 21 12:38:21 PM PDT 24
Finished Apr 21 12:38:22 PM PDT 24
Peak memory 193828 kb
Host smart-346c791a-fcc2-474f-ae19-f59113c61274
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=804562254 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.gpio_intr_test.804562254
Directory /workspace/48.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.gpio_intr_test.2057839456
Short name T753
Test name
Test status
Simulation time 23893099 ps
CPU time 0.57 seconds
Started Apr 21 12:38:06 PM PDT 24
Finished Apr 21 12:38:07 PM PDT 24
Peak memory 193772 kb
Host smart-44fb4775-394b-4c7a-b118-fff7d3a5157b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2057839456 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.gpio_intr_test.2057839456
Directory /workspace/49.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_csr_mem_rw_with_rand_reset.2310388797
Short name T763
Test name
Test status
Simulation time 75000423 ps
CPU time 0.81 seconds
Started Apr 21 12:37:45 PM PDT 24
Finished Apr 21 12:37:46 PM PDT 24
Peak memory 198188 kb
Host smart-a738fae0-63d5-483d-92e5-1af499b74fc0
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2310388797 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_csr_mem_rw_with_rand_reset.2310388797
Directory /workspace/5.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_csr_rw.4194926152
Short name T107
Test name
Test status
Simulation time 87466568 ps
CPU time 0.64 seconds
Started Apr 21 12:37:45 PM PDT 24
Finished Apr 21 12:37:46 PM PDT 24
Peak memory 195676 kb
Host smart-31be3e64-ef6b-4e76-84c9-1d27810b10af
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4194926152 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio
_csr_rw.4194926152
Directory /workspace/5.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_intr_test.2520806349
Short name T795
Test name
Test status
Simulation time 15656360 ps
CPU time 0.58 seconds
Started Apr 21 12:37:51 PM PDT 24
Finished Apr 21 12:37:52 PM PDT 24
Peak memory 193768 kb
Host smart-46e5747d-608c-4180-85e6-4a062e2c4675
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2520806349 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_intr_test.2520806349
Directory /workspace/5.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_same_csr_outstanding.1970651675
Short name T102
Test name
Test status
Simulation time 52181420 ps
CPU time 0.87 seconds
Started Apr 21 12:37:51 PM PDT 24
Finished Apr 21 12:37:52 PM PDT 24
Peak memory 196344 kb
Host smart-f8626886-6718-42da-955b-3c63d1cef2e3
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1970651675 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 5.gpio_same_csr_outstanding.1970651675
Directory /workspace/5.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_tl_errors.3589275894
Short name T820
Test name
Test status
Simulation time 65494865 ps
CPU time 1.12 seconds
Started Apr 21 12:37:49 PM PDT 24
Finished Apr 21 12:37:51 PM PDT 24
Peak memory 198128 kb
Host smart-5f806d92-5190-4aad-badb-f26feb3d92b6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3589275894 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_tl_errors.3589275894
Directory /workspace/5.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_tl_intg_err.3961084844
Short name T54
Test name
Test status
Simulation time 51997449 ps
CPU time 0.89 seconds
Started Apr 21 12:37:46 PM PDT 24
Finished Apr 21 12:37:47 PM PDT 24
Peak memory 197948 kb
Host smart-7edb9db5-6b24-4ecf-a6f7-12ce4fc36d1d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3961084844 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 5.gpio_tl_intg_err.3961084844
Directory /workspace/5.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_csr_mem_rw_with_rand_reset.1356932415
Short name T769
Test name
Test status
Simulation time 27252231 ps
CPU time 1.26 seconds
Started Apr 21 12:37:55 PM PDT 24
Finished Apr 21 12:37:57 PM PDT 24
Peak memory 198360 kb
Host smart-06b49eef-26a2-4026-828d-6281a2000403
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1356932415 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_csr_mem_rw_with_rand_reset.1356932415
Directory /workspace/6.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_csr_rw.233820259
Short name T126
Test name
Test status
Simulation time 19784018 ps
CPU time 0.63 seconds
Started Apr 21 12:38:05 PM PDT 24
Finished Apr 21 12:38:06 PM PDT 24
Peak memory 195156 kb
Host smart-cce5c684-c15a-4e62-ae49-dd7caa9a8775
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=233820259 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_
csr_rw.233820259
Directory /workspace/6.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_intr_test.852622700
Short name T800
Test name
Test status
Simulation time 31649626 ps
CPU time 0.6 seconds
Started Apr 21 12:37:39 PM PDT 24
Finished Apr 21 12:37:40 PM PDT 24
Peak memory 193924 kb
Host smart-f6f75f57-9c02-47a9-8831-2e939ad00859
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=852622700 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_intr_test.852622700
Directory /workspace/6.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_same_csr_outstanding.512530831
Short name T780
Test name
Test status
Simulation time 48728223 ps
CPU time 0.71 seconds
Started Apr 21 12:37:40 PM PDT 24
Finished Apr 21 12:37:41 PM PDT 24
Peak memory 195484 kb
Host smart-00362c8d-b72a-4f89-b054-a06999cbbf92
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=512530831 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 6.gpio_same_csr_outstanding.512530831
Directory /workspace/6.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_tl_errors.2499973331
Short name T745
Test name
Test status
Simulation time 71757113 ps
CPU time 1.69 seconds
Started Apr 21 12:37:49 PM PDT 24
Finished Apr 21 12:37:51 PM PDT 24
Peak memory 198024 kb
Host smart-50f0e789-b3fd-496c-a1a9-c1f3dfe58943
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2499973331 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_tl_errors.2499973331
Directory /workspace/6.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_tl_intg_err.3280542365
Short name T841
Test name
Test status
Simulation time 185723877 ps
CPU time 0.83 seconds
Started Apr 21 12:37:52 PM PDT 24
Finished Apr 21 12:37:54 PM PDT 24
Peak memory 197464 kb
Host smart-683204b6-241f-4855-b064-082808ce14a9
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3280542365 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 6.gpio_tl_intg_err.3280542365
Directory /workspace/6.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_csr_mem_rw_with_rand_reset.4086466637
Short name T728
Test name
Test status
Simulation time 45782590 ps
CPU time 1.21 seconds
Started Apr 21 12:37:43 PM PDT 24
Finished Apr 21 12:37:44 PM PDT 24
Peak memory 198144 kb
Host smart-65721454-22f0-4d40-baf3-ee3ed0f19c96
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4086466637 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_csr_mem_rw_with_rand_reset.4086466637
Directory /workspace/7.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_csr_rw.261103870
Short name T773
Test name
Test status
Simulation time 45439700 ps
CPU time 0.57 seconds
Started Apr 21 12:37:58 PM PDT 24
Finished Apr 21 12:37:59 PM PDT 24
Peak memory 194728 kb
Host smart-64d951ce-ffea-4e96-ba8b-dac2e599a6fb
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=261103870 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_
csr_rw.261103870
Directory /workspace/7.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_intr_test.4183722448
Short name T816
Test name
Test status
Simulation time 11828314 ps
CPU time 0.58 seconds
Started Apr 21 12:37:56 PM PDT 24
Finished Apr 21 12:37:57 PM PDT 24
Peak memory 193852 kb
Host smart-7cb34c8a-d9a3-4dfe-b604-95326cb9ca57
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4183722448 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_intr_test.4183722448
Directory /workspace/7.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_same_csr_outstanding.302046791
Short name T108
Test name
Test status
Simulation time 90447553 ps
CPU time 0.65 seconds
Started Apr 21 12:38:05 PM PDT 24
Finished Apr 21 12:38:12 PM PDT 24
Peak memory 195464 kb
Host smart-264182d6-ed88-4236-aae4-41963ddb0e05
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=302046791 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 7.gpio_same_csr_outstanding.302046791
Directory /workspace/7.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_tl_errors.4289241471
Short name T733
Test name
Test status
Simulation time 108863819 ps
CPU time 1.49 seconds
Started Apr 21 12:37:52 PM PDT 24
Finished Apr 21 12:37:59 PM PDT 24
Peak memory 198256 kb
Host smart-37ed58a4-5a7f-4c95-8697-d014c03566bd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4289241471 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_tl_errors.4289241471
Directory /workspace/7.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_tl_intg_err.2490958512
Short name T69
Test name
Test status
Simulation time 120469709 ps
CPU time 1.41 seconds
Started Apr 21 12:37:37 PM PDT 24
Finished Apr 21 12:37:39 PM PDT 24
Peak memory 197756 kb
Host smart-b5b53d0d-8b13-4159-a310-8f46a9b45c2a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2490958512 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 7.gpio_tl_intg_err.2490958512
Directory /workspace/7.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_csr_mem_rw_with_rand_reset.3761691338
Short name T725
Test name
Test status
Simulation time 17408862 ps
CPU time 0.76 seconds
Started Apr 21 12:37:56 PM PDT 24
Finished Apr 21 12:37:57 PM PDT 24
Peak memory 197976 kb
Host smart-2adc81ce-e4ce-4e76-adac-2c503071cb84
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3761691338 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_csr_mem_rw_with_rand_reset.3761691338
Directory /workspace/8.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_csr_rw.3814084125
Short name T127
Test name
Test status
Simulation time 19103436 ps
CPU time 0.57 seconds
Started Apr 21 12:38:09 PM PDT 24
Finished Apr 21 12:38:15 PM PDT 24
Peak memory 194116 kb
Host smart-651aaaca-5ba6-4b79-94eb-7861850f4460
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3814084125 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio
_csr_rw.3814084125
Directory /workspace/8.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_intr_test.884225138
Short name T724
Test name
Test status
Simulation time 64996945 ps
CPU time 0.6 seconds
Started Apr 21 12:37:48 PM PDT 24
Finished Apr 21 12:37:49 PM PDT 24
Peak memory 193832 kb
Host smart-cb432f34-e736-4065-a074-6b9d2867ad9d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=884225138 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_intr_test.884225138
Directory /workspace/8.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_same_csr_outstanding.2572415031
Short name T132
Test name
Test status
Simulation time 25350326 ps
CPU time 0.73 seconds
Started Apr 21 12:37:43 PM PDT 24
Finished Apr 21 12:37:44 PM PDT 24
Peak memory 196384 kb
Host smart-0e1a9caa-edef-487a-b354-ad98d06f9360
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2572415031 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 8.gpio_same_csr_outstanding.2572415031
Directory /workspace/8.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_tl_errors.3437531405
Short name T817
Test name
Test status
Simulation time 46626017 ps
CPU time 1.28 seconds
Started Apr 21 12:37:41 PM PDT 24
Finished Apr 21 12:37:43 PM PDT 24
Peak memory 198204 kb
Host smart-6bdf04df-80b2-49b0-b530-c1ede9a6f52b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3437531405 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_tl_errors.3437531405
Directory /workspace/8.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_tl_intg_err.781447243
Short name T140
Test name
Test status
Simulation time 50787175 ps
CPU time 0.92 seconds
Started Apr 21 12:37:52 PM PDT 24
Finished Apr 21 12:37:53 PM PDT 24
Peak memory 198048 kb
Host smart-3b326743-8886-438c-b881-1d8648154f10
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=781447243 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 8.gpio_tl_intg_err.781447243
Directory /workspace/8.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_csr_mem_rw_with_rand_reset.2984844506
Short name T720
Test name
Test status
Simulation time 30466301 ps
CPU time 0.87 seconds
Started Apr 21 12:38:02 PM PDT 24
Finished Apr 21 12:38:04 PM PDT 24
Peak memory 197960 kb
Host smart-a01ee0b7-8b3a-4152-b5b8-e34d0b0feae6
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2984844506 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_csr_mem_rw_with_rand_reset.2984844506
Directory /workspace/9.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_csr_rw.2842813979
Short name T118
Test name
Test status
Simulation time 23917831 ps
CPU time 0.6 seconds
Started Apr 21 12:37:41 PM PDT 24
Finished Apr 21 12:37:42 PM PDT 24
Peak memory 195820 kb
Host smart-0cd2af93-cbf1-4f1c-9e80-906b6a671737
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2842813979 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio
_csr_rw.2842813979
Directory /workspace/9.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_intr_test.3596084113
Short name T797
Test name
Test status
Simulation time 26678217 ps
CPU time 0.64 seconds
Started Apr 21 12:38:05 PM PDT 24
Finished Apr 21 12:38:07 PM PDT 24
Peak memory 194676 kb
Host smart-a69d98fa-2650-489a-a2f1-f295cd244fb9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3596084113 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_intr_test.3596084113
Directory /workspace/9.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_same_csr_outstanding.1245755473
Short name T807
Test name
Test status
Simulation time 56160740 ps
CPU time 0.82 seconds
Started Apr 21 12:38:00 PM PDT 24
Finished Apr 21 12:38:02 PM PDT 24
Peak memory 196472 kb
Host smart-3b2ade88-8450-4843-87d5-0a3197ec0fce
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1245755473 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 9.gpio_same_csr_outstanding.1245755473
Directory /workspace/9.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_tl_errors.2037362448
Short name T783
Test name
Test status
Simulation time 292453577 ps
CPU time 2.98 seconds
Started Apr 21 12:37:49 PM PDT 24
Finished Apr 21 12:37:53 PM PDT 24
Peak memory 198188 kb
Host smart-dea8a1c8-4979-47e3-85f8-dc429c8152d4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2037362448 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_tl_errors.2037362448
Directory /workspace/9.gpio_tl_errors/latest

Test location /workspace/coverage/default/0.gpio_alert_test.2870351633
Short name T542
Test name
Test status
Simulation time 12330912 ps
CPU time 0.56 seconds
Started Apr 21 12:45:47 PM PDT 24
Finished Apr 21 12:45:48 PM PDT 24
Peak memory 194980 kb
Host smart-1bfe2b33-c876-40e4-a409-bea2b266cf8f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2870351633 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_alert_test.2870351633
Directory /workspace/0.gpio_alert_test/latest

Test location /workspace/coverage/default/0.gpio_dout_din_regs_random_rw.560395070
Short name T178
Test name
Test status
Simulation time 382479495 ps
CPU time 0.96 seconds
Started Apr 21 12:45:49 PM PDT 24
Finished Apr 21 12:45:50 PM PDT 24
Peak memory 195940 kb
Host smart-016236af-75ef-46cd-b09d-a69c5ac1233a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=560395070 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_dout_din_regs_random_rw.560395070
Directory /workspace/0.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/0.gpio_filter_stress.1979438139
Short name T477
Test name
Test status
Simulation time 3291726591 ps
CPU time 26.27 seconds
Started Apr 21 12:45:53 PM PDT 24
Finished Apr 21 12:46:20 PM PDT 24
Peak memory 196868 kb
Host smart-04bf4f99-a5c2-4bb1-8c72-081a0b286854
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1979438139 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_filter_stres
s.1979438139
Directory /workspace/0.gpio_filter_stress/latest

Test location /workspace/coverage/default/0.gpio_full_random.3731067716
Short name T170
Test name
Test status
Simulation time 132328078 ps
CPU time 0.94 seconds
Started Apr 21 12:45:48 PM PDT 24
Finished Apr 21 12:45:50 PM PDT 24
Peak memory 197172 kb
Host smart-40465ba7-6686-4b8b-b299-1e16dfe2ba4b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3731067716 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_full_random.3731067716
Directory /workspace/0.gpio_full_random/latest

Test location /workspace/coverage/default/0.gpio_intr_rand_pgm.2726152709
Short name T409
Test name
Test status
Simulation time 267810081 ps
CPU time 1.31 seconds
Started Apr 21 12:45:52 PM PDT 24
Finished Apr 21 12:45:54 PM PDT 24
Peak memory 196236 kb
Host smart-ddbc57b3-5f7a-4a86-971b-39774d8dea0f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2726152709 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_intr_rand_pgm.2726152709
Directory /workspace/0.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/0.gpio_intr_with_filter_rand_intr_event.100969693
Short name T584
Test name
Test status
Simulation time 31212537 ps
CPU time 1.28 seconds
Started Apr 21 12:45:49 PM PDT 24
Finished Apr 21 12:45:51 PM PDT 24
Peak memory 196488 kb
Host smart-c6586b45-f4b6-4fbc-89fa-3d9adad93691
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100969693 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 0.gpio_intr_with_filter_rand_intr_event.100969693
Directory /workspace/0.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/0.gpio_rand_intr_trigger.497291646
Short name T25
Test name
Test status
Simulation time 131360490 ps
CPU time 1.16 seconds
Started Apr 21 12:45:46 PM PDT 24
Finished Apr 21 12:45:47 PM PDT 24
Peak memory 197644 kb
Host smart-fdca5375-95b9-4b27-997f-c935f95e0c33
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=497291646 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_rand_intr_trigger.497291646
Directory /workspace/0.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/0.gpio_random_dout_din.942409913
Short name T257
Test name
Test status
Simulation time 340802987 ps
CPU time 1.1 seconds
Started Apr 21 12:45:51 PM PDT 24
Finished Apr 21 12:45:53 PM PDT 24
Peak memory 196048 kb
Host smart-b6fe895e-18e7-44c9-b944-6384ee4ff480
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=942409913 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_random_dout_din.942409913
Directory /workspace/0.gpio_random_dout_din/latest

Test location /workspace/coverage/default/0.gpio_random_dout_din_no_pullup_pulldown.3639406425
Short name T430
Test name
Test status
Simulation time 25426361 ps
CPU time 0.71 seconds
Started Apr 21 12:46:04 PM PDT 24
Finished Apr 21 12:46:07 PM PDT 24
Peak memory 195684 kb
Host smart-21fc7b9f-1118-47c0-916c-5e8f6f05e5fd
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3639406425 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_random_dout_din_no_pullup
_pulldown.3639406425
Directory /workspace/0.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/0.gpio_random_long_reg_writes_reg_reads.1926225768
Short name T349
Test name
Test status
Simulation time 302614908 ps
CPU time 2.84 seconds
Started Apr 21 12:46:00 PM PDT 24
Finished Apr 21 12:46:03 PM PDT 24
Peak memory 198104 kb
Host smart-04f30d87-10d7-40d8-8248-6c3c69235494
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1926225768 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_ran
dom_long_reg_writes_reg_reads.1926225768
Directory /workspace/0.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/0.gpio_sec_cm.3600243643
Short name T58
Test name
Test status
Simulation time 205844677 ps
CPU time 0.86 seconds
Started Apr 21 12:45:55 PM PDT 24
Finished Apr 21 12:45:57 PM PDT 24
Peak memory 213632 kb
Host smart-91d97daf-3e04-4f93-8165-a9d83962c144
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3600243643 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_sec_cm.3600243643
Directory /workspace/0.gpio_sec_cm/latest

Test location /workspace/coverage/default/0.gpio_smoke.3805625916
Short name T486
Test name
Test status
Simulation time 229226554 ps
CPU time 1.12 seconds
Started Apr 21 12:46:04 PM PDT 24
Finished Apr 21 12:46:06 PM PDT 24
Peak memory 196636 kb
Host smart-94cc8fbc-eca3-444e-98ee-a6d1df6336ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3805625916 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_smoke.3805625916
Directory /workspace/0.gpio_smoke/latest

Test location /workspace/coverage/default/0.gpio_smoke_no_pullup_pulldown.3451448198
Short name T42
Test name
Test status
Simulation time 60568481 ps
CPU time 1.11 seconds
Started Apr 21 12:46:06 PM PDT 24
Finished Apr 21 12:46:08 PM PDT 24
Peak memory 196548 kb
Host smart-07182559-a9bc-45a0-8f8f-70336558005b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3451448198 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_no_pullup_pulldown.3451448198
Directory /workspace/0.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/1.gpio_alert_test.4057968267
Short name T711
Test name
Test status
Simulation time 10500339 ps
CPU time 0.61 seconds
Started Apr 21 12:46:03 PM PDT 24
Finished Apr 21 12:46:06 PM PDT 24
Peak memory 193948 kb
Host smart-46267dd6-3849-4f0e-bdc3-edc5c5ee526c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4057968267 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_alert_test.4057968267
Directory /workspace/1.gpio_alert_test/latest

Test location /workspace/coverage/default/1.gpio_dout_din_regs_random_rw.2393566699
Short name T684
Test name
Test status
Simulation time 45848951 ps
CPU time 0.78 seconds
Started Apr 21 12:46:42 PM PDT 24
Finished Apr 21 12:46:44 PM PDT 24
Peak memory 194548 kb
Host smart-d13d09bf-1554-4d56-b3bf-482349b51999
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2393566699 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_dout_din_regs_random_rw.2393566699
Directory /workspace/1.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/1.gpio_filter_stress.2137550067
Short name T560
Test name
Test status
Simulation time 178863738 ps
CPU time 4.93 seconds
Started Apr 21 12:45:58 PM PDT 24
Finished Apr 21 12:46:04 PM PDT 24
Peak memory 196064 kb
Host smart-c71a9daa-e393-4c38-8e1e-4ca4ec8a3d6c
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2137550067 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_filter_stres
s.2137550067
Directory /workspace/1.gpio_filter_stress/latest

Test location /workspace/coverage/default/1.gpio_full_random.3519763005
Short name T317
Test name
Test status
Simulation time 90016637 ps
CPU time 0.64 seconds
Started Apr 21 12:45:50 PM PDT 24
Finished Apr 21 12:45:51 PM PDT 24
Peak memory 194756 kb
Host smart-533aee2b-5870-4d85-9f41-3c092418b439
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3519763005 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_full_random.3519763005
Directory /workspace/1.gpio_full_random/latest

Test location /workspace/coverage/default/1.gpio_intr_rand_pgm.2940837390
Short name T161
Test name
Test status
Simulation time 43991174 ps
CPU time 0.85 seconds
Started Apr 21 12:45:47 PM PDT 24
Finished Apr 21 12:45:49 PM PDT 24
Peak memory 195704 kb
Host smart-637ffc45-ce39-4b23-b4af-389f571f7adf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2940837390 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_intr_rand_pgm.2940837390
Directory /workspace/1.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/1.gpio_intr_with_filter_rand_intr_event.2822972434
Short name T551
Test name
Test status
Simulation time 364431211 ps
CPU time 3.04 seconds
Started Apr 21 12:45:47 PM PDT 24
Finished Apr 21 12:45:51 PM PDT 24
Peak memory 198352 kb
Host smart-b61cf665-33bb-49df-b8af-1e76e84fb83b
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2822972434 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 1.gpio_intr_with_filter_rand_intr_event.2822972434
Directory /workspace/1.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/1.gpio_rand_intr_trigger.337470698
Short name T654
Test name
Test status
Simulation time 194206434 ps
CPU time 1.25 seconds
Started Apr 21 12:45:46 PM PDT 24
Finished Apr 21 12:45:48 PM PDT 24
Peak memory 196736 kb
Host smart-75e4fe1b-520d-4291-84dc-6bb1fef740e6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=337470698 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_rand_intr_trigger.337470698
Directory /workspace/1.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/1.gpio_random_dout_din.2339288308
Short name T719
Test name
Test status
Simulation time 24278242 ps
CPU time 0.76 seconds
Started Apr 21 12:45:51 PM PDT 24
Finished Apr 21 12:45:52 PM PDT 24
Peak memory 196220 kb
Host smart-4e3fbebb-9484-4c76-a29d-83737419ec58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2339288308 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_random_dout_din.2339288308
Directory /workspace/1.gpio_random_dout_din/latest

Test location /workspace/coverage/default/1.gpio_random_dout_din_no_pullup_pulldown.3806285523
Short name T628
Test name
Test status
Simulation time 33104905 ps
CPU time 0.82 seconds
Started Apr 21 12:46:00 PM PDT 24
Finished Apr 21 12:46:02 PM PDT 24
Peak memory 197540 kb
Host smart-914be458-a64f-4495-b4a1-646bcef0af0f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3806285523 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_random_dout_din_no_pullup
_pulldown.3806285523
Directory /workspace/1.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/1.gpio_random_long_reg_writes_reg_reads.2948460623
Short name T468
Test name
Test status
Simulation time 75248503 ps
CPU time 1.29 seconds
Started Apr 21 12:45:53 PM PDT 24
Finished Apr 21 12:45:56 PM PDT 24
Peak memory 198144 kb
Host smart-133dd580-0ee0-4551-a50c-3384ee98b726
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2948460623 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_ran
dom_long_reg_writes_reg_reads.2948460623
Directory /workspace/1.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/1.gpio_sec_cm.1095366864
Short name T73
Test name
Test status
Simulation time 87087297 ps
CPU time 0.96 seconds
Started Apr 21 12:45:58 PM PDT 24
Finished Apr 21 12:46:01 PM PDT 24
Peak memory 214888 kb
Host smart-64310d34-edde-4e27-9392-6be32a23401f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1095366864 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_sec_cm.1095366864
Directory /workspace/1.gpio_sec_cm/latest

Test location /workspace/coverage/default/1.gpio_smoke.2385276561
Short name T631
Test name
Test status
Simulation time 251502060 ps
CPU time 1.32 seconds
Started Apr 21 12:46:02 PM PDT 24
Finished Apr 21 12:46:05 PM PDT 24
Peak memory 197080 kb
Host smart-d580fce7-4715-453b-9724-cf8b0a45845e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2385276561 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_smoke.2385276561
Directory /workspace/1.gpio_smoke/latest

Test location /workspace/coverage/default/1.gpio_smoke_no_pullup_pulldown.2198409625
Short name T259
Test name
Test status
Simulation time 43287024 ps
CPU time 1.25 seconds
Started Apr 21 12:45:54 PM PDT 24
Finished Apr 21 12:45:56 PM PDT 24
Peak memory 196068 kb
Host smart-e786c149-3a34-4106-aa22-77c287643259
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2198409625 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_no_pullup_pulldown.2198409625
Directory /workspace/1.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/1.gpio_stress_all.2549597538
Short name T222
Test name
Test status
Simulation time 3580374387 ps
CPU time 79.1 seconds
Started Apr 21 12:45:59 PM PDT 24
Finished Apr 21 12:47:19 PM PDT 24
Peak memory 198204 kb
Host smart-09939518-6180-45a0-bc33-2367ecb64c02
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2549597538 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.g
pio_stress_all.2549597538
Directory /workspace/1.gpio_stress_all/latest

Test location /workspace/coverage/default/10.gpio_alert_test.1980741177
Short name T414
Test name
Test status
Simulation time 22603182 ps
CPU time 0.56 seconds
Started Apr 21 12:46:23 PM PDT 24
Finished Apr 21 12:46:25 PM PDT 24
Peak memory 193992 kb
Host smart-64208499-2684-40b3-b1e2-2e2e8649664a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1980741177 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_alert_test.1980741177
Directory /workspace/10.gpio_alert_test/latest

Test location /workspace/coverage/default/10.gpio_dout_din_regs_random_rw.3926188410
Short name T419
Test name
Test status
Simulation time 480220038 ps
CPU time 0.92 seconds
Started Apr 21 12:46:24 PM PDT 24
Finished Apr 21 12:46:25 PM PDT 24
Peak memory 197424 kb
Host smart-2f576437-f506-4ee0-94b7-8998b0231cab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3926188410 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_dout_din_regs_random_rw.3926188410
Directory /workspace/10.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/10.gpio_filter_stress.2659855486
Short name T440
Test name
Test status
Simulation time 730842824 ps
CPU time 10.08 seconds
Started Apr 21 12:46:20 PM PDT 24
Finished Apr 21 12:46:31 PM PDT 24
Peak memory 197160 kb
Host smart-4654dc8d-9e3b-4a71-a66a-88e7e36792e0
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2659855486 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_filter_stre
ss.2659855486
Directory /workspace/10.gpio_filter_stress/latest

Test location /workspace/coverage/default/10.gpio_full_random.1052996703
Short name T410
Test name
Test status
Simulation time 68766507 ps
CPU time 0.91 seconds
Started Apr 21 12:46:21 PM PDT 24
Finished Apr 21 12:46:22 PM PDT 24
Peak memory 197244 kb
Host smart-a592ef12-97ed-4710-91eb-1852cc38cac9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1052996703 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_full_random.1052996703
Directory /workspace/10.gpio_full_random/latest

Test location /workspace/coverage/default/10.gpio_intr_rand_pgm.2847737296
Short name T524
Test name
Test status
Simulation time 98523679 ps
CPU time 1.26 seconds
Started Apr 21 12:46:19 PM PDT 24
Finished Apr 21 12:46:20 PM PDT 24
Peak memory 196664 kb
Host smart-dd5c5bef-eabc-489c-bcb5-c76043283bd4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2847737296 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_intr_rand_pgm.2847737296
Directory /workspace/10.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/10.gpio_intr_with_filter_rand_intr_event.1388833517
Short name T196
Test name
Test status
Simulation time 946255227 ps
CPU time 2.14 seconds
Started Apr 21 12:46:24 PM PDT 24
Finished Apr 21 12:46:27 PM PDT 24
Peak memory 196456 kb
Host smart-49be9974-80c4-4878-b6b3-cc3d113ef435
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1388833517 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 10.gpio_intr_with_filter_rand_intr_event.1388833517
Directory /workspace/10.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/10.gpio_rand_intr_trigger.1922363920
Short name T305
Test name
Test status
Simulation time 63488171 ps
CPU time 2.04 seconds
Started Apr 21 12:46:23 PM PDT 24
Finished Apr 21 12:46:25 PM PDT 24
Peak memory 197196 kb
Host smart-fff970e1-9e68-43bb-8809-a215923d8fcb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1922363920 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_rand_intr_trigger
.1922363920
Directory /workspace/10.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/10.gpio_random_dout_din.356500963
Short name T503
Test name
Test status
Simulation time 33551447 ps
CPU time 1.11 seconds
Started Apr 21 12:46:20 PM PDT 24
Finished Apr 21 12:46:22 PM PDT 24
Peak memory 196184 kb
Host smart-6c8c99e0-345d-4ce5-ba68-f59156758f07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=356500963 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_random_dout_din.356500963
Directory /workspace/10.gpio_random_dout_din/latest

Test location /workspace/coverage/default/10.gpio_random_dout_din_no_pullup_pulldown.3786690199
Short name T476
Test name
Test status
Simulation time 53263185 ps
CPU time 1.25 seconds
Started Apr 21 12:46:28 PM PDT 24
Finished Apr 21 12:46:30 PM PDT 24
Peak memory 198220 kb
Host smart-be8c117e-9ec1-4e2f-bfcd-9232d4e85fc7
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3786690199 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_random_dout_din_no_pullu
p_pulldown.3786690199
Directory /workspace/10.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/10.gpio_random_long_reg_writes_reg_reads.756771531
Short name T514
Test name
Test status
Simulation time 676365980 ps
CPU time 3.02 seconds
Started Apr 21 12:46:19 PM PDT 24
Finished Apr 21 12:46:22 PM PDT 24
Peak memory 198144 kb
Host smart-fbec5ee0-d18b-4649-be93-e5defed45e8c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=756771531 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_ran
dom_long_reg_writes_reg_reads.756771531
Directory /workspace/10.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/10.gpio_smoke.221832910
Short name T451
Test name
Test status
Simulation time 130628895 ps
CPU time 1.06 seconds
Started Apr 21 12:46:22 PM PDT 24
Finished Apr 21 12:46:23 PM PDT 24
Peak memory 195656 kb
Host smart-d335c3f1-0a6a-44cb-88ca-18b21d15a315
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=221832910 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_smoke.221832910
Directory /workspace/10.gpio_smoke/latest

Test location /workspace/coverage/default/10.gpio_smoke_no_pullup_pulldown.2270443976
Short name T603
Test name
Test status
Simulation time 227228483 ps
CPU time 1.14 seconds
Started Apr 21 12:46:18 PM PDT 24
Finished Apr 21 12:46:20 PM PDT 24
Peak memory 196620 kb
Host smart-7bc3c973-5922-403e-b145-dd65909746b4
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2270443976 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_no_pullup_pulldown.2270443976
Directory /workspace/10.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/10.gpio_stress_all.2511491248
Short name T449
Test name
Test status
Simulation time 248567740102 ps
CPU time 134.05 seconds
Started Apr 21 12:46:23 PM PDT 24
Finished Apr 21 12:48:38 PM PDT 24
Peak memory 198168 kb
Host smart-570d181a-3056-4bb3-b254-b3881cf9bb8a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2511491248 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.
gpio_stress_all.2511491248
Directory /workspace/10.gpio_stress_all/latest

Test location /workspace/coverage/default/10.gpio_stress_all_with_rand_reset.3678665661
Short name T398
Test name
Test status
Simulation time 37776192407 ps
CPU time 747.02 seconds
Started Apr 21 12:46:20 PM PDT 24
Finished Apr 21 12:58:48 PM PDT 24
Peak memory 198308 kb
Host smart-62449840-afeb-4ba8-8c7d-50f7bd24ad96
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3678665661 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_stress_all_with_rand_reset.3678665661
Directory /workspace/10.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.gpio_alert_test.1479409430
Short name T290
Test name
Test status
Simulation time 48065380 ps
CPU time 0.56 seconds
Started Apr 21 12:46:23 PM PDT 24
Finished Apr 21 12:46:25 PM PDT 24
Peak memory 194108 kb
Host smart-4576abbe-3306-41ea-ba42-e8d13d6bd96c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1479409430 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_alert_test.1479409430
Directory /workspace/11.gpio_alert_test/latest

Test location /workspace/coverage/default/11.gpio_dout_din_regs_random_rw.3134580311
Short name T423
Test name
Test status
Simulation time 107169927 ps
CPU time 0.7 seconds
Started Apr 21 12:46:20 PM PDT 24
Finished Apr 21 12:46:21 PM PDT 24
Peak memory 194268 kb
Host smart-5fa3e3f0-7acc-431f-8866-8e5074241a05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3134580311 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_dout_din_regs_random_rw.3134580311
Directory /workspace/11.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/11.gpio_filter_stress.4158513185
Short name T585
Test name
Test status
Simulation time 880112323 ps
CPU time 16.26 seconds
Started Apr 21 12:46:26 PM PDT 24
Finished Apr 21 12:46:43 PM PDT 24
Peak memory 196732 kb
Host smart-11a6ebff-70e4-434a-a1ab-0c3d523e3b03
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4158513185 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_filter_stre
ss.4158513185
Directory /workspace/11.gpio_filter_stress/latest

Test location /workspace/coverage/default/11.gpio_full_random.998429178
Short name T558
Test name
Test status
Simulation time 72347516 ps
CPU time 0.87 seconds
Started Apr 21 12:46:28 PM PDT 24
Finished Apr 21 12:46:30 PM PDT 24
Peak memory 197288 kb
Host smart-318bac36-50eb-476d-8f06-7ceb0181be62
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=998429178 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_full_random.998429178
Directory /workspace/11.gpio_full_random/latest

Test location /workspace/coverage/default/11.gpio_intr_rand_pgm.1475858002
Short name T479
Test name
Test status
Simulation time 124280116 ps
CPU time 1.07 seconds
Started Apr 21 12:46:21 PM PDT 24
Finished Apr 21 12:46:22 PM PDT 24
Peak memory 196228 kb
Host smart-1f1c1fe1-b8fd-4ccb-81fa-e631516b458e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1475858002 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_intr_rand_pgm.1475858002
Directory /workspace/11.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/11.gpio_intr_with_filter_rand_intr_event.3554563035
Short name T183
Test name
Test status
Simulation time 92049996 ps
CPU time 1.17 seconds
Started Apr 21 12:46:21 PM PDT 24
Finished Apr 21 12:46:23 PM PDT 24
Peak memory 197040 kb
Host smart-d7022c4f-d20a-4eb8-9ee4-84743f26ef51
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3554563035 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 11.gpio_intr_with_filter_rand_intr_event.3554563035
Directory /workspace/11.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/11.gpio_rand_intr_trigger.1364766068
Short name T561
Test name
Test status
Simulation time 379537032 ps
CPU time 2.24 seconds
Started Apr 21 12:46:20 PM PDT 24
Finished Apr 21 12:46:23 PM PDT 24
Peak memory 198116 kb
Host smart-4ea3f0a4-35c2-410f-bc40-e7352bd89115
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1364766068 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_rand_intr_trigger
.1364766068
Directory /workspace/11.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/11.gpio_random_dout_din.3498548735
Short name T528
Test name
Test status
Simulation time 52538041 ps
CPU time 1.05 seconds
Started Apr 21 12:46:20 PM PDT 24
Finished Apr 21 12:46:22 PM PDT 24
Peak memory 196972 kb
Host smart-d8f4a682-97e3-4064-9d30-43a97013beca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3498548735 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_random_dout_din.3498548735
Directory /workspace/11.gpio_random_dout_din/latest

Test location /workspace/coverage/default/11.gpio_random_dout_din_no_pullup_pulldown.3948203147
Short name T675
Test name
Test status
Simulation time 138589432 ps
CPU time 1.05 seconds
Started Apr 21 12:46:21 PM PDT 24
Finished Apr 21 12:46:23 PM PDT 24
Peak memory 196732 kb
Host smart-96bb425f-6124-49da-86d9-650de9b31176
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3948203147 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_random_dout_din_no_pullu
p_pulldown.3948203147
Directory /workspace/11.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/11.gpio_random_long_reg_writes_reg_reads.4102995627
Short name T620
Test name
Test status
Simulation time 1086326577 ps
CPU time 7.01 seconds
Started Apr 21 12:46:23 PM PDT 24
Finished Apr 21 12:46:31 PM PDT 24
Peak memory 198216 kb
Host smart-76c7d175-b7b4-4fd1-9cba-f16d52d6b372
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4102995627 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_ra
ndom_long_reg_writes_reg_reads.4102995627
Directory /workspace/11.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/11.gpio_smoke.3415994284
Short name T593
Test name
Test status
Simulation time 583168108 ps
CPU time 1.29 seconds
Started Apr 21 12:46:23 PM PDT 24
Finished Apr 21 12:46:25 PM PDT 24
Peak memory 196868 kb
Host smart-444549df-11f2-421a-8b27-6fe38f281e08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3415994284 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_smoke.3415994284
Directory /workspace/11.gpio_smoke/latest

Test location /workspace/coverage/default/11.gpio_smoke_no_pullup_pulldown.3795364510
Short name T94
Test name
Test status
Simulation time 45358826 ps
CPU time 1.25 seconds
Started Apr 21 12:46:21 PM PDT 24
Finished Apr 21 12:46:23 PM PDT 24
Peak memory 196536 kb
Host smart-388fe79b-944c-4c41-931d-a41c071b03f7
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3795364510 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_no_pullup_pulldown.3795364510
Directory /workspace/11.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/11.gpio_stress_all.1164267464
Short name T334
Test name
Test status
Simulation time 20760033594 ps
CPU time 79.03 seconds
Started Apr 21 12:46:30 PM PDT 24
Finished Apr 21 12:47:50 PM PDT 24
Peak memory 198168 kb
Host smart-2a7794e5-4fcc-41e0-937d-101c4feed2e5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1164267464 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.
gpio_stress_all.1164267464
Directory /workspace/11.gpio_stress_all/latest

Test location /workspace/coverage/default/11.gpio_stress_all_with_rand_reset.2611458490
Short name T86
Test name
Test status
Simulation time 26116002935 ps
CPU time 597.58 seconds
Started Apr 21 12:46:33 PM PDT 24
Finished Apr 21 12:56:32 PM PDT 24
Peak memory 198300 kb
Host smart-741cf57d-d1ed-45ae-bbd0-f4f920f3f42f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2611458490 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_stress_all_with_rand_reset.2611458490
Directory /workspace/11.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.gpio_alert_test.959122281
Short name T656
Test name
Test status
Simulation time 13220623 ps
CPU time 0.59 seconds
Started Apr 21 12:46:26 PM PDT 24
Finished Apr 21 12:46:27 PM PDT 24
Peak memory 194284 kb
Host smart-6f634dba-5137-407e-a4eb-3c72526ce9f5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=959122281 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_alert_test.959122281
Directory /workspace/12.gpio_alert_test/latest

Test location /workspace/coverage/default/12.gpio_dout_din_regs_random_rw.3728752119
Short name T152
Test name
Test status
Simulation time 37850101 ps
CPU time 0.85 seconds
Started Apr 21 12:46:24 PM PDT 24
Finished Apr 21 12:46:26 PM PDT 24
Peak memory 196292 kb
Host smart-01879539-3081-4c70-90ee-15eaf5f17b08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3728752119 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_dout_din_regs_random_rw.3728752119
Directory /workspace/12.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/12.gpio_filter_stress.156980406
Short name T391
Test name
Test status
Simulation time 880478772 ps
CPU time 12.43 seconds
Started Apr 21 12:46:27 PM PDT 24
Finished Apr 21 12:46:41 PM PDT 24
Peak memory 196964 kb
Host smart-0fefe9db-c586-433e-a74e-0a58ea3a7eed
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=156980406 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_filter_stres
s.156980406
Directory /workspace/12.gpio_filter_stress/latest

Test location /workspace/coverage/default/12.gpio_full_random.677829074
Short name T357
Test name
Test status
Simulation time 345776518 ps
CPU time 1.07 seconds
Started Apr 21 12:46:33 PM PDT 24
Finished Apr 21 12:46:35 PM PDT 24
Peak memory 196860 kb
Host smart-3a4b8c7a-0fde-4790-ad5c-214a5378e39c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=677829074 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_full_random.677829074
Directory /workspace/12.gpio_full_random/latest

Test location /workspace/coverage/default/12.gpio_intr_rand_pgm.447352775
Short name T491
Test name
Test status
Simulation time 158749275 ps
CPU time 0.88 seconds
Started Apr 21 12:46:28 PM PDT 24
Finished Apr 21 12:46:30 PM PDT 24
Peak memory 195760 kb
Host smart-28c8276c-6a74-4d27-9d61-ef3067a8a473
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=447352775 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_intr_rand_pgm.447352775
Directory /workspace/12.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/12.gpio_intr_with_filter_rand_intr_event.3750569959
Short name T316
Test name
Test status
Simulation time 316895611 ps
CPU time 3.46 seconds
Started Apr 21 12:46:24 PM PDT 24
Finished Apr 21 12:46:28 PM PDT 24
Peak memory 198176 kb
Host smart-e6e76649-52a1-425c-acb0-a47d640b7588
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3750569959 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 12.gpio_intr_with_filter_rand_intr_event.3750569959
Directory /workspace/12.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/12.gpio_rand_intr_trigger.85790984
Short name T156
Test name
Test status
Simulation time 50236415 ps
CPU time 1.32 seconds
Started Apr 21 12:46:27 PM PDT 24
Finished Apr 21 12:46:29 PM PDT 24
Peak memory 196780 kb
Host smart-ceb1a4c1-f4b7-484d-99e0-e6c362788563
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85790984 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigger
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_rand_intr_trigger.85790984
Directory /workspace/12.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/12.gpio_random_dout_din.4027278982
Short name T435
Test name
Test status
Simulation time 18602147 ps
CPU time 0.77 seconds
Started Apr 21 12:46:27 PM PDT 24
Finished Apr 21 12:46:28 PM PDT 24
Peak memory 195548 kb
Host smart-fb3ffa9c-56e5-413c-8fc8-5dca61bfe440
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4027278982 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_random_dout_din.4027278982
Directory /workspace/12.gpio_random_dout_din/latest

Test location /workspace/coverage/default/12.gpio_random_dout_din_no_pullup_pulldown.4110443901
Short name T203
Test name
Test status
Simulation time 118243789 ps
CPU time 1.23 seconds
Started Apr 21 12:46:32 PM PDT 24
Finished Apr 21 12:46:34 PM PDT 24
Peak memory 197296 kb
Host smart-dd078ab7-c314-4cec-a8b3-d7d45104b272
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4110443901 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_random_dout_din_no_pullu
p_pulldown.4110443901
Directory /workspace/12.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/12.gpio_random_long_reg_writes_reg_reads.3398103789
Short name T653
Test name
Test status
Simulation time 116007543 ps
CPU time 5.55 seconds
Started Apr 21 12:46:27 PM PDT 24
Finished Apr 21 12:46:33 PM PDT 24
Peak memory 198216 kb
Host smart-7e30f258-84b4-4226-b672-63ac697a6a16
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3398103789 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_ra
ndom_long_reg_writes_reg_reads.3398103789
Directory /workspace/12.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/12.gpio_smoke.708958871
Short name T319
Test name
Test status
Simulation time 198976918 ps
CPU time 1.03 seconds
Started Apr 21 12:46:24 PM PDT 24
Finished Apr 21 12:46:25 PM PDT 24
Peak memory 196500 kb
Host smart-773e59c9-a69c-4d29-a4a4-a3e2b694245f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=708958871 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_smoke.708958871
Directory /workspace/12.gpio_smoke/latest

Test location /workspace/coverage/default/12.gpio_smoke_no_pullup_pulldown.3942859421
Short name T415
Test name
Test status
Simulation time 55410534 ps
CPU time 1.26 seconds
Started Apr 21 12:46:25 PM PDT 24
Finished Apr 21 12:46:27 PM PDT 24
Peak memory 195716 kb
Host smart-cf8c3271-8e40-4929-8436-5fb8ae544497
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3942859421 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_no_pullup_pulldown.3942859421
Directory /workspace/12.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/12.gpio_stress_all.593126113
Short name T245
Test name
Test status
Simulation time 13248815929 ps
CPU time 79.19 seconds
Started Apr 21 12:46:26 PM PDT 24
Finished Apr 21 12:47:46 PM PDT 24
Peak memory 198388 kb
Host smart-c8af99e7-2b29-49d0-878f-8bcb3579aee1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=593126113 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.g
pio_stress_all.593126113
Directory /workspace/12.gpio_stress_all/latest

Test location /workspace/coverage/default/13.gpio_alert_test.2852218834
Short name T707
Test name
Test status
Simulation time 23816295 ps
CPU time 0.59 seconds
Started Apr 21 12:46:26 PM PDT 24
Finished Apr 21 12:46:28 PM PDT 24
Peak memory 194800 kb
Host smart-7ce2a016-91c5-43a9-9b7c-d323a6ff502a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2852218834 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_alert_test.2852218834
Directory /workspace/13.gpio_alert_test/latest

Test location /workspace/coverage/default/13.gpio_dout_din_regs_random_rw.2654784773
Short name T218
Test name
Test status
Simulation time 64573950 ps
CPU time 0.7 seconds
Started Apr 21 12:46:35 PM PDT 24
Finished Apr 21 12:46:36 PM PDT 24
Peak memory 194240 kb
Host smart-a3235f1c-ca55-4f5e-90c9-06dd270f24ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2654784773 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_dout_din_regs_random_rw.2654784773
Directory /workspace/13.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/13.gpio_filter_stress.3025419950
Short name T321
Test name
Test status
Simulation time 587750049 ps
CPU time 7.94 seconds
Started Apr 21 12:46:26 PM PDT 24
Finished Apr 21 12:46:35 PM PDT 24
Peak memory 196552 kb
Host smart-6a3d10c6-6620-4000-85a5-ee522434bacf
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3025419950 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_filter_stre
ss.3025419950
Directory /workspace/13.gpio_filter_stress/latest

Test location /workspace/coverage/default/13.gpio_full_random.3833194152
Short name T413
Test name
Test status
Simulation time 78288197 ps
CPU time 0.72 seconds
Started Apr 21 12:46:33 PM PDT 24
Finished Apr 21 12:46:35 PM PDT 24
Peak memory 194856 kb
Host smart-41422882-4b68-4deb-99fc-579bebb4fdf0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3833194152 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_full_random.3833194152
Directory /workspace/13.gpio_full_random/latest

Test location /workspace/coverage/default/13.gpio_intr_rand_pgm.3721456140
Short name T583
Test name
Test status
Simulation time 47024414 ps
CPU time 1.25 seconds
Started Apr 21 12:46:29 PM PDT 24
Finished Apr 21 12:46:31 PM PDT 24
Peak memory 198248 kb
Host smart-02968e2f-06e0-49fe-a760-2b3a4ea016fc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3721456140 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_intr_rand_pgm.3721456140
Directory /workspace/13.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/13.gpio_intr_with_filter_rand_intr_event.814178820
Short name T625
Test name
Test status
Simulation time 227033986 ps
CPU time 2.35 seconds
Started Apr 21 12:46:28 PM PDT 24
Finished Apr 21 12:46:31 PM PDT 24
Peak memory 198272 kb
Host smart-c26b6c6b-776b-4836-843a-cd4dfb060da3
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=814178820 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 13.gpio_intr_with_filter_rand_intr_event.814178820
Directory /workspace/13.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/13.gpio_rand_intr_trigger.193406664
Short name T292
Test name
Test status
Simulation time 76947961 ps
CPU time 2.54 seconds
Started Apr 21 12:46:28 PM PDT 24
Finished Apr 21 12:46:32 PM PDT 24
Peak memory 196024 kb
Host smart-16234c51-1403-46e1-b600-304f59fc5e58
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=193406664 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_rand_intr_trigger.
193406664
Directory /workspace/13.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/13.gpio_random_dout_din.3263508145
Short name T255
Test name
Test status
Simulation time 206439248 ps
CPU time 0.96 seconds
Started Apr 21 12:46:25 PM PDT 24
Finished Apr 21 12:46:27 PM PDT 24
Peak memory 196132 kb
Host smart-8c4fbaad-06ab-44bc-be80-b45884b50eff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3263508145 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_random_dout_din.3263508145
Directory /workspace/13.gpio_random_dout_din/latest

Test location /workspace/coverage/default/13.gpio_random_dout_din_no_pullup_pulldown.1072163064
Short name T390
Test name
Test status
Simulation time 37370430 ps
CPU time 0.91 seconds
Started Apr 21 12:46:35 PM PDT 24
Finished Apr 21 12:46:36 PM PDT 24
Peak memory 196092 kb
Host smart-e917d299-2a4b-487c-ba35-0abd842adc8d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1072163064 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_random_dout_din_no_pullu
p_pulldown.1072163064
Directory /workspace/13.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/13.gpio_random_long_reg_writes_reg_reads.3768695640
Short name T469
Test name
Test status
Simulation time 946923462 ps
CPU time 3.36 seconds
Started Apr 21 12:46:28 PM PDT 24
Finished Apr 21 12:46:32 PM PDT 24
Peak memory 198256 kb
Host smart-a0c96978-8eef-4b6b-80ee-70b7f56e5fe2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3768695640 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_ra
ndom_long_reg_writes_reg_reads.3768695640
Directory /workspace/13.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/13.gpio_smoke.2351660033
Short name T634
Test name
Test status
Simulation time 74628026 ps
CPU time 1.36 seconds
Started Apr 21 12:46:23 PM PDT 24
Finished Apr 21 12:46:25 PM PDT 24
Peak memory 196968 kb
Host smart-bfe8f544-462c-4981-9296-9b38b6ef1748
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2351660033 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_smoke.2351660033
Directory /workspace/13.gpio_smoke/latest

Test location /workspace/coverage/default/13.gpio_smoke_no_pullup_pulldown.768215882
Short name T194
Test name
Test status
Simulation time 20601083 ps
CPU time 0.78 seconds
Started Apr 21 12:46:27 PM PDT 24
Finished Apr 21 12:46:28 PM PDT 24
Peak memory 195388 kb
Host smart-e557451c-6ee3-4918-b459-bf244081a7c6
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=768215882 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_no_pullup_pulldown.768215882
Directory /workspace/13.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/13.gpio_stress_all.3157112926
Short name T339
Test name
Test status
Simulation time 17135341617 ps
CPU time 37.35 seconds
Started Apr 21 12:46:29 PM PDT 24
Finished Apr 21 12:47:08 PM PDT 24
Peak memory 198268 kb
Host smart-f765a379-ef08-43ac-92dc-23070759455d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3157112926 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.
gpio_stress_all.3157112926
Directory /workspace/13.gpio_stress_all/latest

Test location /workspace/coverage/default/14.gpio_alert_test.134152942
Short name T408
Test name
Test status
Simulation time 41743804 ps
CPU time 0.56 seconds
Started Apr 21 12:46:33 PM PDT 24
Finished Apr 21 12:46:35 PM PDT 24
Peak memory 194072 kb
Host smart-e1d204e6-3889-4a22-b525-4465fe8ae562
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=134152942 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_alert_test.134152942
Directory /workspace/14.gpio_alert_test/latest

Test location /workspace/coverage/default/14.gpio_dout_din_regs_random_rw.1639615445
Short name T472
Test name
Test status
Simulation time 114885235 ps
CPU time 0.73 seconds
Started Apr 21 12:46:34 PM PDT 24
Finished Apr 21 12:46:36 PM PDT 24
Peak memory 195360 kb
Host smart-9aac49d8-57d5-469a-9740-25742d002684
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1639615445 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_dout_din_regs_random_rw.1639615445
Directory /workspace/14.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/14.gpio_filter_stress.2015732305
Short name T602
Test name
Test status
Simulation time 675116133 ps
CPU time 18.36 seconds
Started Apr 21 12:46:34 PM PDT 24
Finished Apr 21 12:46:53 PM PDT 24
Peak memory 197000 kb
Host smart-77c140c9-ed54-4cac-aeb8-ebb2552a5d47
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2015732305 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_filter_stre
ss.2015732305
Directory /workspace/14.gpio_filter_stress/latest

Test location /workspace/coverage/default/14.gpio_full_random.2975745032
Short name T478
Test name
Test status
Simulation time 316486527 ps
CPU time 0.77 seconds
Started Apr 21 12:46:32 PM PDT 24
Finished Apr 21 12:46:34 PM PDT 24
Peak memory 194736 kb
Host smart-2042da2a-5af9-4a07-b82c-f4903f8db8aa
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2975745032 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_full_random.2975745032
Directory /workspace/14.gpio_full_random/latest

Test location /workspace/coverage/default/14.gpio_intr_rand_pgm.2085609789
Short name T568
Test name
Test status
Simulation time 50926740 ps
CPU time 1.06 seconds
Started Apr 21 12:46:33 PM PDT 24
Finished Apr 21 12:46:35 PM PDT 24
Peak memory 197108 kb
Host smart-4c7a145d-2627-4f77-8e64-6c36defb57e1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2085609789 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_intr_rand_pgm.2085609789
Directory /workspace/14.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/14.gpio_intr_with_filter_rand_intr_event.3669927740
Short name T235
Test name
Test status
Simulation time 49512279 ps
CPU time 2.02 seconds
Started Apr 21 12:46:37 PM PDT 24
Finished Apr 21 12:46:39 PM PDT 24
Peak memory 198348 kb
Host smart-d35ac1de-5665-4367-a917-a6036693035d
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3669927740 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 14.gpio_intr_with_filter_rand_intr_event.3669927740
Directory /workspace/14.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/14.gpio_rand_intr_trigger.2989036133
Short name T418
Test name
Test status
Simulation time 408284872 ps
CPU time 1.92 seconds
Started Apr 21 12:46:32 PM PDT 24
Finished Apr 21 12:46:35 PM PDT 24
Peak memory 196316 kb
Host smart-5af62f7c-9945-47b2-b080-11949dcb8e61
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2989036133 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_rand_intr_trigger
.2989036133
Directory /workspace/14.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/14.gpio_random_dout_din.3261667118
Short name T579
Test name
Test status
Simulation time 34540177 ps
CPU time 1.3 seconds
Started Apr 21 12:46:29 PM PDT 24
Finished Apr 21 12:46:31 PM PDT 24
Peak memory 198260 kb
Host smart-fecf8d83-da32-4d6d-acb6-54db5fb7d011
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3261667118 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_random_dout_din.3261667118
Directory /workspace/14.gpio_random_dout_din/latest

Test location /workspace/coverage/default/14.gpio_random_dout_din_no_pullup_pulldown.4152536045
Short name T527
Test name
Test status
Simulation time 493517634 ps
CPU time 0.97 seconds
Started Apr 21 12:46:32 PM PDT 24
Finished Apr 21 12:46:34 PM PDT 24
Peak memory 196792 kb
Host smart-4a64a3a0-1eea-4d59-bfdc-264d00eac9e4
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4152536045 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_random_dout_din_no_pullu
p_pulldown.4152536045
Directory /workspace/14.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/14.gpio_random_long_reg_writes_reg_reads.680748711
Short name T201
Test name
Test status
Simulation time 24458242 ps
CPU time 1.2 seconds
Started Apr 21 12:46:34 PM PDT 24
Finished Apr 21 12:46:36 PM PDT 24
Peak memory 198208 kb
Host smart-97d2d9c2-e526-4175-9792-9b708f2a9e6a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=680748711 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_ran
dom_long_reg_writes_reg_reads.680748711
Directory /workspace/14.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/14.gpio_smoke.3996706152
Short name T496
Test name
Test status
Simulation time 70670322 ps
CPU time 0.72 seconds
Started Apr 21 12:46:33 PM PDT 24
Finished Apr 21 12:46:35 PM PDT 24
Peak memory 194200 kb
Host smart-81777ec5-eec1-4f6d-8d83-3273c3cf8a68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3996706152 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_smoke.3996706152
Directory /workspace/14.gpio_smoke/latest

Test location /workspace/coverage/default/14.gpio_smoke_no_pullup_pulldown.2148606484
Short name T666
Test name
Test status
Simulation time 179722367 ps
CPU time 1.56 seconds
Started Apr 21 12:46:30 PM PDT 24
Finished Apr 21 12:46:33 PM PDT 24
Peak memory 198092 kb
Host smart-c399a9c6-cca9-4d6d-b205-5017eb0c8e22
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2148606484 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_no_pullup_pulldown.2148606484
Directory /workspace/14.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/14.gpio_stress_all.285397045
Short name T717
Test name
Test status
Simulation time 41204623852 ps
CPU time 168.01 seconds
Started Apr 21 12:46:33 PM PDT 24
Finished Apr 21 12:49:22 PM PDT 24
Peak memory 198380 kb
Host smart-e8c0a1dc-3132-4b43-bfe3-35fc03d206dd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=285397045 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.g
pio_stress_all.285397045
Directory /workspace/14.gpio_stress_all/latest

Test location /workspace/coverage/default/14.gpio_stress_all_with_rand_reset.3247300756
Short name T88
Test name
Test status
Simulation time 18102831109 ps
CPU time 560.08 seconds
Started Apr 21 12:46:32 PM PDT 24
Finished Apr 21 12:55:53 PM PDT 24
Peak memory 198228 kb
Host smart-0640b3a2-92cb-415c-8de3-35f77d9768d9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3247300756 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_stress_all_with_rand_reset.3247300756
Directory /workspace/14.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.gpio_alert_test.2352849750
Short name T297
Test name
Test status
Simulation time 13988548 ps
CPU time 0.57 seconds
Started Apr 21 12:46:31 PM PDT 24
Finished Apr 21 12:46:32 PM PDT 24
Peak memory 194948 kb
Host smart-dd35964f-3471-41ef-9f05-c2c7efd2c048
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2352849750 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_alert_test.2352849750
Directory /workspace/15.gpio_alert_test/latest

Test location /workspace/coverage/default/15.gpio_dout_din_regs_random_rw.295399285
Short name T445
Test name
Test status
Simulation time 18147508 ps
CPU time 0.67 seconds
Started Apr 21 12:46:34 PM PDT 24
Finished Apr 21 12:46:35 PM PDT 24
Peak memory 194744 kb
Host smart-f5c14607-9461-4984-886e-30c9d78fd83c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=295399285 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_dout_din_regs_random_rw.295399285
Directory /workspace/15.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/15.gpio_filter_stress.143630984
Short name T240
Test name
Test status
Simulation time 369461200 ps
CPU time 4.14 seconds
Started Apr 21 12:46:34 PM PDT 24
Finished Apr 21 12:46:39 PM PDT 24
Peak memory 195652 kb
Host smart-968cd632-5b57-4c59-8f82-ffd3c3afcdd2
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=143630984 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_filter_stres
s.143630984
Directory /workspace/15.gpio_filter_stress/latest

Test location /workspace/coverage/default/15.gpio_full_random.3701957785
Short name T338
Test name
Test status
Simulation time 76343317 ps
CPU time 0.99 seconds
Started Apr 21 12:46:36 PM PDT 24
Finished Apr 21 12:46:37 PM PDT 24
Peak memory 196888 kb
Host smart-14b4aabe-4072-4c88-8d96-c968913bc694
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3701957785 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_full_random.3701957785
Directory /workspace/15.gpio_full_random/latest

Test location /workspace/coverage/default/15.gpio_intr_rand_pgm.1321600812
Short name T372
Test name
Test status
Simulation time 553875872 ps
CPU time 1.44 seconds
Started Apr 21 12:46:35 PM PDT 24
Finished Apr 21 12:46:37 PM PDT 24
Peak memory 196040 kb
Host smart-256d18df-c0f6-4dde-a282-7843c65c9075
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1321600812 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_intr_rand_pgm.1321600812
Directory /workspace/15.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/15.gpio_intr_with_filter_rand_intr_event.1699200084
Short name T221
Test name
Test status
Simulation time 86719622 ps
CPU time 3.31 seconds
Started Apr 21 12:46:32 PM PDT 24
Finished Apr 21 12:46:36 PM PDT 24
Peak memory 198164 kb
Host smart-f034daff-dcc9-4463-b9d4-f10199dc3910
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1699200084 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 15.gpio_intr_with_filter_rand_intr_event.1699200084
Directory /workspace/15.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/15.gpio_rand_intr_trigger.4032953340
Short name T210
Test name
Test status
Simulation time 114392737 ps
CPU time 2.25 seconds
Started Apr 21 12:46:31 PM PDT 24
Finished Apr 21 12:46:34 PM PDT 24
Peak memory 196812 kb
Host smart-6182a3e1-1193-49e0-aff0-f0cc7054093d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4032953340 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_rand_intr_trigger
.4032953340
Directory /workspace/15.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/15.gpio_random_dout_din.3088677314
Short name T30
Test name
Test status
Simulation time 73836576 ps
CPU time 0.97 seconds
Started Apr 21 12:46:36 PM PDT 24
Finished Apr 21 12:46:37 PM PDT 24
Peak memory 196776 kb
Host smart-ad2ddf1b-7216-46b9-a1b0-e94671b1fe62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3088677314 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_random_dout_din.3088677314
Directory /workspace/15.gpio_random_dout_din/latest

Test location /workspace/coverage/default/15.gpio_random_dout_din_no_pullup_pulldown.2593482654
Short name T216
Test name
Test status
Simulation time 66716504 ps
CPU time 0.92 seconds
Started Apr 21 12:46:31 PM PDT 24
Finished Apr 21 12:46:33 PM PDT 24
Peak memory 196764 kb
Host smart-7979cbb0-bb9e-46ed-b35c-a01a8b4d930e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2593482654 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_random_dout_din_no_pullu
p_pulldown.2593482654
Directory /workspace/15.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/15.gpio_random_long_reg_writes_reg_reads.529023367
Short name T302
Test name
Test status
Simulation time 542765783 ps
CPU time 5.77 seconds
Started Apr 21 12:46:33 PM PDT 24
Finished Apr 21 12:46:39 PM PDT 24
Peak memory 198132 kb
Host smart-31daf1ed-b867-45f6-8f05-3f4d21679152
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=529023367 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_ran
dom_long_reg_writes_reg_reads.529023367
Directory /workspace/15.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/15.gpio_smoke.214550589
Short name T343
Test name
Test status
Simulation time 77020456 ps
CPU time 1.26 seconds
Started Apr 21 12:46:31 PM PDT 24
Finished Apr 21 12:46:33 PM PDT 24
Peak memory 196108 kb
Host smart-3f3e15c7-f47c-4d1a-8f46-42ce80f029bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=214550589 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_smoke.214550589
Directory /workspace/15.gpio_smoke/latest

Test location /workspace/coverage/default/15.gpio_smoke_no_pullup_pulldown.2856485466
Short name T553
Test name
Test status
Simulation time 95712156 ps
CPU time 1.06 seconds
Started Apr 21 12:46:30 PM PDT 24
Finished Apr 21 12:46:32 PM PDT 24
Peak memory 196140 kb
Host smart-60d502e0-8f25-4ae2-9561-17779d4ed11b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2856485466 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_no_pullup_pulldown.2856485466
Directory /workspace/15.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/15.gpio_stress_all.3267055604
Short name T23
Test name
Test status
Simulation time 1186935798 ps
CPU time 27.93 seconds
Started Apr 21 12:46:31 PM PDT 24
Finished Apr 21 12:47:00 PM PDT 24
Peak memory 198028 kb
Host smart-de3ef520-ea6c-4654-8bcd-34ffad74a5ca
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3267055604 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.
gpio_stress_all.3267055604
Directory /workspace/15.gpio_stress_all/latest

Test location /workspace/coverage/default/15.gpio_stress_all_with_rand_reset.611929345
Short name T87
Test name
Test status
Simulation time 15982568135 ps
CPU time 429.57 seconds
Started Apr 21 12:46:33 PM PDT 24
Finished Apr 21 12:53:44 PM PDT 24
Peak memory 198264 kb
Host smart-1dd23813-be33-4a8e-a8b5-d89e7e1d578b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=611929345 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_stress_all_with_rand_reset.611929345
Directory /workspace/15.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.gpio_alert_test.2692580638
Short name T336
Test name
Test status
Simulation time 11677159 ps
CPU time 0.58 seconds
Started Apr 21 12:46:36 PM PDT 24
Finished Apr 21 12:46:37 PM PDT 24
Peak memory 194768 kb
Host smart-4eb0ecb2-47ae-49de-81a2-7e1024f48171
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2692580638 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_alert_test.2692580638
Directory /workspace/16.gpio_alert_test/latest

Test location /workspace/coverage/default/16.gpio_dout_din_regs_random_rw.180405041
Short name T197
Test name
Test status
Simulation time 116593103 ps
CPU time 0.89 seconds
Started Apr 21 12:46:37 PM PDT 24
Finished Apr 21 12:46:39 PM PDT 24
Peak memory 195844 kb
Host smart-010c5f58-93bf-41a8-bd7f-14ec3f929c5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=180405041 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_dout_din_regs_random_rw.180405041
Directory /workspace/16.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/16.gpio_filter_stress.3089137950
Short name T219
Test name
Test status
Simulation time 1498342498 ps
CPU time 23.82 seconds
Started Apr 21 12:46:33 PM PDT 24
Finished Apr 21 12:46:58 PM PDT 24
Peak memory 196460 kb
Host smart-2c9dd300-ccb3-4d97-b06b-e09490a3581a
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3089137950 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_filter_stre
ss.3089137950
Directory /workspace/16.gpio_filter_stress/latest

Test location /workspace/coverage/default/16.gpio_full_random.2387921830
Short name T109
Test name
Test status
Simulation time 64372626 ps
CPU time 1.09 seconds
Started Apr 21 12:46:36 PM PDT 24
Finished Apr 21 12:46:38 PM PDT 24
Peak memory 196668 kb
Host smart-ca31c130-3be6-41c6-a849-07664b8229a4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2387921830 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_full_random.2387921830
Directory /workspace/16.gpio_full_random/latest

Test location /workspace/coverage/default/16.gpio_intr_rand_pgm.501824515
Short name T215
Test name
Test status
Simulation time 131656012 ps
CPU time 1.21 seconds
Started Apr 21 12:46:37 PM PDT 24
Finished Apr 21 12:46:39 PM PDT 24
Peak memory 196988 kb
Host smart-83a0e75d-ff72-4a2d-bdb7-0d50e4e76b34
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=501824515 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_intr_rand_pgm.501824515
Directory /workspace/16.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/16.gpio_intr_with_filter_rand_intr_event.202275012
Short name T601
Test name
Test status
Simulation time 32580486 ps
CPU time 1.36 seconds
Started Apr 21 12:46:37 PM PDT 24
Finished Apr 21 12:46:39 PM PDT 24
Peak memory 196556 kb
Host smart-71b61c7e-ddb1-4f14-a89a-416734a17eed
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=202275012 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 16.gpio_intr_with_filter_rand_intr_event.202275012
Directory /workspace/16.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/16.gpio_rand_intr_trigger.2555952175
Short name T595
Test name
Test status
Simulation time 116267551 ps
CPU time 1.95 seconds
Started Apr 21 12:46:39 PM PDT 24
Finished Apr 21 12:46:41 PM PDT 24
Peak memory 196360 kb
Host smart-16e6c085-3dab-427e-89b4-12b1bea9a05b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2555952175 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_rand_intr_trigger
.2555952175
Directory /workspace/16.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/16.gpio_random_dout_din.1115448171
Short name T213
Test name
Test status
Simulation time 34756981 ps
CPU time 1.31 seconds
Started Apr 21 12:46:32 PM PDT 24
Finished Apr 21 12:46:34 PM PDT 24
Peak memory 198120 kb
Host smart-da2abf93-892e-4751-842e-6df432f9ba06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1115448171 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_random_dout_din.1115448171
Directory /workspace/16.gpio_random_dout_din/latest

Test location /workspace/coverage/default/16.gpio_random_dout_din_no_pullup_pulldown.138329658
Short name T380
Test name
Test status
Simulation time 89256200 ps
CPU time 0.78 seconds
Started Apr 21 12:46:35 PM PDT 24
Finished Apr 21 12:46:36 PM PDT 24
Peak memory 195728 kb
Host smart-fc84ec55-575f-4f5c-9246-1fccd3640e91
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=138329658 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_random_dout_din_no_pullup
_pulldown.138329658
Directory /workspace/16.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/16.gpio_random_long_reg_writes_reg_reads.986461011
Short name T406
Test name
Test status
Simulation time 104003337 ps
CPU time 1.86 seconds
Started Apr 21 12:46:36 PM PDT 24
Finished Apr 21 12:46:39 PM PDT 24
Peak memory 198000 kb
Host smart-917e8c55-2319-46b8-93dc-15fe8286c6b4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=986461011 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_ran
dom_long_reg_writes_reg_reads.986461011
Directory /workspace/16.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/16.gpio_smoke.2742563296
Short name T646
Test name
Test status
Simulation time 152921911 ps
CPU time 1.32 seconds
Started Apr 21 12:46:36 PM PDT 24
Finished Apr 21 12:46:38 PM PDT 24
Peak memory 196908 kb
Host smart-d44e5c26-b570-45f2-8536-d5e216345944
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2742563296 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_smoke.2742563296
Directory /workspace/16.gpio_smoke/latest

Test location /workspace/coverage/default/16.gpio_smoke_no_pullup_pulldown.1142873246
Short name T624
Test name
Test status
Simulation time 107815476 ps
CPU time 0.97 seconds
Started Apr 21 12:46:35 PM PDT 24
Finished Apr 21 12:46:36 PM PDT 24
Peak memory 196524 kb
Host smart-738ef21f-daed-443e-969e-f4eee9dd98a2
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1142873246 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_no_pullup_pulldown.1142873246
Directory /workspace/16.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/16.gpio_stress_all.3197483270
Short name T657
Test name
Test status
Simulation time 7815182695 ps
CPU time 177.21 seconds
Started Apr 21 12:46:36 PM PDT 24
Finished Apr 21 12:49:34 PM PDT 24
Peak memory 198288 kb
Host smart-3e1a3c28-da8a-4a2d-ae2e-abba52b61123
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3197483270 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.
gpio_stress_all.3197483270
Directory /workspace/16.gpio_stress_all/latest

Test location /workspace/coverage/default/17.gpio_alert_test.3859242807
Short name T282
Test name
Test status
Simulation time 14313414 ps
CPU time 0.59 seconds
Started Apr 21 12:46:38 PM PDT 24
Finished Apr 21 12:46:39 PM PDT 24
Peak memory 194740 kb
Host smart-c3931bd0-ec0f-493d-9c34-86eb9fa77701
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3859242807 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_alert_test.3859242807
Directory /workspace/17.gpio_alert_test/latest

Test location /workspace/coverage/default/17.gpio_dout_din_regs_random_rw.3671797836
Short name T184
Test name
Test status
Simulation time 208775987 ps
CPU time 0.94 seconds
Started Apr 21 12:46:40 PM PDT 24
Finished Apr 21 12:46:41 PM PDT 24
Peak memory 196792 kb
Host smart-605f2537-2043-45ee-9384-abf36b603a1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3671797836 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_dout_din_regs_random_rw.3671797836
Directory /workspace/17.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/17.gpio_filter_stress.2818542785
Short name T315
Test name
Test status
Simulation time 2923927509 ps
CPU time 28.98 seconds
Started Apr 21 12:46:37 PM PDT 24
Finished Apr 21 12:47:06 PM PDT 24
Peak memory 197172 kb
Host smart-375eeffd-55bb-4734-9e4b-84d07354ff15
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2818542785 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_filter_stre
ss.2818542785
Directory /workspace/17.gpio_filter_stress/latest

Test location /workspace/coverage/default/17.gpio_full_random.1658070988
Short name T504
Test name
Test status
Simulation time 71896005 ps
CPU time 1.01 seconds
Started Apr 21 12:46:37 PM PDT 24
Finished Apr 21 12:46:38 PM PDT 24
Peak memory 196824 kb
Host smart-519a623b-af1a-4c7b-a0da-18fbcce3cfa4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1658070988 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_full_random.1658070988
Directory /workspace/17.gpio_full_random/latest

Test location /workspace/coverage/default/17.gpio_intr_rand_pgm.959394808
Short name T211
Test name
Test status
Simulation time 33590077 ps
CPU time 0.83 seconds
Started Apr 21 12:46:48 PM PDT 24
Finished Apr 21 12:46:49 PM PDT 24
Peak memory 195792 kb
Host smart-2f7ae1cb-ff73-4d4a-96d9-3e220d4a51ee
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=959394808 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_intr_rand_pgm.959394808
Directory /workspace/17.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/17.gpio_intr_with_filter_rand_intr_event.2210675480
Short name T442
Test name
Test status
Simulation time 55620895 ps
CPU time 2.02 seconds
Started Apr 21 12:46:49 PM PDT 24
Finished Apr 21 12:46:52 PM PDT 24
Peak memory 198276 kb
Host smart-d83a1702-1a8d-4587-af94-9858e152ac38
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2210675480 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 17.gpio_intr_with_filter_rand_intr_event.2210675480
Directory /workspace/17.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/17.gpio_rand_intr_trigger.3593941632
Short name T295
Test name
Test status
Simulation time 324411016 ps
CPU time 2.97 seconds
Started Apr 21 12:47:31 PM PDT 24
Finished Apr 21 12:47:34 PM PDT 24
Peak memory 197344 kb
Host smart-19aa8224-7a04-46e6-8224-cd167c8e351a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3593941632 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_rand_intr_trigger
.3593941632
Directory /workspace/17.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/17.gpio_random_dout_din.2272278068
Short name T149
Test name
Test status
Simulation time 73322776 ps
CPU time 0.99 seconds
Started Apr 21 12:46:40 PM PDT 24
Finished Apr 21 12:46:41 PM PDT 24
Peak memory 197000 kb
Host smart-0b1ed540-e4f8-414e-9680-0186c167b5f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2272278068 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_random_dout_din.2272278068
Directory /workspace/17.gpio_random_dout_din/latest

Test location /workspace/coverage/default/17.gpio_random_dout_din_no_pullup_pulldown.3696894774
Short name T630
Test name
Test status
Simulation time 258654391 ps
CPU time 1.17 seconds
Started Apr 21 12:46:39 PM PDT 24
Finished Apr 21 12:46:40 PM PDT 24
Peak memory 197032 kb
Host smart-ab474324-4036-4c22-93f9-dae0b165a3b5
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3696894774 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_random_dout_din_no_pullu
p_pulldown.3696894774
Directory /workspace/17.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/17.gpio_random_long_reg_writes_reg_reads.3941597179
Short name T19
Test name
Test status
Simulation time 887407080 ps
CPU time 3.86 seconds
Started Apr 21 12:46:35 PM PDT 24
Finished Apr 21 12:46:40 PM PDT 24
Peak memory 198124 kb
Host smart-acb425cc-4b38-40b6-8046-240e6e92face
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3941597179 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_ra
ndom_long_reg_writes_reg_reads.3941597179
Directory /workspace/17.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/17.gpio_smoke.811159243
Short name T329
Test name
Test status
Simulation time 26381035 ps
CPU time 0.76 seconds
Started Apr 21 12:46:38 PM PDT 24
Finished Apr 21 12:46:39 PM PDT 24
Peak memory 195528 kb
Host smart-0723eb60-1ba9-4200-bddb-e31e36ae55f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=811159243 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_smoke.811159243
Directory /workspace/17.gpio_smoke/latest

Test location /workspace/coverage/default/17.gpio_smoke_no_pullup_pulldown.2259338073
Short name T612
Test name
Test status
Simulation time 65111161 ps
CPU time 1.39 seconds
Started Apr 21 12:46:35 PM PDT 24
Finished Apr 21 12:46:37 PM PDT 24
Peak memory 196064 kb
Host smart-e8fb5f28-aa32-4d9c-afff-26bbb05a18b8
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2259338073 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_no_pullup_pulldown.2259338073
Directory /workspace/17.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/17.gpio_stress_all.440712119
Short name T703
Test name
Test status
Simulation time 11292581600 ps
CPU time 154.27 seconds
Started Apr 21 12:46:42 PM PDT 24
Finished Apr 21 12:49:17 PM PDT 24
Peak memory 198328 kb
Host smart-ede815fd-340b-43bd-976e-d3c176dfe456
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=440712119 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.g
pio_stress_all.440712119
Directory /workspace/17.gpio_stress_all/latest

Test location /workspace/coverage/default/18.gpio_alert_test.3025445518
Short name T351
Test name
Test status
Simulation time 37744474 ps
CPU time 0.58 seconds
Started Apr 21 12:46:41 PM PDT 24
Finished Apr 21 12:46:42 PM PDT 24
Peak memory 194076 kb
Host smart-13d2cdbc-4e24-4e4c-8374-26537f9bf501
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3025445518 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_alert_test.3025445518
Directory /workspace/18.gpio_alert_test/latest

Test location /workspace/coverage/default/18.gpio_dout_din_regs_random_rw.1652632924
Short name T520
Test name
Test status
Simulation time 40924555 ps
CPU time 0.65 seconds
Started Apr 21 12:46:51 PM PDT 24
Finished Apr 21 12:46:52 PM PDT 24
Peak memory 194240 kb
Host smart-35bffe01-e318-46f3-8dc9-d0fd1d3e4700
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1652632924 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_dout_din_regs_random_rw.1652632924
Directory /workspace/18.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/18.gpio_filter_stress.3991463191
Short name T718
Test name
Test status
Simulation time 171306515 ps
CPU time 4.86 seconds
Started Apr 21 12:46:40 PM PDT 24
Finished Apr 21 12:46:46 PM PDT 24
Peak memory 196216 kb
Host smart-efec1ae5-cbe1-4c83-87bb-fe0d3040f7a0
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3991463191 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_filter_stre
ss.3991463191
Directory /workspace/18.gpio_filter_stress/latest

Test location /workspace/coverage/default/18.gpio_full_random.1600354533
Short name T488
Test name
Test status
Simulation time 71106352 ps
CPU time 0.93 seconds
Started Apr 21 12:46:51 PM PDT 24
Finished Apr 21 12:46:53 PM PDT 24
Peak memory 197916 kb
Host smart-0bd38981-a1e2-4208-b2d6-4631a75018b0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1600354533 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_full_random.1600354533
Directory /workspace/18.gpio_full_random/latest

Test location /workspace/coverage/default/18.gpio_intr_rand_pgm.4081147555
Short name T690
Test name
Test status
Simulation time 282812853 ps
CPU time 1.39 seconds
Started Apr 21 12:46:41 PM PDT 24
Finished Apr 21 12:46:43 PM PDT 24
Peak memory 196856 kb
Host smart-a1b18005-7889-4868-b295-18553c95a7ff
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4081147555 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_intr_rand_pgm.4081147555
Directory /workspace/18.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/18.gpio_intr_with_filter_rand_intr_event.2152486348
Short name T376
Test name
Test status
Simulation time 517049787 ps
CPU time 2.14 seconds
Started Apr 21 12:46:42 PM PDT 24
Finished Apr 21 12:46:44 PM PDT 24
Peak memory 198268 kb
Host smart-19843748-d1fc-4bc0-90c1-7cb7492a50f9
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2152486348 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 18.gpio_intr_with_filter_rand_intr_event.2152486348
Directory /workspace/18.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/18.gpio_rand_intr_trigger.129204648
Short name T37
Test name
Test status
Simulation time 904463390 ps
CPU time 3.63 seconds
Started Apr 21 12:46:47 PM PDT 24
Finished Apr 21 12:46:52 PM PDT 24
Peak memory 196020 kb
Host smart-39354dee-4fbc-4c23-8572-cfea74499642
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=129204648 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_rand_intr_trigger.
129204648
Directory /workspace/18.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/18.gpio_random_dout_din.183494815
Short name T227
Test name
Test status
Simulation time 88704413 ps
CPU time 0.81 seconds
Started Apr 21 12:46:36 PM PDT 24
Finished Apr 21 12:46:38 PM PDT 24
Peak memory 195552 kb
Host smart-a162f646-0b62-4001-b63b-e556fa328108
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=183494815 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_random_dout_din.183494815
Directory /workspace/18.gpio_random_dout_din/latest

Test location /workspace/coverage/default/18.gpio_random_dout_din_no_pullup_pulldown.45034595
Short name T681
Test name
Test status
Simulation time 177476632 ps
CPU time 1.02 seconds
Started Apr 21 12:46:36 PM PDT 24
Finished Apr 21 12:46:38 PM PDT 24
Peak memory 196800 kb
Host smart-bb0176b5-5fe4-4fc4-b083-c0ed29dd86e0
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45034595 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_random_dout_din_no_pullup_
pulldown.45034595
Directory /workspace/18.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/18.gpio_random_long_reg_writes_reg_reads.1561153528
Short name T710
Test name
Test status
Simulation time 68896541 ps
CPU time 1.6 seconds
Started Apr 21 12:46:42 PM PDT 24
Finished Apr 21 12:46:44 PM PDT 24
Peak memory 198032 kb
Host smart-917a61d3-6700-4fab-aa33-08492b6bc076
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1561153528 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_ra
ndom_long_reg_writes_reg_reads.1561153528
Directory /workspace/18.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/18.gpio_smoke.2709638288
Short name T114
Test name
Test status
Simulation time 44724911 ps
CPU time 0.94 seconds
Started Apr 21 12:46:36 PM PDT 24
Finished Apr 21 12:46:37 PM PDT 24
Peak memory 196620 kb
Host smart-6ce811ce-6807-4c32-8107-195ea4037509
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2709638288 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_smoke.2709638288
Directory /workspace/18.gpio_smoke/latest

Test location /workspace/coverage/default/18.gpio_smoke_no_pullup_pulldown.2985650220
Short name T346
Test name
Test status
Simulation time 179231844 ps
CPU time 0.99 seconds
Started Apr 21 12:46:51 PM PDT 24
Finished Apr 21 12:46:53 PM PDT 24
Peak memory 196684 kb
Host smart-cc7e2665-e1fe-4194-921c-9d8c60391773
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2985650220 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_no_pullup_pulldown.2985650220
Directory /workspace/18.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/18.gpio_stress_all.2742202565
Short name T576
Test name
Test status
Simulation time 5855484072 ps
CPU time 137.97 seconds
Started Apr 21 12:46:40 PM PDT 24
Finished Apr 21 12:48:58 PM PDT 24
Peak memory 198264 kb
Host smart-0758d557-0a2b-4960-846c-5f545ae8d0d7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2742202565 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.
gpio_stress_all.2742202565
Directory /workspace/18.gpio_stress_all/latest

Test location /workspace/coverage/default/19.gpio_dout_din_regs_random_rw.1465780368
Short name T673
Test name
Test status
Simulation time 22274334 ps
CPU time 0.86 seconds
Started Apr 21 12:46:39 PM PDT 24
Finished Apr 21 12:46:41 PM PDT 24
Peak memory 195344 kb
Host smart-8bec8572-af14-4565-b9bc-5389157d5f20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1465780368 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_dout_din_regs_random_rw.1465780368
Directory /workspace/19.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/19.gpio_filter_stress.2432184564
Short name T11
Test name
Test status
Simulation time 698430744 ps
CPU time 23.01 seconds
Started Apr 21 12:46:45 PM PDT 24
Finished Apr 21 12:47:09 PM PDT 24
Peak memory 196892 kb
Host smart-f43cfcbc-6b80-4cce-b992-2f1ca56e6f95
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2432184564 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_filter_stre
ss.2432184564
Directory /workspace/19.gpio_filter_stress/latest

Test location /workspace/coverage/default/19.gpio_full_random.2429928163
Short name T639
Test name
Test status
Simulation time 249910083 ps
CPU time 0.96 seconds
Started Apr 21 12:46:46 PM PDT 24
Finished Apr 21 12:46:47 PM PDT 24
Peak memory 196840 kb
Host smart-95696465-2667-41a9-bf87-ae291ea35797
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2429928163 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_full_random.2429928163
Directory /workspace/19.gpio_full_random/latest

Test location /workspace/coverage/default/19.gpio_intr_rand_pgm.2912644637
Short name T160
Test name
Test status
Simulation time 46335100 ps
CPU time 1.27 seconds
Started Apr 21 12:46:39 PM PDT 24
Finished Apr 21 12:46:41 PM PDT 24
Peak memory 197432 kb
Host smart-467f7f91-5a19-48cc-abbc-d599f821b360
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2912644637 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_intr_rand_pgm.2912644637
Directory /workspace/19.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/19.gpio_intr_with_filter_rand_intr_event.419716784
Short name T404
Test name
Test status
Simulation time 136985619 ps
CPU time 1.75 seconds
Started Apr 21 12:46:40 PM PDT 24
Finished Apr 21 12:46:42 PM PDT 24
Peak memory 198184 kb
Host smart-6f55cb17-9943-40f3-a750-5b02aa038f44
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=419716784 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 19.gpio_intr_with_filter_rand_intr_event.419716784
Directory /workspace/19.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/19.gpio_rand_intr_trigger.802414192
Short name T510
Test name
Test status
Simulation time 125580143 ps
CPU time 3.93 seconds
Started Apr 21 12:46:46 PM PDT 24
Finished Apr 21 12:46:50 PM PDT 24
Peak memory 198220 kb
Host smart-db71e5d9-fb22-4904-87e7-6b7d091a060c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=802414192 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_rand_intr_trigger.
802414192
Directory /workspace/19.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/19.gpio_random_dout_din.1046581397
Short name T470
Test name
Test status
Simulation time 125070513 ps
CPU time 0.86 seconds
Started Apr 21 12:46:38 PM PDT 24
Finished Apr 21 12:46:40 PM PDT 24
Peak memory 196684 kb
Host smart-7b6b1a36-a058-4304-8c94-2e88b42d7cc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1046581397 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_random_dout_din.1046581397
Directory /workspace/19.gpio_random_dout_din/latest

Test location /workspace/coverage/default/19.gpio_random_dout_din_no_pullup_pulldown.2236288972
Short name T375
Test name
Test status
Simulation time 63185121 ps
CPU time 0.91 seconds
Started Apr 21 12:46:45 PM PDT 24
Finished Apr 21 12:46:47 PM PDT 24
Peak memory 195956 kb
Host smart-9ae725f1-1cef-4243-b484-05afedc27406
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2236288972 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_random_dout_din_no_pullu
p_pulldown.2236288972
Directory /workspace/19.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/19.gpio_random_long_reg_writes_reg_reads.3049646330
Short name T167
Test name
Test status
Simulation time 486039536 ps
CPU time 5.26 seconds
Started Apr 21 12:46:40 PM PDT 24
Finished Apr 21 12:46:45 PM PDT 24
Peak memory 198032 kb
Host smart-75bb74d3-0438-427d-b707-6936ceb1bf2a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3049646330 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_ra
ndom_long_reg_writes_reg_reads.3049646330
Directory /workspace/19.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/19.gpio_smoke.2858256777
Short name T198
Test name
Test status
Simulation time 57767265 ps
CPU time 1.22 seconds
Started Apr 21 12:46:51 PM PDT 24
Finished Apr 21 12:46:53 PM PDT 24
Peak memory 197360 kb
Host smart-573bb828-c50c-4c19-84f9-fbd4558cbf38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2858256777 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_smoke.2858256777
Directory /workspace/19.gpio_smoke/latest

Test location /workspace/coverage/default/19.gpio_smoke_no_pullup_pulldown.1963685483
Short name T254
Test name
Test status
Simulation time 58280288 ps
CPU time 0.82 seconds
Started Apr 21 12:46:41 PM PDT 24
Finished Apr 21 12:46:42 PM PDT 24
Peak memory 195416 kb
Host smart-60432268-6182-453d-964f-0935a5a85456
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1963685483 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_no_pullup_pulldown.1963685483
Directory /workspace/19.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/19.gpio_stress_all.3642841519
Short name T464
Test name
Test status
Simulation time 1269930150 ps
CPU time 29.38 seconds
Started Apr 21 12:46:39 PM PDT 24
Finished Apr 21 12:47:09 PM PDT 24
Peak memory 198396 kb
Host smart-a28151cd-69a0-44ca-a9a6-2071ee82932e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3642841519 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.
gpio_stress_all.3642841519
Directory /workspace/19.gpio_stress_all/latest

Test location /workspace/coverage/default/2.gpio_alert_test.2326513570
Short name T269
Test name
Test status
Simulation time 108154048 ps
CPU time 0.59 seconds
Started Apr 21 12:45:53 PM PDT 24
Finished Apr 21 12:45:56 PM PDT 24
Peak memory 194232 kb
Host smart-4e7a9c24-e420-45b3-ac39-d30ca553d757
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2326513570 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_alert_test.2326513570
Directory /workspace/2.gpio_alert_test/latest

Test location /workspace/coverage/default/2.gpio_dout_din_regs_random_rw.349618016
Short name T552
Test name
Test status
Simulation time 138006584 ps
CPU time 0.9 seconds
Started Apr 21 12:46:02 PM PDT 24
Finished Apr 21 12:46:03 PM PDT 24
Peak memory 197492 kb
Host smart-42e506d8-a1ce-483a-8c02-1c741c9cab7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=349618016 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_dout_din_regs_random_rw.349618016
Directory /workspace/2.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/2.gpio_filter_stress.4176846573
Short name T93
Test name
Test status
Simulation time 919666512 ps
CPU time 13.09 seconds
Started Apr 21 12:46:04 PM PDT 24
Finished Apr 21 12:46:19 PM PDT 24
Peak memory 197236 kb
Host smart-dd2c425d-ee6e-433e-853f-4e8654d873d6
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4176846573 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_filter_stres
s.4176846573
Directory /workspace/2.gpio_filter_stress/latest

Test location /workspace/coverage/default/2.gpio_full_random.1903093959
Short name T175
Test name
Test status
Simulation time 63882569 ps
CPU time 0.94 seconds
Started Apr 21 12:45:55 PM PDT 24
Finished Apr 21 12:45:57 PM PDT 24
Peak memory 196848 kb
Host smart-dbf14bc0-f099-4dfc-ac0a-2621160804e4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1903093959 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_full_random.1903093959
Directory /workspace/2.gpio_full_random/latest

Test location /workspace/coverage/default/2.gpio_intr_rand_pgm.2248031873
Short name T251
Test name
Test status
Simulation time 132283384 ps
CPU time 1.03 seconds
Started Apr 21 12:46:04 PM PDT 24
Finished Apr 21 12:46:07 PM PDT 24
Peak memory 196360 kb
Host smart-437076d9-1d1d-4833-b2f3-e070ed98487b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2248031873 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_intr_rand_pgm.2248031873
Directory /workspace/2.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/2.gpio_intr_with_filter_rand_intr_event.848287889
Short name T18
Test name
Test status
Simulation time 178226898 ps
CPU time 3.6 seconds
Started Apr 21 12:45:49 PM PDT 24
Finished Apr 21 12:45:53 PM PDT 24
Peak memory 198156 kb
Host smart-5f2cfb6c-a176-4fde-86b4-a8e3dd66cdbc
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=848287889 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 2.gpio_intr_with_filter_rand_intr_event.848287889
Directory /workspace/2.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/2.gpio_rand_intr_trigger.3953891977
Short name T311
Test name
Test status
Simulation time 121138953 ps
CPU time 1.16 seconds
Started Apr 21 12:45:50 PM PDT 24
Finished Apr 21 12:45:52 PM PDT 24
Peak memory 197024 kb
Host smart-e3f77f5f-e2fc-4ccf-afcc-f3ff897854dd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3953891977 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_rand_intr_trigger.
3953891977
Directory /workspace/2.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/2.gpio_random_dout_din.2589476303
Short name T325
Test name
Test status
Simulation time 41961232 ps
CPU time 1.02 seconds
Started Apr 21 12:45:58 PM PDT 24
Finished Apr 21 12:46:01 PM PDT 24
Peak memory 195876 kb
Host smart-771e6005-ece7-4fa2-8745-2f160a87de54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2589476303 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_random_dout_din.2589476303
Directory /workspace/2.gpio_random_dout_din/latest

Test location /workspace/coverage/default/2.gpio_random_dout_din_no_pullup_pulldown.1305344168
Short name T291
Test name
Test status
Simulation time 137146202 ps
CPU time 0.92 seconds
Started Apr 21 12:45:58 PM PDT 24
Finished Apr 21 12:46:01 PM PDT 24
Peak memory 195984 kb
Host smart-7f9b0f26-717a-4150-b26e-5fbb5387e629
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1305344168 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_random_dout_din_no_pullup
_pulldown.1305344168
Directory /workspace/2.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/2.gpio_random_long_reg_writes_reg_reads.4146418544
Short name T519
Test name
Test status
Simulation time 88666947 ps
CPU time 1.46 seconds
Started Apr 21 12:45:51 PM PDT 24
Finished Apr 21 12:45:53 PM PDT 24
Peak memory 198188 kb
Host smart-bcb7f914-3f20-41dc-aae0-d9e4975733f1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4146418544 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_ran
dom_long_reg_writes_reg_reads.4146418544
Directory /workspace/2.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/2.gpio_sec_cm.1552524578
Short name T72
Test name
Test status
Simulation time 93533764 ps
CPU time 0.96 seconds
Started Apr 21 12:45:53 PM PDT 24
Finished Apr 21 12:45:56 PM PDT 24
Peak memory 214880 kb
Host smart-f8b2c3c6-da3b-452b-91e2-06fb205c6115
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1552524578 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_sec_cm.1552524578
Directory /workspace/2.gpio_sec_cm/latest

Test location /workspace/coverage/default/2.gpio_smoke.1745536835
Short name T660
Test name
Test status
Simulation time 450801301 ps
CPU time 1.27 seconds
Started Apr 21 12:45:58 PM PDT 24
Finished Apr 21 12:46:01 PM PDT 24
Peak memory 198096 kb
Host smart-70d08237-f583-40d9-9cef-377c97d5cae0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1745536835 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_smoke.1745536835
Directory /workspace/2.gpio_smoke/latest

Test location /workspace/coverage/default/2.gpio_smoke_no_pullup_pulldown.1416283713
Short name T573
Test name
Test status
Simulation time 307925323 ps
CPU time 1.53 seconds
Started Apr 21 12:45:48 PM PDT 24
Finished Apr 21 12:45:51 PM PDT 24
Peak memory 196932 kb
Host smart-fe59e25b-66ee-4c94-a49e-3fd097494bd5
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1416283713 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_no_pullup_pulldown.1416283713
Directory /workspace/2.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/2.gpio_stress_all.2419511067
Short name T340
Test name
Test status
Simulation time 42224396854 ps
CPU time 105.95 seconds
Started Apr 21 12:45:50 PM PDT 24
Finished Apr 21 12:47:36 PM PDT 24
Peak memory 198192 kb
Host smart-6ae50f8b-07c3-41a2-a2a1-fb1448acc6f0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2419511067 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.g
pio_stress_all.2419511067
Directory /workspace/2.gpio_stress_all/latest

Test location /workspace/coverage/default/20.gpio_alert_test.2822004549
Short name T683
Test name
Test status
Simulation time 43577571 ps
CPU time 0.56 seconds
Started Apr 21 12:46:41 PM PDT 24
Finished Apr 21 12:46:42 PM PDT 24
Peak memory 194296 kb
Host smart-bd292285-4af8-4f78-ac96-c9951a59b9de
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2822004549 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_alert_test.2822004549
Directory /workspace/20.gpio_alert_test/latest

Test location /workspace/coverage/default/20.gpio_dout_din_regs_random_rw.2576734770
Short name T632
Test name
Test status
Simulation time 26973621 ps
CPU time 0.83 seconds
Started Apr 21 12:46:43 PM PDT 24
Finished Apr 21 12:46:44 PM PDT 24
Peak memory 196656 kb
Host smart-ee5752d7-4692-473f-9580-616a9dc90f14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2576734770 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_dout_din_regs_random_rw.2576734770
Directory /workspace/20.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/20.gpio_filter_stress.520645844
Short name T308
Test name
Test status
Simulation time 698951675 ps
CPU time 16.81 seconds
Started Apr 21 12:46:39 PM PDT 24
Finished Apr 21 12:46:57 PM PDT 24
Peak memory 195708 kb
Host smart-8a21ab86-2101-4118-a5c5-b5738f71f11a
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=520645844 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_filter_stres
s.520645844
Directory /workspace/20.gpio_filter_stress/latest

Test location /workspace/coverage/default/20.gpio_full_random.968658938
Short name T264
Test name
Test status
Simulation time 35904922 ps
CPU time 0.75 seconds
Started Apr 21 12:46:40 PM PDT 24
Finished Apr 21 12:46:42 PM PDT 24
Peak memory 194816 kb
Host smart-52423ec1-52b0-4970-addf-ce4c77132406
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=968658938 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_full_random.968658938
Directory /workspace/20.gpio_full_random/latest

Test location /workspace/coverage/default/20.gpio_intr_rand_pgm.2131975694
Short name T40
Test name
Test status
Simulation time 39882519 ps
CPU time 0.8 seconds
Started Apr 21 12:46:41 PM PDT 24
Finished Apr 21 12:46:43 PM PDT 24
Peak memory 195716 kb
Host smart-5dd68f91-3634-4957-924e-f63498132553
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2131975694 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_intr_rand_pgm.2131975694
Directory /workspace/20.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/20.gpio_intr_with_filter_rand_intr_event.2341780065
Short name T661
Test name
Test status
Simulation time 336203316 ps
CPU time 3.76 seconds
Started Apr 21 12:46:42 PM PDT 24
Finished Apr 21 12:46:46 PM PDT 24
Peak memory 198112 kb
Host smart-7ab43f2b-59e1-4656-9eec-288283e6ac23
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2341780065 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 20.gpio_intr_with_filter_rand_intr_event.2341780065
Directory /workspace/20.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/20.gpio_rand_intr_trigger.3945946500
Short name T546
Test name
Test status
Simulation time 38174583 ps
CPU time 1.26 seconds
Started Apr 21 12:46:42 PM PDT 24
Finished Apr 21 12:46:44 PM PDT 24
Peak memory 196928 kb
Host smart-aefa12ea-0c82-46fa-bcde-043d5af13bec
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3945946500 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_rand_intr_trigger
.3945946500
Directory /workspace/20.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/20.gpio_random_dout_din.2552892853
Short name T95
Test name
Test status
Simulation time 67063121 ps
CPU time 0.73 seconds
Started Apr 21 12:46:39 PM PDT 24
Finished Apr 21 12:46:40 PM PDT 24
Peak memory 196124 kb
Host smart-285e3d80-4b53-4ddc-8b45-0f5641c06ffc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2552892853 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_random_dout_din.2552892853
Directory /workspace/20.gpio_random_dout_din/latest

Test location /workspace/coverage/default/20.gpio_random_dout_din_no_pullup_pulldown.2789903887
Short name T285
Test name
Test status
Simulation time 29100788 ps
CPU time 0.78 seconds
Started Apr 21 12:46:42 PM PDT 24
Finished Apr 21 12:46:44 PM PDT 24
Peak memory 195644 kb
Host smart-12706409-692b-45f2-b5e8-86abb66b5366
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2789903887 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_random_dout_din_no_pullu
p_pulldown.2789903887
Directory /workspace/20.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/20.gpio_random_long_reg_writes_reg_reads.2588735213
Short name T443
Test name
Test status
Simulation time 388620121 ps
CPU time 6.55 seconds
Started Apr 21 12:46:43 PM PDT 24
Finished Apr 21 12:46:50 PM PDT 24
Peak memory 198168 kb
Host smart-437c7780-d721-49a5-a325-dda4b52555b1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2588735213 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_ra
ndom_long_reg_writes_reg_reads.2588735213
Directory /workspace/20.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/20.gpio_smoke.3914059366
Short name T359
Test name
Test status
Simulation time 83315620 ps
CPU time 1.32 seconds
Started Apr 21 12:46:45 PM PDT 24
Finished Apr 21 12:46:47 PM PDT 24
Peak memory 196580 kb
Host smart-7f5c5baf-63cf-47cd-8f57-e9678ce67e62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3914059366 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_smoke.3914059366
Directory /workspace/20.gpio_smoke/latest

Test location /workspace/coverage/default/20.gpio_smoke_no_pullup_pulldown.711061730
Short name T34
Test name
Test status
Simulation time 167340162 ps
CPU time 0.94 seconds
Started Apr 21 12:46:38 PM PDT 24
Finished Apr 21 12:46:40 PM PDT 24
Peak memory 195552 kb
Host smart-b15fbeb2-e701-4561-8ca0-c50f63f649e3
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=711061730 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_no_pullup_pulldown.711061730
Directory /workspace/20.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/20.gpio_stress_all.3597482986
Short name T2
Test name
Test status
Simulation time 30101644208 ps
CPU time 159.11 seconds
Started Apr 21 12:46:40 PM PDT 24
Finished Apr 21 12:49:20 PM PDT 24
Peak memory 198204 kb
Host smart-95b77651-157d-4bf5-9b6f-5d9e1fa3f3b1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3597482986 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.
gpio_stress_all.3597482986
Directory /workspace/20.gpio_stress_all/latest

Test location /workspace/coverage/default/21.gpio_alert_test.4180549271
Short name T600
Test name
Test status
Simulation time 36752399 ps
CPU time 0.56 seconds
Started Apr 21 12:46:48 PM PDT 24
Finished Apr 21 12:46:50 PM PDT 24
Peak memory 193556 kb
Host smart-a62888c6-2c79-4e6c-a93d-ecda634f5f4d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4180549271 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_alert_test.4180549271
Directory /workspace/21.gpio_alert_test/latest

Test location /workspace/coverage/default/21.gpio_dout_din_regs_random_rw.2220313666
Short name T145
Test name
Test status
Simulation time 52629550 ps
CPU time 0.74 seconds
Started Apr 21 12:46:45 PM PDT 24
Finished Apr 21 12:46:47 PM PDT 24
Peak memory 195580 kb
Host smart-616bd3d1-b489-4bc5-b2d4-15b0fa6ad004
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2220313666 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_dout_din_regs_random_rw.2220313666
Directory /workspace/21.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/21.gpio_filter_stress.3036983384
Short name T622
Test name
Test status
Simulation time 773451471 ps
CPU time 21.89 seconds
Started Apr 21 12:46:45 PM PDT 24
Finished Apr 21 12:47:08 PM PDT 24
Peak memory 195700 kb
Host smart-8bd831b5-c667-4a13-b08d-458b306fd573
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3036983384 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_filter_stre
ss.3036983384
Directory /workspace/21.gpio_filter_stress/latest

Test location /workspace/coverage/default/21.gpio_full_random.4179859544
Short name T581
Test name
Test status
Simulation time 63030436 ps
CPU time 1.01 seconds
Started Apr 21 12:46:44 PM PDT 24
Finished Apr 21 12:46:46 PM PDT 24
Peak memory 196612 kb
Host smart-953d8765-b1ac-4106-bbac-9b59d24e8966
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4179859544 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_full_random.4179859544
Directory /workspace/21.gpio_full_random/latest

Test location /workspace/coverage/default/21.gpio_intr_rand_pgm.4111435755
Short name T277
Test name
Test status
Simulation time 118249239 ps
CPU time 1.17 seconds
Started Apr 21 12:46:46 PM PDT 24
Finished Apr 21 12:46:47 PM PDT 24
Peak memory 195956 kb
Host smart-4b13bf3d-cda9-4d13-a24d-5976601d3587
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4111435755 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_intr_rand_pgm.4111435755
Directory /workspace/21.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/21.gpio_intr_with_filter_rand_intr_event.1684454779
Short name T236
Test name
Test status
Simulation time 87041758 ps
CPU time 3.39 seconds
Started Apr 21 12:46:46 PM PDT 24
Finished Apr 21 12:46:50 PM PDT 24
Peak memory 198340 kb
Host smart-6362f54b-dd27-47ef-9dad-21cded811cc4
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1684454779 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 21.gpio_intr_with_filter_rand_intr_event.1684454779
Directory /workspace/21.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/21.gpio_rand_intr_trigger.158765594
Short name T571
Test name
Test status
Simulation time 93357327 ps
CPU time 2.07 seconds
Started Apr 21 12:46:51 PM PDT 24
Finished Apr 21 12:46:54 PM PDT 24
Peak memory 195980 kb
Host smart-6d3b33a0-9416-4319-9a06-d86909c4dd5b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=158765594 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_rand_intr_trigger.
158765594
Directory /workspace/21.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/21.gpio_random_dout_din.76424485
Short name T434
Test name
Test status
Simulation time 21129756 ps
CPU time 0.83 seconds
Started Apr 21 12:46:51 PM PDT 24
Finished Apr 21 12:46:52 PM PDT 24
Peak memory 196660 kb
Host smart-2874c356-5e9e-40c2-a23d-fa704b0287e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=76424485 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_random_dout_din.76424485
Directory /workspace/21.gpio_random_dout_din/latest

Test location /workspace/coverage/default/21.gpio_random_dout_din_no_pullup_pulldown.2578274536
Short name T607
Test name
Test status
Simulation time 96444276 ps
CPU time 0.78 seconds
Started Apr 21 12:46:43 PM PDT 24
Finished Apr 21 12:46:44 PM PDT 24
Peak memory 195616 kb
Host smart-7b8e57a6-2e5f-4aed-bfe8-4b331d373d8f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2578274536 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_random_dout_din_no_pullu
p_pulldown.2578274536
Directory /workspace/21.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/21.gpio_random_long_reg_writes_reg_reads.2866267630
Short name T258
Test name
Test status
Simulation time 333523547 ps
CPU time 1.77 seconds
Started Apr 21 12:46:45 PM PDT 24
Finished Apr 21 12:46:48 PM PDT 24
Peak memory 197760 kb
Host smart-2b8ab333-5d63-4ed8-a8fa-336fb5acad3a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2866267630 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_ra
ndom_long_reg_writes_reg_reads.2866267630
Directory /workspace/21.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/21.gpio_smoke.1835270123
Short name T298
Test name
Test status
Simulation time 40173588 ps
CPU time 0.97 seconds
Started Apr 21 12:46:42 PM PDT 24
Finished Apr 21 12:46:43 PM PDT 24
Peak memory 196596 kb
Host smart-6b50f0d2-fb6d-42be-a0aa-2d64c0d8334f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1835270123 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_smoke.1835270123
Directory /workspace/21.gpio_smoke/latest

Test location /workspace/coverage/default/21.gpio_smoke_no_pullup_pulldown.1084696117
Short name T533
Test name
Test status
Simulation time 164744736 ps
CPU time 0.97 seconds
Started Apr 21 12:46:48 PM PDT 24
Finished Apr 21 12:46:50 PM PDT 24
Peak memory 196740 kb
Host smart-00f2326c-0451-45f0-9db8-f1ee88113da0
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1084696117 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_no_pullup_pulldown.1084696117
Directory /workspace/21.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/21.gpio_stress_all.3369125152
Short name T326
Test name
Test status
Simulation time 2084045020 ps
CPU time 53.34 seconds
Started Apr 21 12:46:45 PM PDT 24
Finished Apr 21 12:47:39 PM PDT 24
Peak memory 198220 kb
Host smart-84eac90c-b7e5-477a-a236-c5fb55e7b4c9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3369125152 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.
gpio_stress_all.3369125152
Directory /workspace/21.gpio_stress_all/latest

Test location /workspace/coverage/default/21.gpio_stress_all_with_rand_reset.1540870231
Short name T35
Test name
Test status
Simulation time 31096872461 ps
CPU time 551.78 seconds
Started Apr 21 12:46:45 PM PDT 24
Finished Apr 21 12:55:58 PM PDT 24
Peak memory 198316 kb
Host smart-0459ff9e-2737-4373-b493-6a810ff8d934
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1540870231 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_stress_all_with_rand_reset.1540870231
Directory /workspace/21.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.gpio_alert_test.3635787752
Short name T252
Test name
Test status
Simulation time 36867674 ps
CPU time 0.55 seconds
Started Apr 21 12:46:50 PM PDT 24
Finished Apr 21 12:46:51 PM PDT 24
Peak memory 194692 kb
Host smart-7aba6870-bea9-4ef7-9b81-b47b1cb6d168
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3635787752 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_alert_test.3635787752
Directory /workspace/22.gpio_alert_test/latest

Test location /workspace/coverage/default/22.gpio_dout_din_regs_random_rw.1286473980
Short name T557
Test name
Test status
Simulation time 131294579 ps
CPU time 0.88 seconds
Started Apr 21 12:46:46 PM PDT 24
Finished Apr 21 12:46:48 PM PDT 24
Peak memory 196688 kb
Host smart-6b759c21-1ef0-495d-ad63-49bffa7305c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1286473980 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_dout_din_regs_random_rw.1286473980
Directory /workspace/22.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/22.gpio_filter_stress.2841351128
Short name T508
Test name
Test status
Simulation time 2154960400 ps
CPU time 27.45 seconds
Started Apr 21 12:46:47 PM PDT 24
Finished Apr 21 12:47:15 PM PDT 24
Peak memory 196928 kb
Host smart-eeb30c5f-e10f-4958-b695-9a1f62f6e178
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2841351128 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_filter_stre
ss.2841351128
Directory /workspace/22.gpio_filter_stress/latest

Test location /workspace/coverage/default/22.gpio_full_random.2615290182
Short name T564
Test name
Test status
Simulation time 114524559 ps
CPU time 0.91 seconds
Started Apr 21 12:46:45 PM PDT 24
Finished Apr 21 12:46:46 PM PDT 24
Peak memory 196908 kb
Host smart-58f11b26-b585-492a-bccb-4dddc50b43db
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2615290182 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_full_random.2615290182
Directory /workspace/22.gpio_full_random/latest

Test location /workspace/coverage/default/22.gpio_intr_rand_pgm.1431004577
Short name T426
Test name
Test status
Simulation time 122913860 ps
CPU time 1.14 seconds
Started Apr 21 12:46:49 PM PDT 24
Finished Apr 21 12:46:51 PM PDT 24
Peak memory 196188 kb
Host smart-285a5d6b-8dec-4742-8ca0-77c737a00638
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1431004577 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_intr_rand_pgm.1431004577
Directory /workspace/22.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/22.gpio_intr_with_filter_rand_intr_event.3660985784
Short name T354
Test name
Test status
Simulation time 974666797 ps
CPU time 3.16 seconds
Started Apr 21 12:46:47 PM PDT 24
Finished Apr 21 12:46:50 PM PDT 24
Peak memory 196720 kb
Host smart-1d3479c3-b4a6-448b-b526-68ea4a98250c
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3660985784 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 22.gpio_intr_with_filter_rand_intr_event.3660985784
Directory /workspace/22.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/22.gpio_rand_intr_trigger.1518029387
Short name T267
Test name
Test status
Simulation time 893601339 ps
CPU time 2.39 seconds
Started Apr 21 12:46:43 PM PDT 24
Finished Apr 21 12:46:46 PM PDT 24
Peak memory 197388 kb
Host smart-532d6d28-0fda-447c-8a43-b92db44be6ce
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1518029387 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_rand_intr_trigger
.1518029387
Directory /workspace/22.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/22.gpio_random_dout_din.588312261
Short name T389
Test name
Test status
Simulation time 20037149 ps
CPU time 0.84 seconds
Started Apr 21 12:46:45 PM PDT 24
Finished Apr 21 12:46:47 PM PDT 24
Peak memory 197452 kb
Host smart-af379c31-8163-40fb-a303-713d3c5f2058
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=588312261 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_random_dout_din.588312261
Directory /workspace/22.gpio_random_dout_din/latest

Test location /workspace/coverage/default/22.gpio_random_dout_din_no_pullup_pulldown.2086740488
Short name T650
Test name
Test status
Simulation time 16488812 ps
CPU time 0.68 seconds
Started Apr 21 12:46:44 PM PDT 24
Finished Apr 21 12:46:45 PM PDT 24
Peak memory 195244 kb
Host smart-df1eff75-3bc7-41e8-82d7-915340937fee
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2086740488 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_random_dout_din_no_pullu
p_pulldown.2086740488
Directory /workspace/22.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/22.gpio_random_long_reg_writes_reg_reads.980582221
Short name T688
Test name
Test status
Simulation time 134150975 ps
CPU time 3.15 seconds
Started Apr 21 12:46:49 PM PDT 24
Finished Apr 21 12:46:53 PM PDT 24
Peak memory 198056 kb
Host smart-666d9c6b-7634-4d60-ab76-bd92cde17ff6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=980582221 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_ran
dom_long_reg_writes_reg_reads.980582221
Directory /workspace/22.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/22.gpio_smoke.2852014355
Short name T49
Test name
Test status
Simulation time 106515775 ps
CPU time 1.14 seconds
Started Apr 21 12:46:48 PM PDT 24
Finished Apr 21 12:46:49 PM PDT 24
Peak memory 195864 kb
Host smart-e78e476f-593c-4239-a4c8-06b1a35c2745
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2852014355 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_smoke.2852014355
Directory /workspace/22.gpio_smoke/latest

Test location /workspace/coverage/default/22.gpio_smoke_no_pullup_pulldown.3750331515
Short name T642
Test name
Test status
Simulation time 277385329 ps
CPU time 0.94 seconds
Started Apr 21 12:46:43 PM PDT 24
Finished Apr 21 12:46:45 PM PDT 24
Peak memory 195448 kb
Host smart-a994b574-4217-42c7-92fc-395883b1362c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3750331515 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_no_pullup_pulldown.3750331515
Directory /workspace/22.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/22.gpio_stress_all.1380334770
Short name T110
Test name
Test status
Simulation time 17107638045 ps
CPU time 226.27 seconds
Started Apr 21 12:46:47 PM PDT 24
Finished Apr 21 12:50:34 PM PDT 24
Peak memory 198388 kb
Host smart-dcc2e7ee-7e84-4287-857c-80254d410220
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1380334770 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.
gpio_stress_all.1380334770
Directory /workspace/22.gpio_stress_all/latest

Test location /workspace/coverage/default/22.gpio_stress_all_with_rand_reset.3805544253
Short name T90
Test name
Test status
Simulation time 24449107212 ps
CPU time 447.11 seconds
Started Apr 21 12:46:46 PM PDT 24
Finished Apr 21 12:54:14 PM PDT 24
Peak memory 198316 kb
Host smart-a9eab53c-e5bc-4ef0-a223-e583a5e7b0b6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3805544253 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_stress_all_with_rand_reset.3805544253
Directory /workspace/22.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.gpio_alert_test.3291095063
Short name T507
Test name
Test status
Simulation time 13343808 ps
CPU time 0.58 seconds
Started Apr 21 12:46:49 PM PDT 24
Finished Apr 21 12:46:50 PM PDT 24
Peak memory 194144 kb
Host smart-7add5bd7-d4bc-490c-b03a-4df9f987a298
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3291095063 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_alert_test.3291095063
Directory /workspace/23.gpio_alert_test/latest

Test location /workspace/coverage/default/23.gpio_dout_din_regs_random_rw.679454963
Short name T180
Test name
Test status
Simulation time 103656219 ps
CPU time 0.84 seconds
Started Apr 21 12:46:47 PM PDT 24
Finished Apr 21 12:46:49 PM PDT 24
Peak memory 195412 kb
Host smart-0cc92876-b768-4ff6-b31e-26381db26526
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=679454963 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_dout_din_regs_random_rw.679454963
Directory /workspace/23.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/23.gpio_filter_stress.4048924195
Short name T456
Test name
Test status
Simulation time 1078853180 ps
CPU time 7.48 seconds
Started Apr 21 12:46:51 PM PDT 24
Finished Apr 21 12:46:59 PM PDT 24
Peak memory 195660 kb
Host smart-50f74b45-3ce8-4f3f-a35b-46e7849f6c8f
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4048924195 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_filter_stre
ss.4048924195
Directory /workspace/23.gpio_filter_stress/latest

Test location /workspace/coverage/default/23.gpio_full_random.1700696119
Short name T680
Test name
Test status
Simulation time 276736539 ps
CPU time 0.98 seconds
Started Apr 21 12:46:42 PM PDT 24
Finished Apr 21 12:46:43 PM PDT 24
Peak memory 197780 kb
Host smart-7517b7b1-b28e-4e6a-be69-bc77632ffb4a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1700696119 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_full_random.1700696119
Directory /workspace/23.gpio_full_random/latest

Test location /workspace/coverage/default/23.gpio_intr_rand_pgm.115287935
Short name T148
Test name
Test status
Simulation time 109597967 ps
CPU time 0.98 seconds
Started Apr 21 12:46:44 PM PDT 24
Finished Apr 21 12:46:45 PM PDT 24
Peak memory 196220 kb
Host smart-00765e56-6718-45fc-ba57-a7dfb48da0c5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115287935 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_intr_rand_pgm.115287935
Directory /workspace/23.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/23.gpio_intr_with_filter_rand_intr_event.1508098251
Short name T597
Test name
Test status
Simulation time 93001765 ps
CPU time 3.71 seconds
Started Apr 21 12:46:42 PM PDT 24
Finished Apr 21 12:46:46 PM PDT 24
Peak memory 198216 kb
Host smart-1c028528-9a12-463c-811a-dd3b2fc62144
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1508098251 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 23.gpio_intr_with_filter_rand_intr_event.1508098251
Directory /workspace/23.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/23.gpio_rand_intr_trigger.2668348679
Short name T47
Test name
Test status
Simulation time 95715316 ps
CPU time 2.46 seconds
Started Apr 21 12:46:48 PM PDT 24
Finished Apr 21 12:46:51 PM PDT 24
Peak memory 196728 kb
Host smart-9549fbf7-9478-45ac-9fb4-b499383487a3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2668348679 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_rand_intr_trigger
.2668348679
Directory /workspace/23.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/23.gpio_random_dout_din.1044235208
Short name T696
Test name
Test status
Simulation time 233377763 ps
CPU time 1.05 seconds
Started Apr 21 12:46:44 PM PDT 24
Finished Apr 21 12:46:45 PM PDT 24
Peak memory 196120 kb
Host smart-50e51d14-6fe7-486a-a5e4-66dcf9d09c26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1044235208 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_random_dout_din.1044235208
Directory /workspace/23.gpio_random_dout_din/latest

Test location /workspace/coverage/default/23.gpio_random_dout_din_no_pullup_pulldown.1851899979
Short name T172
Test name
Test status
Simulation time 139800106 ps
CPU time 1.23 seconds
Started Apr 21 12:46:44 PM PDT 24
Finished Apr 21 12:46:45 PM PDT 24
Peak memory 196000 kb
Host smart-b9994dcc-65a8-4e42-81ee-164721c97758
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1851899979 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_random_dout_din_no_pullu
p_pulldown.1851899979
Directory /workspace/23.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/23.gpio_random_long_reg_writes_reg_reads.2206418425
Short name T3
Test name
Test status
Simulation time 278765316 ps
CPU time 1.42 seconds
Started Apr 21 12:46:52 PM PDT 24
Finished Apr 21 12:46:54 PM PDT 24
Peak memory 198004 kb
Host smart-d2c49fda-3e3e-43bd-bc4b-a37c613d898c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2206418425 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_ra
ndom_long_reg_writes_reg_reads.2206418425
Directory /workspace/23.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/23.gpio_smoke.2652297826
Short name T260
Test name
Test status
Simulation time 97601061 ps
CPU time 1.44 seconds
Started Apr 21 12:46:50 PM PDT 24
Finished Apr 21 12:46:52 PM PDT 24
Peak memory 195712 kb
Host smart-1a862b78-6103-43cc-b93d-99c74e799af8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2652297826 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_smoke.2652297826
Directory /workspace/23.gpio_smoke/latest

Test location /workspace/coverage/default/23.gpio_smoke_no_pullup_pulldown.4031902770
Short name T268
Test name
Test status
Simulation time 64009181 ps
CPU time 1 seconds
Started Apr 21 12:46:49 PM PDT 24
Finished Apr 21 12:46:51 PM PDT 24
Peak memory 196488 kb
Host smart-a056cfa2-559d-427d-841b-ec1494f5023b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4031902770 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_no_pullup_pulldown.4031902770
Directory /workspace/23.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/23.gpio_stress_all.3094639774
Short name T692
Test name
Test status
Simulation time 1593206468 ps
CPU time 21.99 seconds
Started Apr 21 12:46:44 PM PDT 24
Finished Apr 21 12:47:06 PM PDT 24
Peak memory 198156 kb
Host smart-77b73f36-85c7-43a9-9839-bac84411a037
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3094639774 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.
gpio_stress_all.3094639774
Directory /workspace/23.gpio_stress_all/latest

Test location /workspace/coverage/default/23.gpio_stress_all_with_rand_reset.1867868074
Short name T136
Test name
Test status
Simulation time 134884522045 ps
CPU time 2130.05 seconds
Started Apr 21 12:46:52 PM PDT 24
Finished Apr 21 01:22:23 PM PDT 24
Peak memory 198356 kb
Host smart-f0a02821-abcc-4310-9a74-aa649a0f2a44
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1867868074 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_stress_all_with_rand_reset.1867868074
Directory /workspace/23.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.gpio_alert_test.3265474223
Short name T697
Test name
Test status
Simulation time 19361941 ps
CPU time 0.6 seconds
Started Apr 21 12:46:50 PM PDT 24
Finished Apr 21 12:46:51 PM PDT 24
Peak memory 194916 kb
Host smart-5b800783-216a-4623-91c8-5bb4d9c71599
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3265474223 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_alert_test.3265474223
Directory /workspace/24.gpio_alert_test/latest

Test location /workspace/coverage/default/24.gpio_dout_din_regs_random_rw.3667369886
Short name T80
Test name
Test status
Simulation time 245586714 ps
CPU time 0.75 seconds
Started Apr 21 12:46:51 PM PDT 24
Finished Apr 21 12:46:53 PM PDT 24
Peak memory 196204 kb
Host smart-ec5347f5-f22e-4808-bfaa-8f435c9b0f35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3667369886 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_dout_din_regs_random_rw.3667369886
Directory /workspace/24.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/24.gpio_filter_stress.2017855649
Short name T12
Test name
Test status
Simulation time 514426481 ps
CPU time 9 seconds
Started Apr 21 12:46:51 PM PDT 24
Finished Apr 21 12:47:01 PM PDT 24
Peak memory 195676 kb
Host smart-b3f78ee0-5495-4067-9a68-14dab7445d4c
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2017855649 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_filter_stre
ss.2017855649
Directory /workspace/24.gpio_filter_stress/latest

Test location /workspace/coverage/default/24.gpio_full_random.4151591069
Short name T577
Test name
Test status
Simulation time 569751297 ps
CPU time 0.91 seconds
Started Apr 21 12:46:49 PM PDT 24
Finished Apr 21 12:46:51 PM PDT 24
Peak memory 197416 kb
Host smart-eb5659d8-223e-4111-be24-98c4642788f4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4151591069 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_full_random.4151591069
Directory /workspace/24.gpio_full_random/latest

Test location /workspace/coverage/default/24.gpio_intr_rand_pgm.3878464380
Short name T337
Test name
Test status
Simulation time 213735547 ps
CPU time 1.43 seconds
Started Apr 21 12:46:47 PM PDT 24
Finished Apr 21 12:46:49 PM PDT 24
Peak memory 197232 kb
Host smart-df86f07a-d75d-4092-9e77-ed86b973c45c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3878464380 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_intr_rand_pgm.3878464380
Directory /workspace/24.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/24.gpio_intr_with_filter_rand_intr_event.973502184
Short name T506
Test name
Test status
Simulation time 173741515 ps
CPU time 3.52 seconds
Started Apr 21 12:46:49 PM PDT 24
Finished Apr 21 12:46:54 PM PDT 24
Peak memory 198264 kb
Host smart-e755c7a4-133b-43ae-aa8a-9aea1f81b1c4
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=973502184 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 24.gpio_intr_with_filter_rand_intr_event.973502184
Directory /workspace/24.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/24.gpio_rand_intr_trigger.361351019
Short name T76
Test name
Test status
Simulation time 62822169 ps
CPU time 1.23 seconds
Started Apr 21 12:46:49 PM PDT 24
Finished Apr 21 12:46:51 PM PDT 24
Peak memory 197444 kb
Host smart-e80ed150-9d22-4b3f-b136-bc9a85bfba73
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=361351019 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_rand_intr_trigger.
361351019
Directory /workspace/24.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/24.gpio_random_dout_din.133320658
Short name T303
Test name
Test status
Simulation time 15025153 ps
CPU time 0.66 seconds
Started Apr 21 12:46:49 PM PDT 24
Finished Apr 21 12:46:51 PM PDT 24
Peak memory 195548 kb
Host smart-1d5bc584-0755-498a-8227-ea6750e83716
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=133320658 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_random_dout_din.133320658
Directory /workspace/24.gpio_random_dout_din/latest

Test location /workspace/coverage/default/24.gpio_random_dout_din_no_pullup_pulldown.3231219897
Short name T441
Test name
Test status
Simulation time 28800804 ps
CPU time 0.77 seconds
Started Apr 21 12:46:49 PM PDT 24
Finished Apr 21 12:46:50 PM PDT 24
Peak memory 196420 kb
Host smart-52057a07-902a-4c6a-ab60-99e52021d2e8
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3231219897 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_random_dout_din_no_pullu
p_pulldown.3231219897
Directory /workspace/24.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/24.gpio_random_long_reg_writes_reg_reads.134471323
Short name T367
Test name
Test status
Simulation time 214733099 ps
CPU time 1.64 seconds
Started Apr 21 12:46:48 PM PDT 24
Finished Apr 21 12:46:51 PM PDT 24
Peak memory 198184 kb
Host smart-1d581d7d-c6b7-4fa8-9120-60c515b8fca9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=134471323 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_ran
dom_long_reg_writes_reg_reads.134471323
Directory /workspace/24.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/24.gpio_smoke.4020278456
Short name T405
Test name
Test status
Simulation time 23822119 ps
CPU time 0.84 seconds
Started Apr 21 12:46:52 PM PDT 24
Finished Apr 21 12:46:54 PM PDT 24
Peak memory 196656 kb
Host smart-b24d7f20-83a1-4483-8a1a-3dbd4adc745d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4020278456 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_smoke.4020278456
Directory /workspace/24.gpio_smoke/latest

Test location /workspace/coverage/default/24.gpio_smoke_no_pullup_pulldown.499042496
Short name T204
Test name
Test status
Simulation time 61458244 ps
CPU time 1.21 seconds
Started Apr 21 12:46:48 PM PDT 24
Finished Apr 21 12:46:50 PM PDT 24
Peak memory 196040 kb
Host smart-bed2ea66-467b-483f-8d60-2d36aabc3eed
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=499042496 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_no_pullup_pulldown.499042496
Directory /workspace/24.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/24.gpio_stress_all.3946562265
Short name T362
Test name
Test status
Simulation time 14891192882 ps
CPU time 180.58 seconds
Started Apr 21 12:46:51 PM PDT 24
Finished Apr 21 12:49:53 PM PDT 24
Peak memory 198380 kb
Host smart-58793b9e-3005-4e64-9f4d-6f92ce7121aa
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3946562265 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.
gpio_stress_all.3946562265
Directory /workspace/24.gpio_stress_all/latest

Test location /workspace/coverage/default/24.gpio_stress_all_with_rand_reset.2424251806
Short name T84
Test name
Test status
Simulation time 41558984498 ps
CPU time 815.9 seconds
Started Apr 21 12:46:55 PM PDT 24
Finished Apr 21 01:00:31 PM PDT 24
Peak memory 198288 kb
Host smart-489c41f9-e119-4def-a80a-4122007d888e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2424251806 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_stress_all_with_rand_reset.2424251806
Directory /workspace/24.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.gpio_alert_test.3833525217
Short name T63
Test name
Test status
Simulation time 81783636 ps
CPU time 0.57 seconds
Started Apr 21 12:46:49 PM PDT 24
Finished Apr 21 12:46:50 PM PDT 24
Peak memory 194860 kb
Host smart-be2af2ac-8484-45fc-8f77-f7a97382421b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3833525217 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_alert_test.3833525217
Directory /workspace/25.gpio_alert_test/latest

Test location /workspace/coverage/default/25.gpio_dout_din_regs_random_rw.2871556227
Short name T691
Test name
Test status
Simulation time 46155423 ps
CPU time 0.88 seconds
Started Apr 21 12:46:52 PM PDT 24
Finished Apr 21 12:46:54 PM PDT 24
Peak memory 195568 kb
Host smart-37d3a1c8-e6de-439a-80bd-9510a3068ad1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2871556227 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_dout_din_regs_random_rw.2871556227
Directory /workspace/25.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/25.gpio_filter_stress.369729612
Short name T276
Test name
Test status
Simulation time 388860147 ps
CPU time 5.07 seconds
Started Apr 21 12:46:48 PM PDT 24
Finished Apr 21 12:46:54 PM PDT 24
Peak memory 195852 kb
Host smart-903f6c6c-eab8-4ddd-83c4-ffd2b54d9eab
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=369729612 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_filter_stres
s.369729612
Directory /workspace/25.gpio_filter_stress/latest

Test location /workspace/coverage/default/25.gpio_full_random.3557119140
Short name T361
Test name
Test status
Simulation time 35782171 ps
CPU time 0.7 seconds
Started Apr 21 12:46:50 PM PDT 24
Finished Apr 21 12:46:51 PM PDT 24
Peak memory 194892 kb
Host smart-b8cb431f-2926-43bd-a264-f7bedbf5b5c5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3557119140 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_full_random.3557119140
Directory /workspace/25.gpio_full_random/latest

Test location /workspace/coverage/default/25.gpio_intr_rand_pgm.3112234770
Short name T378
Test name
Test status
Simulation time 52086303 ps
CPU time 1.26 seconds
Started Apr 21 12:46:50 PM PDT 24
Finished Apr 21 12:46:52 PM PDT 24
Peak memory 197416 kb
Host smart-f91028ad-2d39-47e3-a9c0-fd8f0814162e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3112234770 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_intr_rand_pgm.3112234770
Directory /workspace/25.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/25.gpio_intr_with_filter_rand_intr_event.181420308
Short name T525
Test name
Test status
Simulation time 128841139 ps
CPU time 1.62 seconds
Started Apr 21 12:46:51 PM PDT 24
Finished Apr 21 12:46:54 PM PDT 24
Peak memory 198268 kb
Host smart-29109ea9-8163-44ba-af64-62f6e7bf23bd
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=181420308 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 25.gpio_intr_with_filter_rand_intr_event.181420308
Directory /workspace/25.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/25.gpio_rand_intr_trigger.1325412246
Short name T223
Test name
Test status
Simulation time 112597975 ps
CPU time 3.33 seconds
Started Apr 21 12:46:57 PM PDT 24
Finished Apr 21 12:47:01 PM PDT 24
Peak memory 197116 kb
Host smart-c3ce24ea-ce04-4a61-acbd-c7dd4fdc5e72
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1325412246 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_rand_intr_trigger
.1325412246
Directory /workspace/25.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/25.gpio_random_dout_din.1607301098
Short name T609
Test name
Test status
Simulation time 61479919 ps
CPU time 0.8 seconds
Started Apr 21 12:46:50 PM PDT 24
Finished Apr 21 12:46:51 PM PDT 24
Peak memory 195480 kb
Host smart-f9688a4c-d1ee-4d6d-90e1-e0a47b657884
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1607301098 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_random_dout_din.1607301098
Directory /workspace/25.gpio_random_dout_din/latest

Test location /workspace/coverage/default/25.gpio_random_dout_din_no_pullup_pulldown.3251901848
Short name T217
Test name
Test status
Simulation time 21349384 ps
CPU time 0.7 seconds
Started Apr 21 12:46:47 PM PDT 24
Finished Apr 21 12:46:49 PM PDT 24
Peak memory 194404 kb
Host smart-afdcf028-16e2-475b-aad4-ab69b34fa188
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3251901848 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_random_dout_din_no_pullu
p_pulldown.3251901848
Directory /workspace/25.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/25.gpio_random_long_reg_writes_reg_reads.1830180358
Short name T81
Test name
Test status
Simulation time 377659588 ps
CPU time 4.25 seconds
Started Apr 21 12:46:48 PM PDT 24
Finished Apr 21 12:46:53 PM PDT 24
Peak memory 198136 kb
Host smart-3de18945-e8af-4a94-9b1a-79e180a5a880
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1830180358 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_ra
ndom_long_reg_writes_reg_reads.1830180358
Directory /workspace/25.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/25.gpio_smoke.20642015
Short name T99
Test name
Test status
Simulation time 68891012 ps
CPU time 1.37 seconds
Started Apr 21 12:46:54 PM PDT 24
Finished Apr 21 12:46:56 PM PDT 24
Peak memory 198140 kb
Host smart-29250ebe-a27f-4874-baf2-f050bcaeab69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=20642015 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_smoke.20642015
Directory /workspace/25.gpio_smoke/latest

Test location /workspace/coverage/default/25.gpio_smoke_no_pullup_pulldown.35455914
Short name T497
Test name
Test status
Simulation time 28453536 ps
CPU time 1.15 seconds
Started Apr 21 12:46:51 PM PDT 24
Finished Apr 21 12:46:53 PM PDT 24
Peak memory 196600 kb
Host smart-2dce0c48-0bea-4222-9fdb-9a0dd9546ac0
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35455914 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_no_pullup_pulldown.35455914
Directory /workspace/25.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/25.gpio_stress_all.2805468238
Short name T44
Test name
Test status
Simulation time 14566600379 ps
CPU time 212.6 seconds
Started Apr 21 12:47:01 PM PDT 24
Finished Apr 21 12:50:34 PM PDT 24
Peak memory 198292 kb
Host smart-909d65db-1ac0-4e1d-a883-1f849a7e47f8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2805468238 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.
gpio_stress_all.2805468238
Directory /workspace/25.gpio_stress_all/latest

Test location /workspace/coverage/default/25.gpio_stress_all_with_rand_reset.3517701947
Short name T570
Test name
Test status
Simulation time 185041152381 ps
CPU time 2062.98 seconds
Started Apr 21 12:46:54 PM PDT 24
Finished Apr 21 01:21:17 PM PDT 24
Peak memory 198340 kb
Host smart-5309944f-55e0-4779-873a-569b23299dad
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3517701947 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_stress_all_with_rand_reset.3517701947
Directory /workspace/25.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.gpio_alert_test.2787205290
Short name T396
Test name
Test status
Simulation time 19345884 ps
CPU time 0.57 seconds
Started Apr 21 12:46:54 PM PDT 24
Finished Apr 21 12:46:55 PM PDT 24
Peak memory 194052 kb
Host smart-6d5a4d93-0bd5-4d82-a53e-b5695e1052b2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2787205290 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_alert_test.2787205290
Directory /workspace/26.gpio_alert_test/latest

Test location /workspace/coverage/default/26.gpio_dout_din_regs_random_rw.3626736287
Short name T306
Test name
Test status
Simulation time 273301579 ps
CPU time 0.85 seconds
Started Apr 21 12:46:55 PM PDT 24
Finished Apr 21 12:46:56 PM PDT 24
Peak memory 196444 kb
Host smart-31e1b908-2e19-4c14-99e6-c4f5596e7ccf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3626736287 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_dout_din_regs_random_rw.3626736287
Directory /workspace/26.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/26.gpio_filter_stress.1679238861
Short name T420
Test name
Test status
Simulation time 80768051 ps
CPU time 3.96 seconds
Started Apr 21 12:46:53 PM PDT 24
Finished Apr 21 12:46:57 PM PDT 24
Peak memory 196732 kb
Host smart-150cc6b0-eeb1-4d59-bc32-5a430669b5d0
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1679238861 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_filter_stre
ss.1679238861
Directory /workspace/26.gpio_filter_stress/latest

Test location /workspace/coverage/default/26.gpio_full_random.1910949449
Short name T7
Test name
Test status
Simulation time 80260616 ps
CPU time 0.99 seconds
Started Apr 21 12:47:01 PM PDT 24
Finished Apr 21 12:47:03 PM PDT 24
Peak memory 196320 kb
Host smart-283de0b3-acf4-4a40-b936-19337b5f57a6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1910949449 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_full_random.1910949449
Directory /workspace/26.gpio_full_random/latest

Test location /workspace/coverage/default/26.gpio_intr_rand_pgm.2121886446
Short name T79
Test name
Test status
Simulation time 345616250 ps
CPU time 0.74 seconds
Started Apr 21 12:46:52 PM PDT 24
Finished Apr 21 12:46:53 PM PDT 24
Peak memory 195708 kb
Host smart-a64d3adc-2124-48db-a550-b34206fa917f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2121886446 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_intr_rand_pgm.2121886446
Directory /workspace/26.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/26.gpio_intr_with_filter_rand_intr_event.3147244227
Short name T509
Test name
Test status
Simulation time 52272131 ps
CPU time 2.15 seconds
Started Apr 21 12:46:56 PM PDT 24
Finished Apr 21 12:46:59 PM PDT 24
Peak memory 198272 kb
Host smart-f1058071-2d07-4032-a52a-68cfbb2023eb
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3147244227 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 26.gpio_intr_with_filter_rand_intr_event.3147244227
Directory /workspace/26.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/26.gpio_rand_intr_trigger.1724503025
Short name T342
Test name
Test status
Simulation time 160740892 ps
CPU time 1.23 seconds
Started Apr 21 12:46:54 PM PDT 24
Finished Apr 21 12:46:56 PM PDT 24
Peak memory 197664 kb
Host smart-e08b8c63-ab2e-4240-804e-4aa72fc60ed5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1724503025 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_rand_intr_trigger
.1724503025
Directory /workspace/26.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/26.gpio_random_dout_din.430000479
Short name T279
Test name
Test status
Simulation time 182614900 ps
CPU time 1.24 seconds
Started Apr 21 12:47:02 PM PDT 24
Finished Apr 21 12:47:04 PM PDT 24
Peak memory 196732 kb
Host smart-870f3bf8-7398-4691-ada1-adebbd72bc0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=430000479 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_random_dout_din.430000479
Directory /workspace/26.gpio_random_dout_din/latest

Test location /workspace/coverage/default/26.gpio_random_dout_din_no_pullup_pulldown.3787995890
Short name T412
Test name
Test status
Simulation time 78513650 ps
CPU time 0.73 seconds
Started Apr 21 12:47:02 PM PDT 24
Finished Apr 21 12:47:04 PM PDT 24
Peak memory 195584 kb
Host smart-3d1f65e1-8131-4561-9a8b-906b818e7084
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3787995890 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_random_dout_din_no_pullu
p_pulldown.3787995890
Directory /workspace/26.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/26.gpio_random_long_reg_writes_reg_reads.1088874904
Short name T234
Test name
Test status
Simulation time 352437636 ps
CPU time 4.33 seconds
Started Apr 21 12:47:02 PM PDT 24
Finished Apr 21 12:47:07 PM PDT 24
Peak memory 198168 kb
Host smart-4e48e1dc-cd30-4ac4-8d99-c8d64663bf53
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1088874904 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_ra
ndom_long_reg_writes_reg_reads.1088874904
Directory /workspace/26.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/26.gpio_smoke.2471658843
Short name T463
Test name
Test status
Simulation time 269028677 ps
CPU time 1.11 seconds
Started Apr 21 12:46:52 PM PDT 24
Finished Apr 21 12:46:54 PM PDT 24
Peak memory 195888 kb
Host smart-9d289179-0acc-4503-9522-df956860dbfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2471658843 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_smoke.2471658843
Directory /workspace/26.gpio_smoke/latest

Test location /workspace/coverage/default/26.gpio_smoke_no_pullup_pulldown.3326889957
Short name T324
Test name
Test status
Simulation time 67036065 ps
CPU time 1.38 seconds
Started Apr 21 12:46:51 PM PDT 24
Finished Apr 21 12:46:53 PM PDT 24
Peak memory 195728 kb
Host smart-1c7cc333-2a49-42cb-b181-f379e03c9b6b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3326889957 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_no_pullup_pulldown.3326889957
Directory /workspace/26.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/26.gpio_stress_all.3713563052
Short name T466
Test name
Test status
Simulation time 18654786663 ps
CPU time 124.3 seconds
Started Apr 21 12:46:52 PM PDT 24
Finished Apr 21 12:48:57 PM PDT 24
Peak memory 198332 kb
Host smart-95951abc-b0ea-429a-b725-2e885e19a3c9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3713563052 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.
gpio_stress_all.3713563052
Directory /workspace/26.gpio_stress_all/latest

Test location /workspace/coverage/default/26.gpio_stress_all_with_rand_reset.3096552020
Short name T540
Test name
Test status
Simulation time 35643236480 ps
CPU time 630.39 seconds
Started Apr 21 12:46:51 PM PDT 24
Finished Apr 21 12:57:23 PM PDT 24
Peak memory 198384 kb
Host smart-88e404d5-567b-4734-89ec-bcbaf90eddbf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3096552020 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_stress_all_with_rand_reset.3096552020
Directory /workspace/26.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.gpio_alert_test.3503609581
Short name T523
Test name
Test status
Simulation time 52268969 ps
CPU time 0.56 seconds
Started Apr 21 12:46:57 PM PDT 24
Finished Apr 21 12:46:58 PM PDT 24
Peak memory 194172 kb
Host smart-a31bdbf9-bab1-4d7e-bc47-eb5d6e0ff23d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3503609581 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_alert_test.3503609581
Directory /workspace/27.gpio_alert_test/latest

Test location /workspace/coverage/default/27.gpio_dout_din_regs_random_rw.51369406
Short name T424
Test name
Test status
Simulation time 45991766 ps
CPU time 0.9 seconds
Started Apr 21 12:46:55 PM PDT 24
Finished Apr 21 12:46:57 PM PDT 24
Peak memory 196752 kb
Host smart-2a569e69-01e7-4d62-8651-80c4531b09db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=51369406 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_dout_din_regs_random_rw.51369406
Directory /workspace/27.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/27.gpio_filter_stress.1221669054
Short name T665
Test name
Test status
Simulation time 754782008 ps
CPU time 24.56 seconds
Started Apr 21 12:46:56 PM PDT 24
Finished Apr 21 12:47:21 PM PDT 24
Peak memory 196968 kb
Host smart-5dc34cdb-c6ff-4ebe-8375-4bccdd3fefa8
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1221669054 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_filter_stre
ss.1221669054
Directory /workspace/27.gpio_filter_stress/latest

Test location /workspace/coverage/default/27.gpio_full_random.1995127314
Short name T4
Test name
Test status
Simulation time 54524742 ps
CPU time 0.8 seconds
Started Apr 21 12:46:57 PM PDT 24
Finished Apr 21 12:46:59 PM PDT 24
Peak memory 196816 kb
Host smart-19839376-018a-4192-8aaf-50a723240d6a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1995127314 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_full_random.1995127314
Directory /workspace/27.gpio_full_random/latest

Test location /workspace/coverage/default/27.gpio_intr_rand_pgm.582757871
Short name T574
Test name
Test status
Simulation time 42889050 ps
CPU time 0.79 seconds
Started Apr 21 12:46:55 PM PDT 24
Finished Apr 21 12:46:56 PM PDT 24
Peak memory 195872 kb
Host smart-55b5cbc6-8d44-47f6-9a26-50a0b46856c9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=582757871 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_intr_rand_pgm.582757871
Directory /workspace/27.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/27.gpio_intr_with_filter_rand_intr_event.4059087888
Short name T199
Test name
Test status
Simulation time 120969113 ps
CPU time 2.39 seconds
Started Apr 21 12:46:57 PM PDT 24
Finished Apr 21 12:47:00 PM PDT 24
Peak memory 198188 kb
Host smart-061938a2-8a49-4fe5-abf4-4498bc028093
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4059087888 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 27.gpio_intr_with_filter_rand_intr_event.4059087888
Directory /workspace/27.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/27.gpio_rand_intr_trigger.1718915498
Short name T462
Test name
Test status
Simulation time 186956221 ps
CPU time 3.31 seconds
Started Apr 21 12:47:02 PM PDT 24
Finished Apr 21 12:47:07 PM PDT 24
Peak memory 196004 kb
Host smart-8eab93a1-9e72-4978-83b6-78e39c5287a5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1718915498 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_rand_intr_trigger
.1718915498
Directory /workspace/27.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/27.gpio_random_dout_din.324359776
Short name T712
Test name
Test status
Simulation time 100788736 ps
CPU time 1.05 seconds
Started Apr 21 12:47:00 PM PDT 24
Finished Apr 21 12:47:02 PM PDT 24
Peak memory 195932 kb
Host smart-25f07711-f7fc-49ad-bc0b-7db689cb000e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=324359776 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_random_dout_din.324359776
Directory /workspace/27.gpio_random_dout_din/latest

Test location /workspace/coverage/default/27.gpio_random_dout_din_no_pullup_pulldown.3068724772
Short name T698
Test name
Test status
Simulation time 67614372 ps
CPU time 1.27 seconds
Started Apr 21 12:46:53 PM PDT 24
Finished Apr 21 12:46:55 PM PDT 24
Peak memory 196044 kb
Host smart-1456aa2f-e340-48b0-b4f6-23a73597b466
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3068724772 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_random_dout_din_no_pullu
p_pulldown.3068724772
Directory /workspace/27.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/27.gpio_random_long_reg_writes_reg_reads.2260809531
Short name T166
Test name
Test status
Simulation time 123188744 ps
CPU time 5.46 seconds
Started Apr 21 12:46:53 PM PDT 24
Finished Apr 21 12:46:59 PM PDT 24
Peak memory 198204 kb
Host smart-97e4a5fb-0612-47c8-bf5f-d3008d10d13c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2260809531 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_ra
ndom_long_reg_writes_reg_reads.2260809531
Directory /workspace/27.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/27.gpio_smoke.930353207
Short name T565
Test name
Test status
Simulation time 46624401 ps
CPU time 1.02 seconds
Started Apr 21 12:47:01 PM PDT 24
Finished Apr 21 12:47:03 PM PDT 24
Peak memory 196496 kb
Host smart-8fbabdda-f945-4102-afe1-4b6e0e672b02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=930353207 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_smoke.930353207
Directory /workspace/27.gpio_smoke/latest

Test location /workspace/coverage/default/27.gpio_smoke_no_pullup_pulldown.2182627777
Short name T333
Test name
Test status
Simulation time 187176835 ps
CPU time 1.36 seconds
Started Apr 21 12:46:52 PM PDT 24
Finished Apr 21 12:46:54 PM PDT 24
Peak memory 196944 kb
Host smart-6240afa3-d104-4657-afb9-2792088249e4
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2182627777 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_no_pullup_pulldown.2182627777
Directory /workspace/27.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/27.gpio_stress_all.2535234730
Short name T425
Test name
Test status
Simulation time 8732269522 ps
CPU time 119.05 seconds
Started Apr 21 12:47:01 PM PDT 24
Finished Apr 21 12:49:01 PM PDT 24
Peak memory 198352 kb
Host smart-1b14a68b-d26f-451e-90f9-36f685c48532
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2535234730 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.
gpio_stress_all.2535234730
Directory /workspace/27.gpio_stress_all/latest

Test location /workspace/coverage/default/28.gpio_alert_test.1807330324
Short name T200
Test name
Test status
Simulation time 32713717 ps
CPU time 0.56 seconds
Started Apr 21 12:47:02 PM PDT 24
Finished Apr 21 12:47:04 PM PDT 24
Peak memory 194088 kb
Host smart-d5dd74f5-d026-4075-a4cd-1a3af31307fd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1807330324 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_alert_test.1807330324
Directory /workspace/28.gpio_alert_test/latest

Test location /workspace/coverage/default/28.gpio_dout_din_regs_random_rw.3088339464
Short name T312
Test name
Test status
Simulation time 40373081 ps
CPU time 0.68 seconds
Started Apr 21 12:46:55 PM PDT 24
Finished Apr 21 12:46:56 PM PDT 24
Peak memory 194776 kb
Host smart-d4915f1b-7dee-42d7-9f9c-bab9457b8c81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3088339464 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_dout_din_regs_random_rw.3088339464
Directory /workspace/28.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/28.gpio_filter_stress.3066658010
Short name T563
Test name
Test status
Simulation time 714354722 ps
CPU time 11.15 seconds
Started Apr 21 12:47:00 PM PDT 24
Finished Apr 21 12:47:12 PM PDT 24
Peak memory 198212 kb
Host smart-3a3c1627-0319-49d9-bccb-d0fb66e4caac
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3066658010 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_filter_stre
ss.3066658010
Directory /workspace/28.gpio_filter_stress/latest

Test location /workspace/coverage/default/28.gpio_full_random.3466990806
Short name T411
Test name
Test status
Simulation time 47873773 ps
CPU time 0.86 seconds
Started Apr 21 12:47:03 PM PDT 24
Finished Apr 21 12:47:05 PM PDT 24
Peak memory 196272 kb
Host smart-3bf1bc10-8b53-4794-be2b-d5e2bf8c7ec9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3466990806 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_full_random.3466990806
Directory /workspace/28.gpio_full_random/latest

Test location /workspace/coverage/default/28.gpio_intr_rand_pgm.810372066
Short name T250
Test name
Test status
Simulation time 91020487 ps
CPU time 0.84 seconds
Started Apr 21 12:47:01 PM PDT 24
Finished Apr 21 12:47:03 PM PDT 24
Peak memory 196784 kb
Host smart-58c1acb4-3695-46c7-8b79-9aaa882f5ba5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=810372066 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_intr_rand_pgm.810372066
Directory /workspace/28.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/28.gpio_intr_with_filter_rand_intr_event.2098881574
Short name T679
Test name
Test status
Simulation time 150437972 ps
CPU time 1.72 seconds
Started Apr 21 12:46:56 PM PDT 24
Finished Apr 21 12:46:58 PM PDT 24
Peak memory 198272 kb
Host smart-459d145e-bc5f-4825-80eb-f4fb67ff5cc3
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2098881574 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 28.gpio_intr_with_filter_rand_intr_event.2098881574
Directory /workspace/28.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/28.gpio_rand_intr_trigger.2667629524
Short name T547
Test name
Test status
Simulation time 42670482 ps
CPU time 1.01 seconds
Started Apr 21 12:46:57 PM PDT 24
Finished Apr 21 12:46:58 PM PDT 24
Peak memory 195736 kb
Host smart-8f0c07c5-0f4d-46f6-a04b-f27be816f20d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2667629524 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_rand_intr_trigger
.2667629524
Directory /workspace/28.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/28.gpio_random_dout_din.3089963661
Short name T233
Test name
Test status
Simulation time 38532283 ps
CPU time 0.67 seconds
Started Apr 21 12:46:57 PM PDT 24
Finished Apr 21 12:46:59 PM PDT 24
Peak memory 195072 kb
Host smart-bf5dbe85-21ae-409b-bbe9-3f9123d666af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3089963661 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_random_dout_din.3089963661
Directory /workspace/28.gpio_random_dout_din/latest

Test location /workspace/coverage/default/28.gpio_random_dout_din_no_pullup_pulldown.459453473
Short name T444
Test name
Test status
Simulation time 80088116 ps
CPU time 0.8 seconds
Started Apr 21 12:46:56 PM PDT 24
Finished Apr 21 12:46:58 PM PDT 24
Peak memory 195508 kb
Host smart-0aa9e349-dcc3-4a86-b5a6-63368b198f3e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=459453473 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_random_dout_din_no_pullup
_pulldown.459453473
Directory /workspace/28.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/28.gpio_random_long_reg_writes_reg_reads.802808575
Short name T304
Test name
Test status
Simulation time 62459312 ps
CPU time 3 seconds
Started Apr 21 12:47:06 PM PDT 24
Finished Apr 21 12:47:09 PM PDT 24
Peak memory 198128 kb
Host smart-99afa658-42ed-4f4e-82e3-698e53ca5fbd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=802808575 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_ran
dom_long_reg_writes_reg_reads.802808575
Directory /workspace/28.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/28.gpio_smoke.2159763412
Short name T82
Test name
Test status
Simulation time 97404247 ps
CPU time 1.05 seconds
Started Apr 21 12:47:02 PM PDT 24
Finished Apr 21 12:47:04 PM PDT 24
Peak memory 195732 kb
Host smart-2e01c284-5261-4b3a-b72b-780d376b10a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2159763412 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_smoke.2159763412
Directory /workspace/28.gpio_smoke/latest

Test location /workspace/coverage/default/28.gpio_smoke_no_pullup_pulldown.1684933090
Short name T192
Test name
Test status
Simulation time 76370405 ps
CPU time 1.12 seconds
Started Apr 21 12:46:58 PM PDT 24
Finished Apr 21 12:46:59 PM PDT 24
Peak memory 195784 kb
Host smart-41db7d56-7f6c-466e-bc0f-eebe9a603c81
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1684933090 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_no_pullup_pulldown.1684933090
Directory /workspace/28.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/28.gpio_stress_all.1704864849
Short name T534
Test name
Test status
Simulation time 15938323526 ps
CPU time 186.63 seconds
Started Apr 21 12:46:56 PM PDT 24
Finished Apr 21 12:50:03 PM PDT 24
Peak memory 198280 kb
Host smart-090eee4f-34aa-4619-ac00-6291ecc9d760
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1704864849 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.
gpio_stress_all.1704864849
Directory /workspace/28.gpio_stress_all/latest

Test location /workspace/coverage/default/28.gpio_stress_all_with_rand_reset.1449512314
Short name T85
Test name
Test status
Simulation time 383430864160 ps
CPU time 1771.64 seconds
Started Apr 21 12:47:01 PM PDT 24
Finished Apr 21 01:16:34 PM PDT 24
Peak memory 198352 kb
Host smart-8a764cda-3d89-4359-a568-7a45e4cbcd6f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1449512314 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_stress_all_with_rand_reset.1449512314
Directory /workspace/28.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.gpio_alert_test.2062609441
Short name T212
Test name
Test status
Simulation time 71638658 ps
CPU time 0.56 seconds
Started Apr 21 12:46:54 PM PDT 24
Finished Apr 21 12:46:55 PM PDT 24
Peak memory 194128 kb
Host smart-5cd67781-0c39-45ad-95d6-f7f2a09a6b81
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2062609441 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_alert_test.2062609441
Directory /workspace/29.gpio_alert_test/latest

Test location /workspace/coverage/default/29.gpio_dout_din_regs_random_rw.3393303639
Short name T331
Test name
Test status
Simulation time 27466430 ps
CPU time 0.73 seconds
Started Apr 21 12:46:56 PM PDT 24
Finished Apr 21 12:46:58 PM PDT 24
Peak memory 194332 kb
Host smart-a1fc683c-2873-4d56-be24-6433adf81a5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3393303639 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_dout_din_regs_random_rw.3393303639
Directory /workspace/29.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/29.gpio_filter_stress.3786963296
Short name T663
Test name
Test status
Simulation time 3239446552 ps
CPU time 21.54 seconds
Started Apr 21 12:47:02 PM PDT 24
Finished Apr 21 12:47:25 PM PDT 24
Peak memory 197608 kb
Host smart-ac77f582-1347-4e64-ae26-240002f55f84
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3786963296 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_filter_stre
ss.3786963296
Directory /workspace/29.gpio_filter_stress/latest

Test location /workspace/coverage/default/29.gpio_full_random.3820915196
Short name T475
Test name
Test status
Simulation time 63712248 ps
CPU time 0.63 seconds
Started Apr 21 12:47:02 PM PDT 24
Finished Apr 21 12:47:04 PM PDT 24
Peak memory 194544 kb
Host smart-e64abcae-4a5e-495f-b5b9-70b94a5d7d95
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3820915196 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_full_random.3820915196
Directory /workspace/29.gpio_full_random/latest

Test location /workspace/coverage/default/29.gpio_intr_rand_pgm.212173572
Short name T253
Test name
Test status
Simulation time 437817225 ps
CPU time 1.23 seconds
Started Apr 21 12:46:56 PM PDT 24
Finished Apr 21 12:46:58 PM PDT 24
Peak memory 196204 kb
Host smart-616440e1-5d1b-42f0-9623-2a5016394629
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=212173572 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_intr_rand_pgm.212173572
Directory /workspace/29.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/29.gpio_intr_with_filter_rand_intr_event.3545832622
Short name T206
Test name
Test status
Simulation time 98155384 ps
CPU time 1.18 seconds
Started Apr 21 12:46:59 PM PDT 24
Finished Apr 21 12:47:00 PM PDT 24
Peak memory 196676 kb
Host smart-70d99608-36ca-4ddf-988e-a2b64dc01c12
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3545832622 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 29.gpio_intr_with_filter_rand_intr_event.3545832622
Directory /workspace/29.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/29.gpio_rand_intr_trigger.2746319538
Short name T422
Test name
Test status
Simulation time 298631208 ps
CPU time 2.25 seconds
Started Apr 21 12:46:57 PM PDT 24
Finished Apr 21 12:47:00 PM PDT 24
Peak memory 197084 kb
Host smart-fe2bf18d-fa9d-407d-84c5-b42236265a06
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2746319538 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_rand_intr_trigger
.2746319538
Directory /workspace/29.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/29.gpio_random_dout_din.3647141115
Short name T416
Test name
Test status
Simulation time 1031073212 ps
CPU time 1.2 seconds
Started Apr 21 12:46:57 PM PDT 24
Finished Apr 21 12:46:59 PM PDT 24
Peak memory 198220 kb
Host smart-c84b8d58-3a67-4120-a30f-7acc126d4ca2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3647141115 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_random_dout_din.3647141115
Directory /workspace/29.gpio_random_dout_din/latest

Test location /workspace/coverage/default/29.gpio_random_dout_din_no_pullup_pulldown.1022665705
Short name T481
Test name
Test status
Simulation time 48966247 ps
CPU time 1.3 seconds
Started Apr 21 12:47:01 PM PDT 24
Finished Apr 21 12:47:03 PM PDT 24
Peak memory 197384 kb
Host smart-a3bb08e2-b298-4e55-b933-034db0a70f66
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1022665705 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_random_dout_din_no_pullu
p_pulldown.1022665705
Directory /workspace/29.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/29.gpio_random_long_reg_writes_reg_reads.3703360564
Short name T699
Test name
Test status
Simulation time 361677247 ps
CPU time 5.84 seconds
Started Apr 21 12:47:03 PM PDT 24
Finished Apr 21 12:47:10 PM PDT 24
Peak memory 198340 kb
Host smart-520aa708-53a1-4409-ab78-b4686a6481c7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3703360564 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_ra
ndom_long_reg_writes_reg_reads.3703360564
Directory /workspace/29.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/29.gpio_smoke.3039955593
Short name T176
Test name
Test status
Simulation time 651085007 ps
CPU time 1.33 seconds
Started Apr 21 12:46:59 PM PDT 24
Finished Apr 21 12:47:01 PM PDT 24
Peak memory 196764 kb
Host smart-82a87a0d-c7d9-464c-8378-23326ba0ab7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3039955593 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_smoke.3039955593
Directory /workspace/29.gpio_smoke/latest

Test location /workspace/coverage/default/29.gpio_smoke_no_pullup_pulldown.1738500729
Short name T165
Test name
Test status
Simulation time 202605861 ps
CPU time 1.23 seconds
Started Apr 21 12:47:00 PM PDT 24
Finished Apr 21 12:47:02 PM PDT 24
Peak memory 195816 kb
Host smart-01353a94-4c23-4779-b720-213e59ae873d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1738500729 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_no_pullup_pulldown.1738500729
Directory /workspace/29.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/29.gpio_stress_all.824668751
Short name T177
Test name
Test status
Simulation time 1246097477 ps
CPU time 31.3 seconds
Started Apr 21 12:47:03 PM PDT 24
Finished Apr 21 12:47:35 PM PDT 24
Peak memory 198476 kb
Host smart-ac3e5f47-54f5-49af-a149-ebc40a0579be
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=824668751 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.g
pio_stress_all.824668751
Directory /workspace/29.gpio_stress_all/latest

Test location /workspace/coverage/default/3.gpio_alert_test.2288025323
Short name T648
Test name
Test status
Simulation time 14458802 ps
CPU time 0.59 seconds
Started Apr 21 12:45:54 PM PDT 24
Finished Apr 21 12:45:56 PM PDT 24
Peak memory 194080 kb
Host smart-84db8620-306c-46c3-9be1-29f610397502
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2288025323 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_alert_test.2288025323
Directory /workspace/3.gpio_alert_test/latest

Test location /workspace/coverage/default/3.gpio_dout_din_regs_random_rw.675816013
Short name T383
Test name
Test status
Simulation time 167528133 ps
CPU time 0.94 seconds
Started Apr 21 12:46:04 PM PDT 24
Finished Apr 21 12:46:06 PM PDT 24
Peak memory 196120 kb
Host smart-808858ce-c369-4fde-b014-67bfc2012ce0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=675816013 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_dout_din_regs_random_rw.675816013
Directory /workspace/3.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/3.gpio_filter_stress.2179742518
Short name T385
Test name
Test status
Simulation time 240693685 ps
CPU time 12.02 seconds
Started Apr 21 12:45:57 PM PDT 24
Finished Apr 21 12:46:11 PM PDT 24
Peak memory 198224 kb
Host smart-f1d83e6f-6963-4085-b8ce-e581cf05e448
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2179742518 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_filter_stres
s.2179742518
Directory /workspace/3.gpio_filter_stress/latest

Test location /workspace/coverage/default/3.gpio_full_random.1650264137
Short name T117
Test name
Test status
Simulation time 131336099 ps
CPU time 0.97 seconds
Started Apr 21 12:45:56 PM PDT 24
Finished Apr 21 12:45:58 PM PDT 24
Peak memory 197348 kb
Host smart-9dd77ea9-b451-47a0-9413-d03c455f2fc0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1650264137 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_full_random.1650264137
Directory /workspace/3.gpio_full_random/latest

Test location /workspace/coverage/default/3.gpio_intr_rand_pgm.2721149703
Short name T590
Test name
Test status
Simulation time 58495376 ps
CPU time 1.03 seconds
Started Apr 21 12:45:55 PM PDT 24
Finished Apr 21 12:45:57 PM PDT 24
Peak memory 196780 kb
Host smart-f162a08b-a976-43fe-aa70-639b24366327
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2721149703 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_intr_rand_pgm.2721149703
Directory /workspace/3.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/3.gpio_intr_with_filter_rand_intr_event.1783925410
Short name T615
Test name
Test status
Simulation time 76386009 ps
CPU time 2.85 seconds
Started Apr 21 12:46:04 PM PDT 24
Finished Apr 21 12:46:09 PM PDT 24
Peak memory 198252 kb
Host smart-948b46bb-8daa-4165-8056-09a65cdf3534
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1783925410 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 3.gpio_intr_with_filter_rand_intr_event.1783925410
Directory /workspace/3.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/3.gpio_rand_intr_trigger.2836007314
Short name T22
Test name
Test status
Simulation time 81418719 ps
CPU time 1.85 seconds
Started Apr 21 12:45:57 PM PDT 24
Finished Apr 21 12:46:00 PM PDT 24
Peak memory 196652 kb
Host smart-ab66b689-2b4b-435b-8673-b6eba1a7fddb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2836007314 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_rand_intr_trigger.
2836007314
Directory /workspace/3.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/3.gpio_random_dout_din.3708466246
Short name T550
Test name
Test status
Simulation time 105348196 ps
CPU time 0.88 seconds
Started Apr 21 12:46:06 PM PDT 24
Finished Apr 21 12:46:08 PM PDT 24
Peak memory 197572 kb
Host smart-9831d86c-a41e-4147-bae6-03de0993029d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3708466246 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_random_dout_din.3708466246
Directory /workspace/3.gpio_random_dout_din/latest

Test location /workspace/coverage/default/3.gpio_random_dout_din_no_pullup_pulldown.4012403572
Short name T366
Test name
Test status
Simulation time 90838284 ps
CPU time 1.12 seconds
Started Apr 21 12:46:00 PM PDT 24
Finished Apr 21 12:46:02 PM PDT 24
Peak memory 196296 kb
Host smart-9a996d2f-426f-4678-b6d5-9330c3918155
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4012403572 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_random_dout_din_no_pullup
_pulldown.4012403572
Directory /workspace/3.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/3.gpio_random_long_reg_writes_reg_reads.3104376785
Short name T610
Test name
Test status
Simulation time 122754474 ps
CPU time 5.39 seconds
Started Apr 21 12:45:51 PM PDT 24
Finished Apr 21 12:45:57 PM PDT 24
Peak memory 198192 kb
Host smart-525e6b8c-d8fb-43e9-b53b-0ed75b5d9baa
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3104376785 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_ran
dom_long_reg_writes_reg_reads.3104376785
Directory /workspace/3.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/3.gpio_sec_cm.3513916454
Short name T60
Test name
Test status
Simulation time 192100839 ps
CPU time 0.97 seconds
Started Apr 21 12:46:03 PM PDT 24
Finished Apr 21 12:46:05 PM PDT 24
Peak memory 214952 kb
Host smart-7a52aabe-65cd-4674-917e-33dc591e285c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3513916454 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_sec_cm.3513916454
Directory /workspace/3.gpio_sec_cm/latest

Test location /workspace/coverage/default/3.gpio_smoke.318824225
Short name T113
Test name
Test status
Simulation time 236300365 ps
CPU time 1.15 seconds
Started Apr 21 12:45:57 PM PDT 24
Finished Apr 21 12:45:59 PM PDT 24
Peak memory 195860 kb
Host smart-8466ff54-821e-426a-9923-bf3ef1935fe3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=318824225 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_smoke.318824225
Directory /workspace/3.gpio_smoke/latest

Test location /workspace/coverage/default/3.gpio_smoke_no_pullup_pulldown.3623936831
Short name T668
Test name
Test status
Simulation time 39585760 ps
CPU time 1.09 seconds
Started Apr 21 12:45:57 PM PDT 24
Finished Apr 21 12:46:00 PM PDT 24
Peak memory 195812 kb
Host smart-99119cd8-44e6-4085-ab2e-c4962856a77b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3623936831 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_no_pullup_pulldown.3623936831
Directory /workspace/3.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/3.gpio_stress_all.4199267945
Short name T320
Test name
Test status
Simulation time 158859219206 ps
CPU time 214.68 seconds
Started Apr 21 12:46:09 PM PDT 24
Finished Apr 21 12:49:45 PM PDT 24
Peak memory 198216 kb
Host smart-83d226c9-7102-4c45-8833-3489cbd40031
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4199267945 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.g
pio_stress_all.4199267945
Directory /workspace/3.gpio_stress_all/latest

Test location /workspace/coverage/default/30.gpio_alert_test.1912325989
Short name T483
Test name
Test status
Simulation time 15623267 ps
CPU time 0.62 seconds
Started Apr 21 12:47:09 PM PDT 24
Finished Apr 21 12:47:10 PM PDT 24
Peak memory 195128 kb
Host smart-e799c005-8a8c-4069-8b00-eec9b1d132f5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1912325989 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_alert_test.1912325989
Directory /workspace/30.gpio_alert_test/latest

Test location /workspace/coverage/default/30.gpio_dout_din_regs_random_rw.424591127
Short name T230
Test name
Test status
Simulation time 85636772 ps
CPU time 0.71 seconds
Started Apr 21 12:46:57 PM PDT 24
Finished Apr 21 12:46:59 PM PDT 24
Peak memory 195356 kb
Host smart-c7c23a07-b46f-4cc1-9f1b-20257df8cff8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=424591127 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_dout_din_regs_random_rw.424591127
Directory /workspace/30.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/30.gpio_filter_stress.2809446462
Short name T151
Test name
Test status
Simulation time 475101562 ps
CPU time 6.64 seconds
Started Apr 21 12:47:14 PM PDT 24
Finished Apr 21 12:47:21 PM PDT 24
Peak memory 196860 kb
Host smart-c576906e-dbc6-479a-a1f7-b83f4299082e
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2809446462 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_filter_stre
ss.2809446462
Directory /workspace/30.gpio_filter_stress/latest

Test location /workspace/coverage/default/30.gpio_full_random.2643851926
Short name T500
Test name
Test status
Simulation time 99442538 ps
CPU time 1.02 seconds
Started Apr 21 12:47:01 PM PDT 24
Finished Apr 21 12:47:02 PM PDT 24
Peak memory 196580 kb
Host smart-61fda877-63ea-4890-b5c1-9e9b206c7c53
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2643851926 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_full_random.2643851926
Directory /workspace/30.gpio_full_random/latest

Test location /workspace/coverage/default/30.gpio_intr_rand_pgm.257182786
Short name T265
Test name
Test status
Simulation time 34460490 ps
CPU time 0.67 seconds
Started Apr 21 12:47:02 PM PDT 24
Finished Apr 21 12:47:04 PM PDT 24
Peak memory 193704 kb
Host smart-e24b9847-1475-4a5e-89ab-9efd02f7bd69
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=257182786 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_intr_rand_pgm.257182786
Directory /workspace/30.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/30.gpio_intr_with_filter_rand_intr_event.1359170727
Short name T387
Test name
Test status
Simulation time 52146156 ps
CPU time 2.03 seconds
Started Apr 21 12:47:00 PM PDT 24
Finished Apr 21 12:47:03 PM PDT 24
Peak memory 198260 kb
Host smart-2b53b4b8-6583-4f70-9989-b9df1ac421fc
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1359170727 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 30.gpio_intr_with_filter_rand_intr_event.1359170727
Directory /workspace/30.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/30.gpio_rand_intr_trigger.3026699025
Short name T644
Test name
Test status
Simulation time 1105297321 ps
CPU time 2.1 seconds
Started Apr 21 12:47:03 PM PDT 24
Finished Apr 21 12:47:06 PM PDT 24
Peak memory 197336 kb
Host smart-385d0086-cef9-4c75-ad7d-57c9184a34f8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3026699025 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_rand_intr_trigger
.3026699025
Directory /workspace/30.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/30.gpio_random_dout_din.3083406346
Short name T676
Test name
Test status
Simulation time 94627546 ps
CPU time 0.75 seconds
Started Apr 21 12:46:56 PM PDT 24
Finished Apr 21 12:46:58 PM PDT 24
Peak memory 195660 kb
Host smart-2b87079f-faad-4167-aa24-effe3c690f9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3083406346 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_random_dout_din.3083406346
Directory /workspace/30.gpio_random_dout_din/latest

Test location /workspace/coverage/default/30.gpio_random_dout_din_no_pullup_pulldown.870253266
Short name T280
Test name
Test status
Simulation time 55958115 ps
CPU time 0.96 seconds
Started Apr 21 12:46:56 PM PDT 24
Finished Apr 21 12:46:57 PM PDT 24
Peak memory 196716 kb
Host smart-e0b2ad9a-816e-4215-8696-6ba2b7899fa7
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=870253266 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_random_dout_din_no_pullup
_pulldown.870253266
Directory /workspace/30.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/30.gpio_random_long_reg_writes_reg_reads.705193933
Short name T6
Test name
Test status
Simulation time 1017469907 ps
CPU time 6.04 seconds
Started Apr 21 12:47:06 PM PDT 24
Finished Apr 21 12:47:13 PM PDT 24
Peak memory 198196 kb
Host smart-c41ac03e-3af9-44c4-bd59-60eb5ccf51ca
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=705193933 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_ran
dom_long_reg_writes_reg_reads.705193933
Directory /workspace/30.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/30.gpio_smoke.2389811360
Short name T373
Test name
Test status
Simulation time 75372651 ps
CPU time 1.19 seconds
Started Apr 21 12:47:00 PM PDT 24
Finished Apr 21 12:47:02 PM PDT 24
Peak memory 196124 kb
Host smart-49aaa67d-cb65-4f62-8216-5db84346ede6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2389811360 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_smoke.2389811360
Directory /workspace/30.gpio_smoke/latest

Test location /workspace/coverage/default/30.gpio_smoke_no_pullup_pulldown.2743247024
Short name T604
Test name
Test status
Simulation time 285173009 ps
CPU time 1.08 seconds
Started Apr 21 12:46:56 PM PDT 24
Finished Apr 21 12:46:58 PM PDT 24
Peak memory 195828 kb
Host smart-69e82422-fe72-40d5-aee1-64d70f7b4a2f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2743247024 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_no_pullup_pulldown.2743247024
Directory /workspace/30.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/30.gpio_stress_all.3478622113
Short name T548
Test name
Test status
Simulation time 13739405931 ps
CPU time 194.75 seconds
Started Apr 21 12:47:02 PM PDT 24
Finished Apr 21 12:50:18 PM PDT 24
Peak memory 198296 kb
Host smart-f3a12ce9-72cf-4fe6-b896-2dd84de643f0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3478622113 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.
gpio_stress_all.3478622113
Directory /workspace/30.gpio_stress_all/latest

Test location /workspace/coverage/default/31.gpio_alert_test.2356816029
Short name T485
Test name
Test status
Simulation time 14898396 ps
CPU time 0.58 seconds
Started Apr 21 12:47:04 PM PDT 24
Finished Apr 21 12:47:05 PM PDT 24
Peak memory 194724 kb
Host smart-f226fc79-58f9-40c9-ba4d-b6b1358ebe65
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2356816029 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_alert_test.2356816029
Directory /workspace/31.gpio_alert_test/latest

Test location /workspace/coverage/default/31.gpio_dout_din_regs_random_rw.2398148343
Short name T237
Test name
Test status
Simulation time 46903791 ps
CPU time 0.89 seconds
Started Apr 21 12:47:00 PM PDT 24
Finished Apr 21 12:47:01 PM PDT 24
Peak memory 196488 kb
Host smart-76f28520-3073-4012-97f0-f97b9e7f1061
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2398148343 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_dout_din_regs_random_rw.2398148343
Directory /workspace/31.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/31.gpio_filter_stress.540166611
Short name T360
Test name
Test status
Simulation time 142217091 ps
CPU time 4.02 seconds
Started Apr 21 12:47:04 PM PDT 24
Finished Apr 21 12:47:08 PM PDT 24
Peak memory 195688 kb
Host smart-8e0cb84d-a8fe-404f-a937-82bb8d169b8c
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=540166611 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_filter_stres
s.540166611
Directory /workspace/31.gpio_filter_stress/latest

Test location /workspace/coverage/default/31.gpio_full_random.2990440551
Short name T51
Test name
Test status
Simulation time 258580891 ps
CPU time 1 seconds
Started Apr 21 12:46:59 PM PDT 24
Finished Apr 21 12:47:00 PM PDT 24
Peak memory 197944 kb
Host smart-f928be76-5ce7-4138-964e-031110ffa276
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2990440551 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_full_random.2990440551
Directory /workspace/31.gpio_full_random/latest

Test location /workspace/coverage/default/31.gpio_intr_rand_pgm.3446863511
Short name T671
Test name
Test status
Simulation time 100200365 ps
CPU time 0.8 seconds
Started Apr 21 12:47:03 PM PDT 24
Finished Apr 21 12:47:05 PM PDT 24
Peak memory 195592 kb
Host smart-30c484c2-0b7d-492d-b704-3e8bb07a1d1a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3446863511 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_intr_rand_pgm.3446863511
Directory /workspace/31.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/31.gpio_intr_with_filter_rand_intr_event.3693457520
Short name T401
Test name
Test status
Simulation time 53602432 ps
CPU time 1.34 seconds
Started Apr 21 12:46:59 PM PDT 24
Finished Apr 21 12:47:01 PM PDT 24
Peak memory 197188 kb
Host smart-6d1b7a48-217d-49b1-996b-8c35da996ee5
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3693457520 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 31.gpio_intr_with_filter_rand_intr_event.3693457520
Directory /workspace/31.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/31.gpio_rand_intr_trigger.2726224993
Short name T168
Test name
Test status
Simulation time 236686447 ps
CPU time 1.12 seconds
Started Apr 21 12:47:07 PM PDT 24
Finished Apr 21 12:47:09 PM PDT 24
Peak memory 195704 kb
Host smart-168f945d-43b0-45b4-b1fa-e259a1ca8dac
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2726224993 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_rand_intr_trigger
.2726224993
Directory /workspace/31.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/31.gpio_random_dout_din.1959264239
Short name T174
Test name
Test status
Simulation time 33064236 ps
CPU time 1.45 seconds
Started Apr 21 12:46:59 PM PDT 24
Finished Apr 21 12:47:02 PM PDT 24
Peak memory 198336 kb
Host smart-d1ad1f09-714a-4832-b533-d27a8a232f17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1959264239 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_random_dout_din.1959264239
Directory /workspace/31.gpio_random_dout_din/latest

Test location /workspace/coverage/default/31.gpio_random_dout_din_no_pullup_pulldown.2045250785
Short name T232
Test name
Test status
Simulation time 22387656 ps
CPU time 0.85 seconds
Started Apr 21 12:47:08 PM PDT 24
Finished Apr 21 12:47:09 PM PDT 24
Peak memory 196872 kb
Host smart-9786f5a9-837e-451a-b5ee-5b8294b997df
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2045250785 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_random_dout_din_no_pullu
p_pulldown.2045250785
Directory /workspace/31.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/31.gpio_random_long_reg_writes_reg_reads.3736252651
Short name T594
Test name
Test status
Simulation time 476157493 ps
CPU time 3.87 seconds
Started Apr 21 12:47:00 PM PDT 24
Finished Apr 21 12:47:04 PM PDT 24
Peak memory 198164 kb
Host smart-5a3c79fc-798f-4242-84bb-f29b4de8ff4e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3736252651 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_ra
ndom_long_reg_writes_reg_reads.3736252651
Directory /workspace/31.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/31.gpio_smoke.112693613
Short name T187
Test name
Test status
Simulation time 128433756 ps
CPU time 1.03 seconds
Started Apr 21 12:47:01 PM PDT 24
Finished Apr 21 12:47:03 PM PDT 24
Peak memory 195904 kb
Host smart-4694695b-58ed-470e-b3ec-26d9f1410cab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=112693613 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_smoke.112693613
Directory /workspace/31.gpio_smoke/latest

Test location /workspace/coverage/default/31.gpio_smoke_no_pullup_pulldown.789271170
Short name T43
Test name
Test status
Simulation time 249633127 ps
CPU time 1.26 seconds
Started Apr 21 12:47:02 PM PDT 24
Finished Apr 21 12:47:05 PM PDT 24
Peak memory 196068 kb
Host smart-0075df41-d82b-4bf7-adc6-73497de1563b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=789271170 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_no_pullup_pulldown.789271170
Directory /workspace/31.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/31.gpio_stress_all.723447946
Short name T8
Test name
Test status
Simulation time 67531005345 ps
CPU time 188.33 seconds
Started Apr 21 12:46:59 PM PDT 24
Finished Apr 21 12:50:08 PM PDT 24
Peak memory 198296 kb
Host smart-a4f11c4e-7f30-4836-8107-16a8f255cd37
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=723447946 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.g
pio_stress_all.723447946
Directory /workspace/31.gpio_stress_all/latest

Test location /workspace/coverage/default/32.gpio_alert_test.2164698022
Short name T531
Test name
Test status
Simulation time 36771191 ps
CPU time 0.59 seconds
Started Apr 21 12:47:09 PM PDT 24
Finished Apr 21 12:47:10 PM PDT 24
Peak memory 194928 kb
Host smart-d1c833e5-7fa2-43ec-bbc8-1f98c1e2c2ec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2164698022 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_alert_test.2164698022
Directory /workspace/32.gpio_alert_test/latest

Test location /workspace/coverage/default/32.gpio_dout_din_regs_random_rw.4057403969
Short name T147
Test name
Test status
Simulation time 30959529 ps
CPU time 0.84 seconds
Started Apr 21 12:47:02 PM PDT 24
Finished Apr 21 12:47:05 PM PDT 24
Peak memory 196784 kb
Host smart-3f6978fa-2d8d-419c-a922-62eeba19e942
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4057403969 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_dout_din_regs_random_rw.4057403969
Directory /workspace/32.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/32.gpio_filter_stress.1467373219
Short name T314
Test name
Test status
Simulation time 2435743138 ps
CPU time 22.53 seconds
Started Apr 21 12:47:04 PM PDT 24
Finished Apr 21 12:47:27 PM PDT 24
Peak memory 196732 kb
Host smart-c9ffd1e0-9de3-43bf-a771-e005b2e40bdc
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1467373219 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_filter_stre
ss.1467373219
Directory /workspace/32.gpio_filter_stress/latest

Test location /workspace/coverage/default/32.gpio_full_random.1533462824
Short name T271
Test name
Test status
Simulation time 154645450 ps
CPU time 0.77 seconds
Started Apr 21 12:47:03 PM PDT 24
Finished Apr 21 12:47:05 PM PDT 24
Peak memory 195928 kb
Host smart-dbea1f72-f0f7-4c17-b421-7d1d21c6bcab
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1533462824 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_full_random.1533462824
Directory /workspace/32.gpio_full_random/latest

Test location /workspace/coverage/default/32.gpio_intr_rand_pgm.2562823249
Short name T473
Test name
Test status
Simulation time 88630252 ps
CPU time 1.23 seconds
Started Apr 21 12:47:09 PM PDT 24
Finished Apr 21 12:47:10 PM PDT 24
Peak memory 196752 kb
Host smart-4f1ac6bf-c625-4ecf-9177-4b820e073cf1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2562823249 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_intr_rand_pgm.2562823249
Directory /workspace/32.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/32.gpio_intr_with_filter_rand_intr_event.2272410030
Short name T465
Test name
Test status
Simulation time 167607371 ps
CPU time 3.12 seconds
Started Apr 21 12:47:14 PM PDT 24
Finished Apr 21 12:47:18 PM PDT 24
Peak memory 198352 kb
Host smart-c5c15a78-3616-49ab-92d6-65ca3986d63d
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2272410030 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 32.gpio_intr_with_filter_rand_intr_event.2272410030
Directory /workspace/32.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/32.gpio_rand_intr_trigger.1797761277
Short name T438
Test name
Test status
Simulation time 115155505 ps
CPU time 2.54 seconds
Started Apr 21 12:47:03 PM PDT 24
Finished Apr 21 12:47:07 PM PDT 24
Peak memory 198144 kb
Host smart-a2832ac2-1abf-4f28-a375-5e8bc2b37556
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1797761277 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_rand_intr_trigger
.1797761277
Directory /workspace/32.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/32.gpio_random_dout_din.3071856788
Short name T262
Test name
Test status
Simulation time 129298814 ps
CPU time 1.11 seconds
Started Apr 21 12:47:15 PM PDT 24
Finished Apr 21 12:47:16 PM PDT 24
Peak memory 196280 kb
Host smart-afa30735-98cd-4499-b28b-a3b7a23d0d16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3071856788 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_random_dout_din.3071856788
Directory /workspace/32.gpio_random_dout_din/latest

Test location /workspace/coverage/default/32.gpio_random_dout_din_no_pullup_pulldown.212547608
Short name T371
Test name
Test status
Simulation time 156023133 ps
CPU time 0.98 seconds
Started Apr 21 12:47:00 PM PDT 24
Finished Apr 21 12:47:02 PM PDT 24
Peak memory 196028 kb
Host smart-d84e0e09-1f86-43c6-927e-912390424a2b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=212547608 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_random_dout_din_no_pullup
_pulldown.212547608
Directory /workspace/32.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/32.gpio_random_long_reg_writes_reg_reads.1394010449
Short name T39
Test name
Test status
Simulation time 105404240 ps
CPU time 4.79 seconds
Started Apr 21 12:47:03 PM PDT 24
Finished Apr 21 12:47:09 PM PDT 24
Peak memory 198172 kb
Host smart-1ba333ec-1855-4cc1-a8a5-cd55a3ba7d4c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1394010449 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_ra
ndom_long_reg_writes_reg_reads.1394010449
Directory /workspace/32.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/32.gpio_smoke.937106736
Short name T484
Test name
Test status
Simulation time 85046539 ps
CPU time 0.99 seconds
Started Apr 21 12:46:59 PM PDT 24
Finished Apr 21 12:47:01 PM PDT 24
Peak memory 195960 kb
Host smart-891174fe-2939-4fc6-ba62-dd05a7aaafdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=937106736 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_smoke.937106736
Directory /workspace/32.gpio_smoke/latest

Test location /workspace/coverage/default/32.gpio_smoke_no_pullup_pulldown.267443420
Short name T185
Test name
Test status
Simulation time 135573855 ps
CPU time 1.33 seconds
Started Apr 21 12:46:58 PM PDT 24
Finished Apr 21 12:46:59 PM PDT 24
Peak memory 196984 kb
Host smart-62b50ca7-4360-4a71-9f84-fc8d89d24033
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=267443420 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_no_pullup_pulldown.267443420
Directory /workspace/32.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/32.gpio_stress_all.1402851474
Short name T446
Test name
Test status
Simulation time 38132569845 ps
CPU time 92.94 seconds
Started Apr 21 12:47:04 PM PDT 24
Finished Apr 21 12:48:38 PM PDT 24
Peak memory 198324 kb
Host smart-926e9a5d-0709-4d9c-b04b-75401c9017bb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1402851474 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.
gpio_stress_all.1402851474
Directory /workspace/32.gpio_stress_all/latest

Test location /workspace/coverage/default/33.gpio_alert_test.4093251216
Short name T28
Test name
Test status
Simulation time 41595620 ps
CPU time 0.6 seconds
Started Apr 21 12:47:04 PM PDT 24
Finished Apr 21 12:47:05 PM PDT 24
Peak memory 194864 kb
Host smart-3995c3e0-8eb7-4848-a96d-9358c556f373
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4093251216 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_alert_test.4093251216
Directory /workspace/33.gpio_alert_test/latest

Test location /workspace/coverage/default/33.gpio_dout_din_regs_random_rw.4226502838
Short name T450
Test name
Test status
Simulation time 24439584 ps
CPU time 0.64 seconds
Started Apr 21 12:47:22 PM PDT 24
Finished Apr 21 12:47:24 PM PDT 24
Peak memory 194100 kb
Host smart-df11936e-a701-47e6-a6e1-70892d12cabf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4226502838 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_dout_din_regs_random_rw.4226502838
Directory /workspace/33.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/33.gpio_filter_stress.4090961952
Short name T704
Test name
Test status
Simulation time 1462245479 ps
CPU time 25.91 seconds
Started Apr 21 12:47:15 PM PDT 24
Finished Apr 21 12:47:41 PM PDT 24
Peak memory 198064 kb
Host smart-7f5b82be-47fd-4ab4-8fc5-7ac34ef062e9
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4090961952 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_filter_stre
ss.4090961952
Directory /workspace/33.gpio_filter_stress/latest

Test location /workspace/coverage/default/33.gpio_full_random.1432623726
Short name T433
Test name
Test status
Simulation time 215073386 ps
CPU time 0.91 seconds
Started Apr 21 12:47:12 PM PDT 24
Finished Apr 21 12:47:13 PM PDT 24
Peak memory 196300 kb
Host smart-d73cee25-0806-41ca-885e-842d917701f5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1432623726 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_full_random.1432623726
Directory /workspace/33.gpio_full_random/latest

Test location /workspace/coverage/default/33.gpio_intr_rand_pgm.2374333855
Short name T569
Test name
Test status
Simulation time 510423424 ps
CPU time 0.91 seconds
Started Apr 21 12:47:14 PM PDT 24
Finished Apr 21 12:47:15 PM PDT 24
Peak memory 196060 kb
Host smart-e3699f40-1a4c-4719-8bed-aaf264684286
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2374333855 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_intr_rand_pgm.2374333855
Directory /workspace/33.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/33.gpio_intr_with_filter_rand_intr_event.2056453034
Short name T318
Test name
Test status
Simulation time 104604736 ps
CPU time 2.2 seconds
Started Apr 21 12:47:32 PM PDT 24
Finished Apr 21 12:47:34 PM PDT 24
Peak memory 198120 kb
Host smart-75147fa6-10f6-4d03-8d3d-2bc27a131c4e
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2056453034 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 33.gpio_intr_with_filter_rand_intr_event.2056453034
Directory /workspace/33.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/33.gpio_rand_intr_trigger.2044326007
Short name T480
Test name
Test status
Simulation time 109489334 ps
CPU time 3.12 seconds
Started Apr 21 12:47:09 PM PDT 24
Finished Apr 21 12:47:12 PM PDT 24
Peak memory 197372 kb
Host smart-23ed47a1-29df-4a58-8aad-5e29f0979c6c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2044326007 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_rand_intr_trigger
.2044326007
Directory /workspace/33.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/33.gpio_random_dout_din.2409841236
Short name T709
Test name
Test status
Simulation time 204004313 ps
CPU time 1.23 seconds
Started Apr 21 12:47:02 PM PDT 24
Finished Apr 21 12:47:04 PM PDT 24
Peak memory 197248 kb
Host smart-94efab79-e0b4-4003-95d5-73434ed96d0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2409841236 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_random_dout_din.2409841236
Directory /workspace/33.gpio_random_dout_din/latest

Test location /workspace/coverage/default/33.gpio_random_dout_din_no_pullup_pulldown.519386885
Short name T243
Test name
Test status
Simulation time 59747078 ps
CPU time 0.93 seconds
Started Apr 21 12:47:04 PM PDT 24
Finished Apr 21 12:47:06 PM PDT 24
Peak memory 196684 kb
Host smart-11da6c92-ec49-46d3-8c92-2635ef5d2c53
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=519386885 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_random_dout_din_no_pullup
_pulldown.519386885
Directory /workspace/33.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/33.gpio_random_long_reg_writes_reg_reads.2858631305
Short name T5
Test name
Test status
Simulation time 449480600 ps
CPU time 6.15 seconds
Started Apr 21 12:47:21 PM PDT 24
Finished Apr 21 12:47:28 PM PDT 24
Peak memory 198092 kb
Host smart-cde1412e-90ce-42d2-8eb0-4461263dc555
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2858631305 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_ra
ndom_long_reg_writes_reg_reads.2858631305
Directory /workspace/33.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/33.gpio_smoke.2205268318
Short name T169
Test name
Test status
Simulation time 155078802 ps
CPU time 1.24 seconds
Started Apr 21 12:47:16 PM PDT 24
Finished Apr 21 12:47:18 PM PDT 24
Peak memory 195768 kb
Host smart-0ef39131-d70e-4638-8c3e-df32c24908db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2205268318 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_smoke.2205268318
Directory /workspace/33.gpio_smoke/latest

Test location /workspace/coverage/default/33.gpio_smoke_no_pullup_pulldown.3732697112
Short name T715
Test name
Test status
Simulation time 180219126 ps
CPU time 1.29 seconds
Started Apr 21 12:47:12 PM PDT 24
Finished Apr 21 12:47:13 PM PDT 24
Peak memory 197028 kb
Host smart-c4d09af3-c21d-4ef4-a3ff-1f5da9898603
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3732697112 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_no_pullup_pulldown.3732697112
Directory /workspace/33.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/33.gpio_stress_all.1792284082
Short name T377
Test name
Test status
Simulation time 5556616114 ps
CPU time 163.68 seconds
Started Apr 21 12:47:10 PM PDT 24
Finished Apr 21 12:49:54 PM PDT 24
Peak memory 198328 kb
Host smart-cdca9ced-363b-4e64-b96e-5866eee4372c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1792284082 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.
gpio_stress_all.1792284082
Directory /workspace/33.gpio_stress_all/latest

Test location /workspace/coverage/default/33.gpio_stress_all_with_rand_reset.4833579
Short name T89
Test name
Test status
Simulation time 248990430688 ps
CPU time 1724.05 seconds
Started Apr 21 12:47:10 PM PDT 24
Finished Apr 21 01:15:55 PM PDT 24
Peak memory 198400 kb
Host smart-832fdb4e-9ffc-41e9-b2ac-eb8337f1b4f8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=4833579 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_stress_all_with_rand_reset.4833579
Directory /workspace/33.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.gpio_alert_test.3257496609
Short name T202
Test name
Test status
Simulation time 73819418 ps
CPU time 0.59 seconds
Started Apr 21 12:47:21 PM PDT 24
Finished Apr 21 12:47:22 PM PDT 24
Peak memory 194772 kb
Host smart-77f629ef-1ade-4a43-84e5-183c5b22fe12
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3257496609 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_alert_test.3257496609
Directory /workspace/34.gpio_alert_test/latest

Test location /workspace/coverage/default/34.gpio_dout_din_regs_random_rw.431428395
Short name T713
Test name
Test status
Simulation time 35994602 ps
CPU time 0.8 seconds
Started Apr 21 12:47:08 PM PDT 24
Finished Apr 21 12:47:09 PM PDT 24
Peak memory 195428 kb
Host smart-eed17e7c-7da0-4b13-a792-cdf862983c84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=431428395 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_dout_din_regs_random_rw.431428395
Directory /workspace/34.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/34.gpio_filter_stress.1434985626
Short name T708
Test name
Test status
Simulation time 2171572387 ps
CPU time 24.47 seconds
Started Apr 21 12:47:28 PM PDT 24
Finished Apr 21 12:47:53 PM PDT 24
Peak memory 197448 kb
Host smart-c22778c0-84e6-43f8-a64f-253a0bbcef23
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1434985626 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_filter_stre
ss.1434985626
Directory /workspace/34.gpio_filter_stress/latest

Test location /workspace/coverage/default/34.gpio_full_random.3416603078
Short name T313
Test name
Test status
Simulation time 141523718 ps
CPU time 0.69 seconds
Started Apr 21 12:47:21 PM PDT 24
Finished Apr 21 12:47:22 PM PDT 24
Peak memory 195660 kb
Host smart-b9d8d3bf-cf07-47ee-a2b0-c50dcb39a647
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3416603078 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_full_random.3416603078
Directory /workspace/34.gpio_full_random/latest

Test location /workspace/coverage/default/34.gpio_intr_rand_pgm.3577692641
Short name T522
Test name
Test status
Simulation time 194066706 ps
CPU time 1.32 seconds
Started Apr 21 12:47:18 PM PDT 24
Finished Apr 21 12:47:20 PM PDT 24
Peak memory 197080 kb
Host smart-1fa9650e-9864-4d0f-8063-256f349b593c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3577692641 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_intr_rand_pgm.3577692641
Directory /workspace/34.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/34.gpio_intr_with_filter_rand_intr_event.4276409784
Short name T616
Test name
Test status
Simulation time 315886773 ps
CPU time 3.64 seconds
Started Apr 21 12:47:13 PM PDT 24
Finished Apr 21 12:47:17 PM PDT 24
Peak memory 198276 kb
Host smart-65e5251f-9f5d-4bf3-bb98-a5bb71a8e7c5
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4276409784 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 34.gpio_intr_with_filter_rand_intr_event.4276409784
Directory /workspace/34.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/34.gpio_rand_intr_trigger.3410717984
Short name T490
Test name
Test status
Simulation time 133018841 ps
CPU time 1.98 seconds
Started Apr 21 12:47:18 PM PDT 24
Finished Apr 21 12:47:21 PM PDT 24
Peak memory 198232 kb
Host smart-7412076c-3e58-4167-bb69-09033add9a90
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3410717984 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_rand_intr_trigger
.3410717984
Directory /workspace/34.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/34.gpio_random_dout_din.1118234828
Short name T294
Test name
Test status
Simulation time 33345782 ps
CPU time 1.18 seconds
Started Apr 21 12:47:12 PM PDT 24
Finished Apr 21 12:47:14 PM PDT 24
Peak memory 197152 kb
Host smart-e756dda2-63d8-46d4-8a82-1f0af4f55a32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1118234828 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_random_dout_din.1118234828
Directory /workspace/34.gpio_random_dout_din/latest

Test location /workspace/coverage/default/34.gpio_random_dout_din_no_pullup_pulldown.1883486149
Short name T562
Test name
Test status
Simulation time 78915720 ps
CPU time 0.7 seconds
Started Apr 21 12:47:13 PM PDT 24
Finished Apr 21 12:47:14 PM PDT 24
Peak memory 194612 kb
Host smart-6ca0980a-52c5-49e6-a296-9a64763e1c56
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1883486149 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_random_dout_din_no_pullu
p_pulldown.1883486149
Directory /workspace/34.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/34.gpio_random_long_reg_writes_reg_reads.1630852239
Short name T10
Test name
Test status
Simulation time 183530293 ps
CPU time 2.54 seconds
Started Apr 21 12:47:21 PM PDT 24
Finished Apr 21 12:47:24 PM PDT 24
Peak memory 198076 kb
Host smart-3c7a079a-ca93-4b28-a690-341f7b978199
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1630852239 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_ra
ndom_long_reg_writes_reg_reads.1630852239
Directory /workspace/34.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/34.gpio_smoke.281946962
Short name T388
Test name
Test status
Simulation time 115231128 ps
CPU time 1 seconds
Started Apr 21 12:47:14 PM PDT 24
Finished Apr 21 12:47:15 PM PDT 24
Peak memory 195760 kb
Host smart-995bece4-633f-4584-aea3-9d89ee6430f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=281946962 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_smoke.281946962
Directory /workspace/34.gpio_smoke/latest

Test location /workspace/coverage/default/34.gpio_smoke_no_pullup_pulldown.2756051815
Short name T15
Test name
Test status
Simulation time 37084331 ps
CPU time 1.04 seconds
Started Apr 21 12:47:22 PM PDT 24
Finished Apr 21 12:47:24 PM PDT 24
Peak memory 196000 kb
Host smart-08c53f19-eee3-49e0-86a2-6d2475958f0b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2756051815 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_no_pullup_pulldown.2756051815
Directory /workspace/34.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/34.gpio_stress_all.2382779639
Short name T559
Test name
Test status
Simulation time 56694104873 ps
CPU time 208.33 seconds
Started Apr 21 12:47:22 PM PDT 24
Finished Apr 21 12:50:51 PM PDT 24
Peak memory 198320 kb
Host smart-0f4514be-a4b2-4018-afdd-8f9509dbb23f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2382779639 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.
gpio_stress_all.2382779639
Directory /workspace/34.gpio_stress_all/latest

Test location /workspace/coverage/default/35.gpio_alert_test.2104750420
Short name T356
Test name
Test status
Simulation time 17567589 ps
CPU time 0.62 seconds
Started Apr 21 12:47:21 PM PDT 24
Finished Apr 21 12:47:22 PM PDT 24
Peak memory 194060 kb
Host smart-f39f4316-e5ac-44d0-a708-601a5641fdbc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2104750420 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_alert_test.2104750420
Directory /workspace/35.gpio_alert_test/latest

Test location /workspace/coverage/default/35.gpio_dout_din_regs_random_rw.3410894821
Short name T146
Test name
Test status
Simulation time 117611019 ps
CPU time 0.64 seconds
Started Apr 21 12:47:21 PM PDT 24
Finished Apr 21 12:47:23 PM PDT 24
Peak memory 194916 kb
Host smart-e3ca12de-2013-472f-b0e6-6aa729ab96bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3410894821 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_dout_din_regs_random_rw.3410894821
Directory /workspace/35.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/35.gpio_filter_stress.672196854
Short name T369
Test name
Test status
Simulation time 2496104268 ps
CPU time 22.75 seconds
Started Apr 21 12:47:27 PM PDT 24
Finished Apr 21 12:47:50 PM PDT 24
Peak memory 197248 kb
Host smart-8f14a8c8-40d1-4adb-881f-1d629e5441a2
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=672196854 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_filter_stres
s.672196854
Directory /workspace/35.gpio_filter_stress/latest

Test location /workspace/coverage/default/35.gpio_full_random.3258916342
Short name T498
Test name
Test status
Simulation time 386994024 ps
CPU time 1.04 seconds
Started Apr 21 12:47:26 PM PDT 24
Finished Apr 21 12:47:27 PM PDT 24
Peak memory 196592 kb
Host smart-7d77faed-0368-4b37-8a4c-ff95c06ed28f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3258916342 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_full_random.3258916342
Directory /workspace/35.gpio_full_random/latest

Test location /workspace/coverage/default/35.gpio_intr_rand_pgm.2604175937
Short name T427
Test name
Test status
Simulation time 43650638 ps
CPU time 0.71 seconds
Started Apr 21 12:47:18 PM PDT 24
Finished Apr 21 12:47:19 PM PDT 24
Peak memory 194492 kb
Host smart-b1af1d06-cbab-472f-a5bd-0d5561c99a9b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2604175937 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_intr_rand_pgm.2604175937
Directory /workspace/35.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/35.gpio_intr_with_filter_rand_intr_event.5925822
Short name T352
Test name
Test status
Simulation time 102307810 ps
CPU time 1.02 seconds
Started Apr 21 12:47:17 PM PDT 24
Finished Apr 21 12:47:19 PM PDT 24
Peak memory 196316 kb
Host smart-b603ce1a-c39e-4af4-b398-069229e2389f
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5925822 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SE
Q=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 35.gpio_intr_with_filter_rand_intr_event.5925822
Directory /workspace/35.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/35.gpio_rand_intr_trigger.2611063733
Short name T537
Test name
Test status
Simulation time 41527050 ps
CPU time 1.07 seconds
Started Apr 21 12:47:27 PM PDT 24
Finished Apr 21 12:47:29 PM PDT 24
Peak memory 195628 kb
Host smart-99910551-ae6c-4176-b6f5-80001493f36f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2611063733 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_rand_intr_trigger
.2611063733
Directory /workspace/35.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/35.gpio_random_dout_din.2512278645
Short name T667
Test name
Test status
Simulation time 204156938 ps
CPU time 1.04 seconds
Started Apr 21 12:47:18 PM PDT 24
Finished Apr 21 12:47:19 PM PDT 24
Peak memory 196116 kb
Host smart-d4fb25c2-f0d7-40b8-b1a1-0448a471b87d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2512278645 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_random_dout_din.2512278645
Directory /workspace/35.gpio_random_dout_din/latest

Test location /workspace/coverage/default/35.gpio_random_dout_din_no_pullup_pulldown.1996942334
Short name T158
Test name
Test status
Simulation time 47018040 ps
CPU time 0.82 seconds
Started Apr 21 12:47:18 PM PDT 24
Finished Apr 21 12:47:20 PM PDT 24
Peak memory 195676 kb
Host smart-7e3715aa-077a-465a-992b-a5ee74a2076c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1996942334 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_random_dout_din_no_pullu
p_pulldown.1996942334
Directory /workspace/35.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/35.gpio_random_long_reg_writes_reg_reads.3355119069
Short name T457
Test name
Test status
Simulation time 431481952 ps
CPU time 5.22 seconds
Started Apr 21 12:47:19 PM PDT 24
Finished Apr 21 12:47:24 PM PDT 24
Peak memory 198128 kb
Host smart-10968bdd-f6e5-4e59-a7f0-5aa23c528b3a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3355119069 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_ra
ndom_long_reg_writes_reg_reads.3355119069
Directory /workspace/35.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/35.gpio_smoke.1754857351
Short name T341
Test name
Test status
Simulation time 52524044 ps
CPU time 0.87 seconds
Started Apr 21 12:47:14 PM PDT 24
Finished Apr 21 12:47:15 PM PDT 24
Peak memory 196456 kb
Host smart-950eabf7-469d-409a-a107-9203126a2bd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1754857351 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_smoke.1754857351
Directory /workspace/35.gpio_smoke/latest

Test location /workspace/coverage/default/35.gpio_smoke_no_pullup_pulldown.134773757
Short name T249
Test name
Test status
Simulation time 30834776 ps
CPU time 0.88 seconds
Started Apr 21 12:47:21 PM PDT 24
Finished Apr 21 12:47:23 PM PDT 24
Peak memory 195404 kb
Host smart-73b50326-c45f-42c6-b7b5-d9c4dd5d7ea7
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=134773757 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_no_pullup_pulldown.134773757
Directory /workspace/35.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/35.gpio_stress_all.1094613435
Short name T13
Test name
Test status
Simulation time 17798385934 ps
CPU time 104.09 seconds
Started Apr 21 12:47:20 PM PDT 24
Finished Apr 21 12:49:05 PM PDT 24
Peak memory 198308 kb
Host smart-be078e96-4898-441c-979a-e934e3c96580
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1094613435 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.
gpio_stress_all.1094613435
Directory /workspace/35.gpio_stress_all/latest

Test location /workspace/coverage/default/35.gpio_stress_all_with_rand_reset.2340105536
Short name T538
Test name
Test status
Simulation time 13929979771 ps
CPU time 385.14 seconds
Started Apr 21 12:47:16 PM PDT 24
Finished Apr 21 12:53:41 PM PDT 24
Peak memory 198376 kb
Host smart-04bc8c1c-6f32-4fe4-b1cb-99893c97a0aa
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2340105536 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_stress_all_with_rand_reset.2340105536
Directory /workspace/35.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.gpio_alert_test.1037131325
Short name T278
Test name
Test status
Simulation time 13841685 ps
CPU time 0.59 seconds
Started Apr 21 12:47:19 PM PDT 24
Finished Apr 21 12:47:20 PM PDT 24
Peak memory 194104 kb
Host smart-7773969a-9a7d-4293-b4aa-6aeb7456bc83
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1037131325 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_alert_test.1037131325
Directory /workspace/36.gpio_alert_test/latest

Test location /workspace/coverage/default/36.gpio_dout_din_regs_random_rw.3346641947
Short name T606
Test name
Test status
Simulation time 56093222 ps
CPU time 0.93 seconds
Started Apr 21 12:47:22 PM PDT 24
Finished Apr 21 12:47:24 PM PDT 24
Peak memory 196236 kb
Host smart-6d3ac394-c56e-41e5-8f2b-88a065f8e152
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3346641947 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_dout_din_regs_random_rw.3346641947
Directory /workspace/36.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/36.gpio_filter_stress.2774483340
Short name T347
Test name
Test status
Simulation time 790246346 ps
CPU time 25.72 seconds
Started Apr 21 12:47:19 PM PDT 24
Finished Apr 21 12:47:45 PM PDT 24
Peak memory 196952 kb
Host smart-1d108ddb-d880-4174-a9eb-2e7430d4fe7a
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2774483340 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_filter_stre
ss.2774483340
Directory /workspace/36.gpio_filter_stress/latest

Test location /workspace/coverage/default/36.gpio_full_random.4258879813
Short name T592
Test name
Test status
Simulation time 116634991 ps
CPU time 0.71 seconds
Started Apr 21 12:47:15 PM PDT 24
Finished Apr 21 12:47:16 PM PDT 24
Peak memory 194856 kb
Host smart-324df6ac-d11b-442c-8abb-9cdf3a6c9a1c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4258879813 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_full_random.4258879813
Directory /workspace/36.gpio_full_random/latest

Test location /workspace/coverage/default/36.gpio_intr_rand_pgm.1292090209
Short name T407
Test name
Test status
Simulation time 435469576 ps
CPU time 0.69 seconds
Started Apr 21 12:47:21 PM PDT 24
Finished Apr 21 12:47:23 PM PDT 24
Peak memory 194528 kb
Host smart-62d79501-39a1-4ab0-85c8-6c0bb5879ee4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1292090209 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_intr_rand_pgm.1292090209
Directory /workspace/36.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/36.gpio_intr_with_filter_rand_intr_event.4157438439
Short name T501
Test name
Test status
Simulation time 68511238 ps
CPU time 0.91 seconds
Started Apr 21 12:47:21 PM PDT 24
Finished Apr 21 12:47:23 PM PDT 24
Peak memory 196004 kb
Host smart-3471bca5-65bc-494d-9be7-927ee4d73843
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4157438439 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 36.gpio_intr_with_filter_rand_intr_event.4157438439
Directory /workspace/36.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/36.gpio_rand_intr_trigger.1405899887
Short name T459
Test name
Test status
Simulation time 434551697 ps
CPU time 3.53 seconds
Started Apr 21 12:47:19 PM PDT 24
Finished Apr 21 12:47:23 PM PDT 24
Peak memory 196876 kb
Host smart-2702915c-c793-45df-96a9-6ef97d23617d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1405899887 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_rand_intr_trigger
.1405899887
Directory /workspace/36.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/36.gpio_random_dout_din.942599866
Short name T155
Test name
Test status
Simulation time 104287348 ps
CPU time 0.92 seconds
Started Apr 21 12:47:17 PM PDT 24
Finished Apr 21 12:47:18 PM PDT 24
Peak memory 196268 kb
Host smart-159b148c-165c-43a6-b022-840de1afbaa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=942599866 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_random_dout_din.942599866
Directory /workspace/36.gpio_random_dout_din/latest

Test location /workspace/coverage/default/36.gpio_random_dout_din_no_pullup_pulldown.1849287476
Short name T428
Test name
Test status
Simulation time 58275446 ps
CPU time 1.07 seconds
Started Apr 21 12:47:17 PM PDT 24
Finished Apr 21 12:47:19 PM PDT 24
Peak memory 196104 kb
Host smart-7cfe5c72-65f8-459c-ac14-5f668134217a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1849287476 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_random_dout_din_no_pullu
p_pulldown.1849287476
Directory /workspace/36.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/36.gpio_random_long_reg_writes_reg_reads.3940855061
Short name T74
Test name
Test status
Simulation time 87603337 ps
CPU time 3.84 seconds
Started Apr 21 12:47:27 PM PDT 24
Finished Apr 21 12:47:32 PM PDT 24
Peak memory 198172 kb
Host smart-1f1e6f3c-86fc-4329-80eb-83d17f678135
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3940855061 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_ra
ndom_long_reg_writes_reg_reads.3940855061
Directory /workspace/36.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/36.gpio_smoke.320712255
Short name T323
Test name
Test status
Simulation time 82050565 ps
CPU time 1.31 seconds
Started Apr 21 12:47:18 PM PDT 24
Finished Apr 21 12:47:20 PM PDT 24
Peak memory 197240 kb
Host smart-bda9f289-4049-42f9-93f6-0dfee436cb16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=320712255 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_smoke.320712255
Directory /workspace/36.gpio_smoke/latest

Test location /workspace/coverage/default/36.gpio_smoke_no_pullup_pulldown.2971620131
Short name T266
Test name
Test status
Simulation time 41952479 ps
CPU time 0.7 seconds
Started Apr 21 12:47:14 PM PDT 24
Finished Apr 21 12:47:15 PM PDT 24
Peak memory 194264 kb
Host smart-d824f414-2cc6-4189-b895-366ae56931d5
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2971620131 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_no_pullup_pulldown.2971620131
Directory /workspace/36.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/36.gpio_stress_all.3912103567
Short name T48
Test name
Test status
Simulation time 16639489162 ps
CPU time 94.58 seconds
Started Apr 21 12:47:22 PM PDT 24
Finished Apr 21 12:48:58 PM PDT 24
Peak memory 198324 kb
Host smart-03dae4ab-63dc-48b7-832f-0ba7ce5db8a4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3912103567 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.
gpio_stress_all.3912103567
Directory /workspace/36.gpio_stress_all/latest

Test location /workspace/coverage/default/37.gpio_alert_test.909389629
Short name T386
Test name
Test status
Simulation time 75840171 ps
CPU time 0.57 seconds
Started Apr 21 12:47:19 PM PDT 24
Finished Apr 21 12:47:20 PM PDT 24
Peak memory 194672 kb
Host smart-def3829f-c165-4891-85dd-17db42b30aa6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=909389629 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_alert_test.909389629
Directory /workspace/37.gpio_alert_test/latest

Test location /workspace/coverage/default/37.gpio_dout_din_regs_random_rw.4166158260
Short name T545
Test name
Test status
Simulation time 62211872 ps
CPU time 0.64 seconds
Started Apr 21 12:47:21 PM PDT 24
Finished Apr 21 12:47:22 PM PDT 24
Peak memory 193896 kb
Host smart-e142f239-2ab6-4968-9b0e-3b1b884291de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4166158260 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_dout_din_regs_random_rw.4166158260
Directory /workspace/37.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/37.gpio_filter_stress.152975936
Short name T455
Test name
Test status
Simulation time 1880687642 ps
CPU time 27.97 seconds
Started Apr 21 12:47:20 PM PDT 24
Finished Apr 21 12:47:48 PM PDT 24
Peak memory 196900 kb
Host smart-3a6a3595-c238-4472-973b-b6ffd8045112
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=152975936 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_filter_stres
s.152975936
Directory /workspace/37.gpio_filter_stress/latest

Test location /workspace/coverage/default/37.gpio_full_random.1598969229
Short name T453
Test name
Test status
Simulation time 56778779 ps
CPU time 0.91 seconds
Started Apr 21 12:47:17 PM PDT 24
Finished Apr 21 12:47:18 PM PDT 24
Peak memory 197420 kb
Host smart-ecb213f2-4813-4843-ad45-93bd222596b3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1598969229 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_full_random.1598969229
Directory /workspace/37.gpio_full_random/latest

Test location /workspace/coverage/default/37.gpio_intr_rand_pgm.2799130019
Short name T335
Test name
Test status
Simulation time 143009265 ps
CPU time 0.91 seconds
Started Apr 21 12:47:15 PM PDT 24
Finished Apr 21 12:47:17 PM PDT 24
Peak memory 196024 kb
Host smart-2e18459a-c5b6-48c8-852b-6c8b498422ce
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2799130019 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_intr_rand_pgm.2799130019
Directory /workspace/37.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/37.gpio_intr_with_filter_rand_intr_event.2275845635
Short name T582
Test name
Test status
Simulation time 183612678 ps
CPU time 3.51 seconds
Started Apr 21 12:47:18 PM PDT 24
Finished Apr 21 12:47:22 PM PDT 24
Peak memory 198332 kb
Host smart-da192d80-4a51-4101-96f8-132d0bbb7391
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2275845635 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 37.gpio_intr_with_filter_rand_intr_event.2275845635
Directory /workspace/37.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/37.gpio_rand_intr_trigger.2629701774
Short name T627
Test name
Test status
Simulation time 256828498 ps
CPU time 2.28 seconds
Started Apr 21 12:47:28 PM PDT 24
Finished Apr 21 12:47:30 PM PDT 24
Peak memory 198160 kb
Host smart-97a06efe-11dd-4d7a-a5c9-b8c9466f6488
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2629701774 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_rand_intr_trigger
.2629701774
Directory /workspace/37.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/37.gpio_random_dout_din.926764711
Short name T651
Test name
Test status
Simulation time 29916757 ps
CPU time 1.12 seconds
Started Apr 21 12:47:29 PM PDT 24
Finished Apr 21 12:47:31 PM PDT 24
Peak memory 197328 kb
Host smart-7638f6df-e4cd-4ce3-ac8d-5e86f31c39be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=926764711 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_random_dout_din.926764711
Directory /workspace/37.gpio_random_dout_din/latest

Test location /workspace/coverage/default/37.gpio_random_dout_din_no_pullup_pulldown.1988075269
Short name T208
Test name
Test status
Simulation time 73568093 ps
CPU time 0.85 seconds
Started Apr 21 12:47:21 PM PDT 24
Finished Apr 21 12:47:22 PM PDT 24
Peak memory 196864 kb
Host smart-af3fefd0-0176-4efa-8f7a-dcfad269e6a6
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1988075269 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_random_dout_din_no_pullu
p_pulldown.1988075269
Directory /workspace/37.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/37.gpio_random_long_reg_writes_reg_reads.520861070
Short name T164
Test name
Test status
Simulation time 425062697 ps
CPU time 4.9 seconds
Started Apr 21 12:47:24 PM PDT 24
Finished Apr 21 12:47:29 PM PDT 24
Peak memory 198244 kb
Host smart-e253a779-6854-4af9-8222-4d0a7d13db67
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=520861070 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_ran
dom_long_reg_writes_reg_reads.520861070
Directory /workspace/37.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/37.gpio_smoke.210296284
Short name T694
Test name
Test status
Simulation time 56121554 ps
CPU time 0.99 seconds
Started Apr 21 12:47:30 PM PDT 24
Finished Apr 21 12:47:31 PM PDT 24
Peak memory 196540 kb
Host smart-ab5aef0c-f999-48ef-8b3b-6d91d1b7e161
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=210296284 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_smoke.210296284
Directory /workspace/37.gpio_smoke/latest

Test location /workspace/coverage/default/37.gpio_smoke_no_pullup_pulldown.776381335
Short name T589
Test name
Test status
Simulation time 106305401 ps
CPU time 1.21 seconds
Started Apr 21 12:47:23 PM PDT 24
Finished Apr 21 12:47:25 PM PDT 24
Peak memory 196044 kb
Host smart-11523ffa-fb65-4655-acac-37289d3c7d05
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=776381335 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_no_pullup_pulldown.776381335
Directory /workspace/37.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/37.gpio_stress_all.3836336640
Short name T637
Test name
Test status
Simulation time 8209849951 ps
CPU time 24.02 seconds
Started Apr 21 12:47:36 PM PDT 24
Finished Apr 21 12:48:00 PM PDT 24
Peak memory 198212 kb
Host smart-4374ab76-309b-4235-bea6-9f4e475d60b2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3836336640 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.
gpio_stress_all.3836336640
Directory /workspace/37.gpio_stress_all/latest

Test location /workspace/coverage/default/38.gpio_alert_test.1441756147
Short name T611
Test name
Test status
Simulation time 37315392 ps
CPU time 0.58 seconds
Started Apr 21 12:47:25 PM PDT 24
Finished Apr 21 12:47:26 PM PDT 24
Peak memory 195124 kb
Host smart-777befd8-878b-479b-8e7a-35c8977f5b26
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1441756147 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_alert_test.1441756147
Directory /workspace/38.gpio_alert_test/latest

Test location /workspace/coverage/default/38.gpio_dout_din_regs_random_rw.3886582886
Short name T706
Test name
Test status
Simulation time 248662955 ps
CPU time 0.93 seconds
Started Apr 21 12:47:19 PM PDT 24
Finished Apr 21 12:47:21 PM PDT 24
Peak memory 196088 kb
Host smart-b94b93d3-7747-4a0f-a693-388d9f9cebe2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3886582886 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_dout_din_regs_random_rw.3886582886
Directory /workspace/38.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/38.gpio_filter_stress.462047500
Short name T162
Test name
Test status
Simulation time 442132439 ps
CPU time 20.64 seconds
Started Apr 21 12:47:19 PM PDT 24
Finished Apr 21 12:47:40 PM PDT 24
Peak memory 197040 kb
Host smart-1cfb7acb-33b5-48da-8142-88b0ebc4481f
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=462047500 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_filter_stres
s.462047500
Directory /workspace/38.gpio_filter_stress/latest

Test location /workspace/coverage/default/38.gpio_full_random.3281072261
Short name T274
Test name
Test status
Simulation time 235089283 ps
CPU time 1.06 seconds
Started Apr 21 12:47:35 PM PDT 24
Finished Apr 21 12:47:37 PM PDT 24
Peak memory 196908 kb
Host smart-ef02ae15-2e79-4a49-a3e6-75af41f3f2c6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3281072261 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_full_random.3281072261
Directory /workspace/38.gpio_full_random/latest

Test location /workspace/coverage/default/38.gpio_intr_rand_pgm.803677162
Short name T402
Test name
Test status
Simulation time 33557993 ps
CPU time 1.03 seconds
Started Apr 21 12:47:21 PM PDT 24
Finished Apr 21 12:47:23 PM PDT 24
Peak memory 196176 kb
Host smart-84fbaeba-8dac-4ed9-8484-e3afde2841cb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=803677162 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_intr_rand_pgm.803677162
Directory /workspace/38.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/38.gpio_intr_with_filter_rand_intr_event.588156812
Short name T647
Test name
Test status
Simulation time 585876525 ps
CPU time 3.62 seconds
Started Apr 21 12:47:21 PM PDT 24
Finished Apr 21 12:47:26 PM PDT 24
Peak memory 198264 kb
Host smart-4d5e0797-523a-4b07-a0b6-73f1fcef456d
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=588156812 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 38.gpio_intr_with_filter_rand_intr_event.588156812
Directory /workspace/38.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/38.gpio_rand_intr_trigger.3091343903
Short name T645
Test name
Test status
Simulation time 374461747 ps
CPU time 2.74 seconds
Started Apr 21 12:47:22 PM PDT 24
Finished Apr 21 12:47:25 PM PDT 24
Peak memory 197132 kb
Host smart-df05f6a0-4794-4771-8322-c353b02013a6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3091343903 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_rand_intr_trigger
.3091343903
Directory /workspace/38.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/38.gpio_random_dout_din.1444768227
Short name T393
Test name
Test status
Simulation time 30420939 ps
CPU time 0.76 seconds
Started Apr 21 12:47:21 PM PDT 24
Finished Apr 21 12:47:23 PM PDT 24
Peak memory 196296 kb
Host smart-f17d3dcb-a47b-4c17-a534-51992ea47c50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1444768227 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_random_dout_din.1444768227
Directory /workspace/38.gpio_random_dout_din/latest

Test location /workspace/coverage/default/38.gpio_random_dout_din_no_pullup_pulldown.838130881
Short name T283
Test name
Test status
Simulation time 49852232 ps
CPU time 1.19 seconds
Started Apr 21 12:47:22 PM PDT 24
Finished Apr 21 12:47:24 PM PDT 24
Peak memory 196916 kb
Host smart-be2c2413-63f0-4699-bc53-df4cca78c216
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=838130881 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_random_dout_din_no_pullup
_pulldown.838130881
Directory /workspace/38.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/38.gpio_random_long_reg_writes_reg_reads.2506477493
Short name T535
Test name
Test status
Simulation time 332393822 ps
CPU time 3.77 seconds
Started Apr 21 12:47:24 PM PDT 24
Finished Apr 21 12:47:29 PM PDT 24
Peak memory 197972 kb
Host smart-6caad442-32a5-4724-bc01-df4bbeb88d08
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2506477493 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_ra
ndom_long_reg_writes_reg_reads.2506477493
Directory /workspace/38.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/38.gpio_smoke.3646660136
Short name T214
Test name
Test status
Simulation time 88189507 ps
CPU time 0.87 seconds
Started Apr 21 12:47:24 PM PDT 24
Finished Apr 21 12:47:26 PM PDT 24
Peak memory 196640 kb
Host smart-3d5d11fc-1409-41c9-9c66-980f9b15989d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3646660136 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_smoke.3646660136
Directory /workspace/38.gpio_smoke/latest

Test location /workspace/coverage/default/38.gpio_smoke_no_pullup_pulldown.1705262784
Short name T275
Test name
Test status
Simulation time 73909370 ps
CPU time 1.05 seconds
Started Apr 21 12:47:38 PM PDT 24
Finished Apr 21 12:47:40 PM PDT 24
Peak memory 195652 kb
Host smart-a30c3efa-9622-4c37-bc36-83fce718069f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1705262784 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_no_pullup_pulldown.1705262784
Directory /workspace/38.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/38.gpio_stress_all.1214161046
Short name T190
Test name
Test status
Simulation time 4905344087 ps
CPU time 68.77 seconds
Started Apr 21 12:47:31 PM PDT 24
Finished Apr 21 12:48:41 PM PDT 24
Peak memory 198324 kb
Host smart-58502f3f-dcbf-48c7-9e13-63ef08c32cfe
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1214161046 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.
gpio_stress_all.1214161046
Directory /workspace/38.gpio_stress_all/latest

Test location /workspace/coverage/default/38.gpio_stress_all_with_rand_reset.3148558123
Short name T400
Test name
Test status
Simulation time 27783720763 ps
CPU time 821.04 seconds
Started Apr 21 12:47:21 PM PDT 24
Finished Apr 21 01:01:03 PM PDT 24
Peak memory 198392 kb
Host smart-2e14f1eb-4869-4b7a-adb8-3b8a5a06a981
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3148558123 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_stress_all_with_rand_reset.3148558123
Directory /workspace/38.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.gpio_alert_test.3634279567
Short name T458
Test name
Test status
Simulation time 49174852 ps
CPU time 0.57 seconds
Started Apr 21 12:47:33 PM PDT 24
Finished Apr 21 12:47:34 PM PDT 24
Peak memory 194224 kb
Host smart-4fe480d2-0fcc-48b9-8140-0396e1ffa32a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3634279567 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_alert_test.3634279567
Directory /workspace/39.gpio_alert_test/latest

Test location /workspace/coverage/default/39.gpio_dout_din_regs_random_rw.499913526
Short name T163
Test name
Test status
Simulation time 97147754 ps
CPU time 0.83 seconds
Started Apr 21 12:47:29 PM PDT 24
Finished Apr 21 12:47:30 PM PDT 24
Peak memory 195924 kb
Host smart-797beba0-b53e-47e9-8f58-aa6f385aec82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=499913526 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_dout_din_regs_random_rw.499913526
Directory /workspace/39.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/39.gpio_filter_stress.2453189757
Short name T493
Test name
Test status
Simulation time 532672565 ps
CPU time 17.61 seconds
Started Apr 21 12:47:37 PM PDT 24
Finished Apr 21 12:47:55 PM PDT 24
Peak memory 197160 kb
Host smart-c4a49ef5-5d01-4baa-8eb4-20a2c6c313e7
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2453189757 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_filter_stre
ss.2453189757
Directory /workspace/39.gpio_filter_stress/latest

Test location /workspace/coverage/default/39.gpio_full_random.1759893625
Short name T353
Test name
Test status
Simulation time 55739642 ps
CPU time 0.99 seconds
Started Apr 21 12:47:38 PM PDT 24
Finished Apr 21 12:47:39 PM PDT 24
Peak memory 196868 kb
Host smart-797f1a04-4bfa-4f10-8fed-2dd06a297ead
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1759893625 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_full_random.1759893625
Directory /workspace/39.gpio_full_random/latest

Test location /workspace/coverage/default/39.gpio_intr_rand_pgm.2616182305
Short name T701
Test name
Test status
Simulation time 30768723 ps
CPU time 0.72 seconds
Started Apr 21 12:47:22 PM PDT 24
Finished Apr 21 12:47:24 PM PDT 24
Peak memory 195644 kb
Host smart-3f5d8727-4187-4d18-8d17-c827d52d5a0b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2616182305 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_intr_rand_pgm.2616182305
Directory /workspace/39.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/39.gpio_intr_with_filter_rand_intr_event.1030185632
Short name T502
Test name
Test status
Simulation time 302644273 ps
CPU time 3 seconds
Started Apr 21 12:47:22 PM PDT 24
Finished Apr 21 12:47:26 PM PDT 24
Peak memory 198188 kb
Host smart-dceaeda1-8eef-4c04-be86-dffbd23f6105
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1030185632 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 39.gpio_intr_with_filter_rand_intr_event.1030185632
Directory /workspace/39.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/39.gpio_rand_intr_trigger.1450871631
Short name T96
Test name
Test status
Simulation time 96901163 ps
CPU time 2.74 seconds
Started Apr 21 12:47:20 PM PDT 24
Finished Apr 21 12:47:23 PM PDT 24
Peak memory 197368 kb
Host smart-64d13571-9583-4f03-821f-e312b7ef4447
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1450871631 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_rand_intr_trigger
.1450871631
Directory /workspace/39.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/39.gpio_random_dout_din.2685243095
Short name T532
Test name
Test status
Simulation time 179707873 ps
CPU time 1.08 seconds
Started Apr 21 12:47:19 PM PDT 24
Finished Apr 21 12:47:21 PM PDT 24
Peak memory 196964 kb
Host smart-fbbba837-9e19-4dde-a75c-5d0937680f81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2685243095 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_random_dout_din.2685243095
Directory /workspace/39.gpio_random_dout_din/latest

Test location /workspace/coverage/default/39.gpio_random_dout_din_no_pullup_pulldown.2203313965
Short name T209
Test name
Test status
Simulation time 23768017 ps
CPU time 0.91 seconds
Started Apr 21 12:47:20 PM PDT 24
Finished Apr 21 12:47:22 PM PDT 24
Peak memory 196156 kb
Host smart-c172db8c-7b53-4ad0-bcde-a4607bb0a495
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2203313965 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_random_dout_din_no_pullu
p_pulldown.2203313965
Directory /workspace/39.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/39.gpio_random_long_reg_writes_reg_reads.1735993172
Short name T432
Test name
Test status
Simulation time 780297521 ps
CPU time 5.49 seconds
Started Apr 21 12:47:20 PM PDT 24
Finished Apr 21 12:47:26 PM PDT 24
Peak memory 198260 kb
Host smart-013f210a-2781-4348-b7dc-283e8044ec92
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1735993172 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_ra
ndom_long_reg_writes_reg_reads.1735993172
Directory /workspace/39.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/39.gpio_smoke.3694026921
Short name T399
Test name
Test status
Simulation time 59803783 ps
CPU time 1.1 seconds
Started Apr 21 12:47:21 PM PDT 24
Finished Apr 21 12:47:23 PM PDT 24
Peak memory 196532 kb
Host smart-8f4732bb-6ae2-41ac-b41e-09f562ed8dba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3694026921 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_smoke.3694026921
Directory /workspace/39.gpio_smoke/latest

Test location /workspace/coverage/default/39.gpio_smoke_no_pullup_pulldown.1433542625
Short name T549
Test name
Test status
Simulation time 240073480 ps
CPU time 1.25 seconds
Started Apr 21 12:47:25 PM PDT 24
Finished Apr 21 12:47:27 PM PDT 24
Peak memory 195764 kb
Host smart-f1878f53-dfe4-4fd6-ac27-f03cd0d1f8ea
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1433542625 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_no_pullup_pulldown.1433542625
Directory /workspace/39.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/39.gpio_stress_all.487933740
Short name T116
Test name
Test status
Simulation time 8950106542 ps
CPU time 125.15 seconds
Started Apr 21 12:47:29 PM PDT 24
Finished Apr 21 12:49:35 PM PDT 24
Peak memory 198252 kb
Host smart-e99d7883-2ae1-4b00-ab9c-5bcc9ae1ec8d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=487933740 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.g
pio_stress_all.487933740
Directory /workspace/39.gpio_stress_all/latest

Test location /workspace/coverage/default/4.gpio_alert_test.1892865981
Short name T330
Test name
Test status
Simulation time 48872990 ps
CPU time 0.57 seconds
Started Apr 21 12:46:03 PM PDT 24
Finished Apr 21 12:46:06 PM PDT 24
Peak memory 194884 kb
Host smart-657bb19e-8af5-439a-978d-521708675b00
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1892865981 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_alert_test.1892865981
Directory /workspace/4.gpio_alert_test/latest

Test location /workspace/coverage/default/4.gpio_dout_din_regs_random_rw.544694341
Short name T91
Test name
Test status
Simulation time 137994765 ps
CPU time 0.77 seconds
Started Apr 21 12:46:02 PM PDT 24
Finished Apr 21 12:46:04 PM PDT 24
Peak memory 195340 kb
Host smart-6146f949-97d7-4ec6-95ba-bcc65e56623e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=544694341 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_dout_din_regs_random_rw.544694341
Directory /workspace/4.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/4.gpio_filter_stress.639513964
Short name T29
Test name
Test status
Simulation time 229960564 ps
CPU time 10.57 seconds
Started Apr 21 12:46:53 PM PDT 24
Finished Apr 21 12:47:04 PM PDT 24
Peak memory 197968 kb
Host smart-86a84f49-e2af-4ad5-8ecc-79127be404e3
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=639513964 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_filter_stress
.639513964
Directory /workspace/4.gpio_filter_stress/latest

Test location /workspace/coverage/default/4.gpio_full_random.1806192170
Short name T621
Test name
Test status
Simulation time 320351275 ps
CPU time 1.07 seconds
Started Apr 21 12:46:06 PM PDT 24
Finished Apr 21 12:46:08 PM PDT 24
Peak memory 196524 kb
Host smart-e49af7d3-d1c0-40dd-a53c-58ba6623c9f7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1806192170 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_full_random.1806192170
Directory /workspace/4.gpio_full_random/latest

Test location /workspace/coverage/default/4.gpio_intr_rand_pgm.572490248
Short name T599
Test name
Test status
Simulation time 119817949 ps
CPU time 1.04 seconds
Started Apr 21 12:46:10 PM PDT 24
Finished Apr 21 12:46:12 PM PDT 24
Peak memory 196224 kb
Host smart-fd7c0de6-2041-47fc-8575-a329d8631ad1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=572490248 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_intr_rand_pgm.572490248
Directory /workspace/4.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/4.gpio_intr_with_filter_rand_intr_event.46775897
Short name T226
Test name
Test status
Simulation time 60165585 ps
CPU time 2.43 seconds
Started Apr 21 12:46:07 PM PDT 24
Finished Apr 21 12:46:10 PM PDT 24
Peak memory 198168 kb
Host smart-9ff026c4-221a-49dc-b75a-9307483ec32a
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46775897 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 4.gpio_intr_with_filter_rand_intr_event.46775897
Directory /workspace/4.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/4.gpio_rand_intr_trigger.3299918955
Short name T17
Test name
Test status
Simulation time 164823763 ps
CPU time 1.39 seconds
Started Apr 21 12:46:02 PM PDT 24
Finished Apr 21 12:46:04 PM PDT 24
Peak memory 196876 kb
Host smart-ccdf67ae-662f-4d8e-9fa9-ea3d07a37c22
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3299918955 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_rand_intr_trigger.
3299918955
Directory /workspace/4.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/4.gpio_random_dout_din.1483246319
Short name T195
Test name
Test status
Simulation time 16898470 ps
CPU time 0.72 seconds
Started Apr 21 12:46:02 PM PDT 24
Finished Apr 21 12:46:04 PM PDT 24
Peak memory 196396 kb
Host smart-7c1818b2-9714-4cb9-ad44-75c64c04676a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1483246319 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_random_dout_din.1483246319
Directory /workspace/4.gpio_random_dout_din/latest

Test location /workspace/coverage/default/4.gpio_random_dout_din_no_pullup_pulldown.2031732142
Short name T614
Test name
Test status
Simulation time 55414537 ps
CPU time 1.04 seconds
Started Apr 21 12:46:04 PM PDT 24
Finished Apr 21 12:46:07 PM PDT 24
Peak memory 196008 kb
Host smart-faaa4f13-7557-4e4f-ad34-b2adfa44be74
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2031732142 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_random_dout_din_no_pullup
_pulldown.2031732142
Directory /workspace/4.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/4.gpio_random_long_reg_writes_reg_reads.98731051
Short name T36
Test name
Test status
Simulation time 771897331 ps
CPU time 3.65 seconds
Started Apr 21 12:45:52 PM PDT 24
Finished Apr 21 12:45:56 PM PDT 24
Peak memory 198124 kb
Host smart-8932a5eb-a51a-49bf-91e2-218ad4eabdc3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98731051 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_w
rites_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_rando
m_long_reg_writes_reg_reads.98731051
Directory /workspace/4.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/4.gpio_smoke.3974713294
Short name T511
Test name
Test status
Simulation time 28988112 ps
CPU time 0.89 seconds
Started Apr 21 12:45:59 PM PDT 24
Finished Apr 21 12:46:01 PM PDT 24
Peak memory 196388 kb
Host smart-4c704d9e-e33d-4ebf-b07c-05e5674bd0cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3974713294 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_smoke.3974713294
Directory /workspace/4.gpio_smoke/latest

Test location /workspace/coverage/default/4.gpio_smoke_no_pullup_pulldown.1636527090
Short name T272
Test name
Test status
Simulation time 48106430 ps
CPU time 0.97 seconds
Started Apr 21 12:46:02 PM PDT 24
Finished Apr 21 12:46:04 PM PDT 24
Peak memory 197420 kb
Host smart-19c16982-dde3-4d83-957d-a33974df91c9
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1636527090 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_no_pullup_pulldown.1636527090
Directory /workspace/4.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/4.gpio_stress_all.3189421416
Short name T487
Test name
Test status
Simulation time 23372485841 ps
CPU time 119.03 seconds
Started Apr 21 12:46:04 PM PDT 24
Finished Apr 21 12:48:05 PM PDT 24
Peak memory 198396 kb
Host smart-870744ae-b0ba-401a-877e-3c352e8df6fc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3189421416 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.g
pio_stress_all.3189421416
Directory /workspace/4.gpio_stress_all/latest

Test location /workspace/coverage/default/40.gpio_alert_test.2829054964
Short name T332
Test name
Test status
Simulation time 24280924 ps
CPU time 0.59 seconds
Started Apr 21 12:47:22 PM PDT 24
Finished Apr 21 12:47:23 PM PDT 24
Peak memory 194304 kb
Host smart-fb152daa-a791-4c27-9820-fa3581242d44
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2829054964 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_alert_test.2829054964
Directory /workspace/40.gpio_alert_test/latest

Test location /workspace/coverage/default/40.gpio_dout_din_regs_random_rw.1516500945
Short name T224
Test name
Test status
Simulation time 47367539 ps
CPU time 0.73 seconds
Started Apr 21 12:47:27 PM PDT 24
Finished Apr 21 12:47:28 PM PDT 24
Peak memory 195376 kb
Host smart-1f23c053-2569-4022-a7bf-5046b678bb7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1516500945 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_dout_din_regs_random_rw.1516500945
Directory /workspace/40.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/40.gpio_filter_stress.3802509893
Short name T345
Test name
Test status
Simulation time 129498963 ps
CPU time 5.11 seconds
Started Apr 21 12:47:26 PM PDT 24
Finished Apr 21 12:47:32 PM PDT 24
Peak memory 196924 kb
Host smart-f357c38b-50f6-4c5c-992b-bdf77349fd8b
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3802509893 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_filter_stre
ss.3802509893
Directory /workspace/40.gpio_filter_stress/latest

Test location /workspace/coverage/default/40.gpio_full_random.3237177778
Short name T150
Test name
Test status
Simulation time 277084038 ps
CPU time 0.88 seconds
Started Apr 21 12:47:21 PM PDT 24
Finished Apr 21 12:47:23 PM PDT 24
Peak memory 196232 kb
Host smart-6d19f8bb-f4ef-4695-a7c7-81fb4704207b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3237177778 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_full_random.3237177778
Directory /workspace/40.gpio_full_random/latest

Test location /workspace/coverage/default/40.gpio_intr_rand_pgm.904039434
Short name T394
Test name
Test status
Simulation time 279863731 ps
CPU time 1.33 seconds
Started Apr 21 12:47:25 PM PDT 24
Finished Apr 21 12:47:27 PM PDT 24
Peak memory 197028 kb
Host smart-e052d925-bc56-4657-8dcf-5c911cb70b30
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=904039434 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_intr_rand_pgm.904039434
Directory /workspace/40.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/40.gpio_intr_with_filter_rand_intr_event.727695928
Short name T261
Test name
Test status
Simulation time 50982593 ps
CPU time 2.11 seconds
Started Apr 21 12:47:26 PM PDT 24
Finished Apr 21 12:47:29 PM PDT 24
Peak memory 198320 kb
Host smart-2c05999b-da48-44ee-acd5-fcf20fd85a3d
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=727695928 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 40.gpio_intr_with_filter_rand_intr_event.727695928
Directory /workspace/40.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/40.gpio_rand_intr_trigger.749487481
Short name T655
Test name
Test status
Simulation time 213628732 ps
CPU time 1.86 seconds
Started Apr 21 12:47:23 PM PDT 24
Finished Apr 21 12:47:25 PM PDT 24
Peak memory 196888 kb
Host smart-9b52f057-4cca-41ec-b7a3-a38771576b0e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=749487481 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_rand_intr_trigger.
749487481
Directory /workspace/40.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/40.gpio_random_dout_din.1711851356
Short name T618
Test name
Test status
Simulation time 25666373 ps
CPU time 0.88 seconds
Started Apr 21 12:47:24 PM PDT 24
Finished Apr 21 12:47:26 PM PDT 24
Peak memory 196020 kb
Host smart-e61d3faf-cd5a-46f6-8581-74324f767844
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1711851356 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_random_dout_din.1711851356
Directory /workspace/40.gpio_random_dout_din/latest

Test location /workspace/coverage/default/40.gpio_random_dout_din_no_pullup_pulldown.3935925082
Short name T205
Test name
Test status
Simulation time 73362487 ps
CPU time 1.02 seconds
Started Apr 21 12:47:29 PM PDT 24
Finished Apr 21 12:47:31 PM PDT 24
Peak memory 195888 kb
Host smart-791237b1-17d3-4f27-9c39-459ed5c07134
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3935925082 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_random_dout_din_no_pullu
p_pulldown.3935925082
Directory /workspace/40.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/40.gpio_random_long_reg_writes_reg_reads.1168510344
Short name T307
Test name
Test status
Simulation time 81329958 ps
CPU time 1.43 seconds
Started Apr 21 12:47:20 PM PDT 24
Finished Apr 21 12:47:22 PM PDT 24
Peak memory 198240 kb
Host smart-532189bc-0a3b-47a7-85b5-1e5f21aa98d7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1168510344 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_ra
ndom_long_reg_writes_reg_reads.1168510344
Directory /workspace/40.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/40.gpio_smoke.3833777876
Short name T238
Test name
Test status
Simulation time 57889828 ps
CPU time 0.81 seconds
Started Apr 21 12:47:20 PM PDT 24
Finished Apr 21 12:47:21 PM PDT 24
Peak memory 196160 kb
Host smart-c72dbee0-3ac0-4301-a3e4-92cd4a371990
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3833777876 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_smoke.3833777876
Directory /workspace/40.gpio_smoke/latest

Test location /workspace/coverage/default/40.gpio_smoke_no_pullup_pulldown.2988489550
Short name T636
Test name
Test status
Simulation time 45708411 ps
CPU time 1.16 seconds
Started Apr 21 12:47:32 PM PDT 24
Finished Apr 21 12:47:34 PM PDT 24
Peak memory 195864 kb
Host smart-985dd916-e2e6-4a74-b47d-55be031c68e1
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2988489550 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_no_pullup_pulldown.2988489550
Directory /workspace/40.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/40.gpio_stress_all.1781685831
Short name T664
Test name
Test status
Simulation time 21269375112 ps
CPU time 147.22 seconds
Started Apr 21 12:47:19 PM PDT 24
Finished Apr 21 12:49:47 PM PDT 24
Peak memory 198260 kb
Host smart-7e02b0ae-da03-459f-a278-bae09fe64b50
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1781685831 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.
gpio_stress_all.1781685831
Directory /workspace/40.gpio_stress_all/latest

Test location /workspace/coverage/default/41.gpio_alert_test.539558952
Short name T159
Test name
Test status
Simulation time 16077637 ps
CPU time 0.64 seconds
Started Apr 21 12:47:25 PM PDT 24
Finished Apr 21 12:47:26 PM PDT 24
Peak memory 194284 kb
Host smart-eff51861-7e5b-407f-8f97-86aa708eb8f5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=539558952 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_alert_test.539558952
Directory /workspace/41.gpio_alert_test/latest

Test location /workspace/coverage/default/41.gpio_dout_din_regs_random_rw.4247032809
Short name T629
Test name
Test status
Simulation time 29583699 ps
CPU time 0.73 seconds
Started Apr 21 12:47:21 PM PDT 24
Finished Apr 21 12:47:22 PM PDT 24
Peak memory 196120 kb
Host smart-fa659fc6-01ce-4d55-bdfa-4e034544f61a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4247032809 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_dout_din_regs_random_rw.4247032809
Directory /workspace/41.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/41.gpio_filter_stress.552304055
Short name T686
Test name
Test status
Simulation time 739062861 ps
CPU time 18.65 seconds
Started Apr 21 12:47:34 PM PDT 24
Finished Apr 21 12:47:53 PM PDT 24
Peak memory 198180 kb
Host smart-27ba6311-4248-49da-983b-297f2b59a0d4
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=552304055 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_filter_stres
s.552304055
Directory /workspace/41.gpio_filter_stress/latest

Test location /workspace/coverage/default/41.gpio_full_random.994477101
Short name T242
Test name
Test status
Simulation time 319455948 ps
CPU time 1.12 seconds
Started Apr 21 12:47:36 PM PDT 24
Finished Apr 21 12:47:38 PM PDT 24
Peak memory 196804 kb
Host smart-ee43bf6d-89ac-4c0b-87f6-3ebf155ba224
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=994477101 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_full_random.994477101
Directory /workspace/41.gpio_full_random/latest

Test location /workspace/coverage/default/41.gpio_intr_rand_pgm.869137587
Short name T231
Test name
Test status
Simulation time 41854141 ps
CPU time 0.99 seconds
Started Apr 21 12:47:26 PM PDT 24
Finished Apr 21 12:47:27 PM PDT 24
Peak memory 197040 kb
Host smart-d7a117b6-5fa8-42ab-a258-ce8c6886fd80
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=869137587 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_intr_rand_pgm.869137587
Directory /workspace/41.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/41.gpio_intr_with_filter_rand_intr_event.3828418728
Short name T575
Test name
Test status
Simulation time 83257785 ps
CPU time 1.71 seconds
Started Apr 21 12:47:25 PM PDT 24
Finished Apr 21 12:47:27 PM PDT 24
Peak memory 197368 kb
Host smart-2c80e1cf-728f-43a2-b7bd-ca34f33d0bfb
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3828418728 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 41.gpio_intr_with_filter_rand_intr_event.3828418728
Directory /workspace/41.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/41.gpio_rand_intr_trigger.134340110
Short name T682
Test name
Test status
Simulation time 210758441 ps
CPU time 2.11 seconds
Started Apr 21 12:47:21 PM PDT 24
Finished Apr 21 12:47:25 PM PDT 24
Peak memory 195900 kb
Host smart-c89c2765-e04d-450b-b626-00205e74401f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=134340110 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_rand_intr_trigger.
134340110
Directory /workspace/41.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/41.gpio_random_dout_din.2026460794
Short name T189
Test name
Test status
Simulation time 196566525 ps
CPU time 1.07 seconds
Started Apr 21 12:47:33 PM PDT 24
Finished Apr 21 12:47:34 PM PDT 24
Peak memory 196728 kb
Host smart-cadc9dd4-e5d7-4dc5-b61a-f3d68233c285
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2026460794 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_random_dout_din.2026460794
Directory /workspace/41.gpio_random_dout_din/latest

Test location /workspace/coverage/default/41.gpio_random_dout_din_no_pullup_pulldown.545938307
Short name T539
Test name
Test status
Simulation time 53722866 ps
CPU time 0.77 seconds
Started Apr 21 12:47:35 PM PDT 24
Finished Apr 21 12:47:36 PM PDT 24
Peak memory 195716 kb
Host smart-fa116a04-192f-44de-8cc1-b82195a96aaa
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=545938307 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_random_dout_din_no_pullup
_pulldown.545938307
Directory /workspace/41.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/41.gpio_random_long_reg_writes_reg_reads.2785416205
Short name T77
Test name
Test status
Simulation time 132497211 ps
CPU time 5.67 seconds
Started Apr 21 12:47:34 PM PDT 24
Finished Apr 21 12:47:41 PM PDT 24
Peak memory 198020 kb
Host smart-2f6c7a2c-f011-494e-881d-f75728ee33d6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2785416205 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_ra
ndom_long_reg_writes_reg_reads.2785416205
Directory /workspace/41.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/41.gpio_smoke.1400266455
Short name T179
Test name
Test status
Simulation time 213565376 ps
CPU time 1.18 seconds
Started Apr 21 12:47:20 PM PDT 24
Finished Apr 21 12:47:21 PM PDT 24
Peak memory 195644 kb
Host smart-96f0897c-77fe-4ae5-ade2-042dafab047c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1400266455 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_smoke.1400266455
Directory /workspace/41.gpio_smoke/latest

Test location /workspace/coverage/default/41.gpio_smoke_no_pullup_pulldown.3030462037
Short name T379
Test name
Test status
Simulation time 140351492 ps
CPU time 1.15 seconds
Started Apr 21 12:47:33 PM PDT 24
Finished Apr 21 12:47:35 PM PDT 24
Peak memory 196660 kb
Host smart-7c384d86-c77e-485b-935a-b1aa00344efb
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3030462037 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_no_pullup_pulldown.3030462037
Directory /workspace/41.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/41.gpio_stress_all.3541727847
Short name T225
Test name
Test status
Simulation time 25495668342 ps
CPU time 186.16 seconds
Started Apr 21 12:47:33 PM PDT 24
Finished Apr 21 12:50:40 PM PDT 24
Peak memory 198384 kb
Host smart-8c43d2be-81ee-4510-b7b9-f34d05f43ed0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3541727847 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.
gpio_stress_all.3541727847
Directory /workspace/41.gpio_stress_all/latest

Test location /workspace/coverage/default/41.gpio_stress_all_with_rand_reset.2685353957
Short name T14
Test name
Test status
Simulation time 209383242125 ps
CPU time 1601.23 seconds
Started Apr 21 12:47:40 PM PDT 24
Finished Apr 21 01:14:22 PM PDT 24
Peak memory 198316 kb
Host smart-11095ed4-dbee-40a5-a2a1-a8819bf04aa9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2685353957 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_stress_all_with_rand_reset.2685353957
Directory /workspace/41.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.gpio_alert_test.206651467
Short name T716
Test name
Test status
Simulation time 12737612 ps
CPU time 0.6 seconds
Started Apr 21 12:47:32 PM PDT 24
Finished Apr 21 12:47:33 PM PDT 24
Peak memory 194064 kb
Host smart-e6c9d51e-f4c5-43bf-885a-1d8239315724
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=206651467 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_alert_test.206651467
Directory /workspace/42.gpio_alert_test/latest

Test location /workspace/coverage/default/42.gpio_dout_din_regs_random_rw.1505460862
Short name T111
Test name
Test status
Simulation time 158584912 ps
CPU time 0.65 seconds
Started Apr 21 12:47:38 PM PDT 24
Finished Apr 21 12:47:39 PM PDT 24
Peak memory 194320 kb
Host smart-d6156e6c-0ddd-42fd-ab09-b8c8b39644b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1505460862 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_dout_din_regs_random_rw.1505460862
Directory /workspace/42.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/42.gpio_filter_stress.1798833692
Short name T429
Test name
Test status
Simulation time 1669817856 ps
CPU time 12.17 seconds
Started Apr 21 12:47:21 PM PDT 24
Finished Apr 21 12:47:34 PM PDT 24
Peak memory 196904 kb
Host smart-0093b5e5-7490-4cc3-8a64-e0e1bb810d68
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1798833692 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_filter_stre
ss.1798833692
Directory /workspace/42.gpio_filter_stress/latest

Test location /workspace/coverage/default/42.gpio_full_random.1072877385
Short name T643
Test name
Test status
Simulation time 419329259 ps
CPU time 0.71 seconds
Started Apr 21 12:47:34 PM PDT 24
Finished Apr 21 12:47:35 PM PDT 24
Peak memory 194860 kb
Host smart-35738af1-f76e-480a-a517-fa2dd779571f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1072877385 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_full_random.1072877385
Directory /workspace/42.gpio_full_random/latest

Test location /workspace/coverage/default/42.gpio_intr_rand_pgm.3572420873
Short name T284
Test name
Test status
Simulation time 37578927 ps
CPU time 0.66 seconds
Started Apr 21 12:47:40 PM PDT 24
Finished Apr 21 12:47:41 PM PDT 24
Peak memory 194504 kb
Host smart-fe938577-9244-456e-984c-11fc8ac0074c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3572420873 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_intr_rand_pgm.3572420873
Directory /workspace/42.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/42.gpio_rand_intr_trigger.2558248423
Short name T296
Test name
Test status
Simulation time 108743606 ps
CPU time 2.41 seconds
Started Apr 21 12:47:21 PM PDT 24
Finished Apr 21 12:47:24 PM PDT 24
Peak memory 198228 kb
Host smart-2b7908f6-7dd8-4b4e-b19e-62805fa1e281
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2558248423 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_rand_intr_trigger
.2558248423
Directory /workspace/42.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/42.gpio_random_dout_din.2283098495
Short name T608
Test name
Test status
Simulation time 17670952 ps
CPU time 0.75 seconds
Started Apr 21 12:47:37 PM PDT 24
Finished Apr 21 12:47:38 PM PDT 24
Peak memory 195724 kb
Host smart-5ea59342-d98c-4cc2-a4b5-6ee888b9fdaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2283098495 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_random_dout_din.2283098495
Directory /workspace/42.gpio_random_dout_din/latest

Test location /workspace/coverage/default/42.gpio_random_dout_din_no_pullup_pulldown.79588337
Short name T677
Test name
Test status
Simulation time 27550611 ps
CPU time 1.11 seconds
Started Apr 21 12:47:30 PM PDT 24
Finished Apr 21 12:47:32 PM PDT 24
Peak memory 196688 kb
Host smart-b73f9c12-dd8b-4e10-ba18-e23864abed3c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79588337 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_random_dout_din_no_pullup_
pulldown.79588337
Directory /workspace/42.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/42.gpio_random_long_reg_writes_reg_reads.2515703116
Short name T263
Test name
Test status
Simulation time 53311655 ps
CPU time 2.42 seconds
Started Apr 21 12:47:43 PM PDT 24
Finished Apr 21 12:47:46 PM PDT 24
Peak memory 198236 kb
Host smart-3e60db27-2983-48b7-9fc8-0414a170d77d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2515703116 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_ra
ndom_long_reg_writes_reg_reads.2515703116
Directory /workspace/42.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/42.gpio_smoke.1848478612
Short name T417
Test name
Test status
Simulation time 136914759 ps
CPU time 1.32 seconds
Started Apr 21 12:47:36 PM PDT 24
Finished Apr 21 12:47:38 PM PDT 24
Peak memory 195776 kb
Host smart-89e1d54a-8fc6-4ae6-8aec-aa62e974c57a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1848478612 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_smoke.1848478612
Directory /workspace/42.gpio_smoke/latest

Test location /workspace/coverage/default/42.gpio_smoke_no_pullup_pulldown.974462631
Short name T437
Test name
Test status
Simulation time 23700328 ps
CPU time 0.89 seconds
Started Apr 21 12:47:45 PM PDT 24
Finished Apr 21 12:47:47 PM PDT 24
Peak memory 195980 kb
Host smart-9d811a3f-2d4f-49a3-9419-ade60c642224
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=974462631 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_no_pullup_pulldown.974462631
Directory /workspace/42.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/42.gpio_stress_all.1473174907
Short name T499
Test name
Test status
Simulation time 32562612103 ps
CPU time 225.84 seconds
Started Apr 21 12:47:44 PM PDT 24
Finished Apr 21 12:51:31 PM PDT 24
Peak memory 198176 kb
Host smart-767d98ab-6783-42e8-97a5-e3fe7f29ad1f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1473174907 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.
gpio_stress_all.1473174907
Directory /workspace/42.gpio_stress_all/latest

Test location /workspace/coverage/default/43.gpio_alert_test.245708209
Short name T578
Test name
Test status
Simulation time 50082638 ps
CPU time 0.62 seconds
Started Apr 21 12:47:35 PM PDT 24
Finished Apr 21 12:47:36 PM PDT 24
Peak memory 194988 kb
Host smart-915f5a6a-21d0-4737-b99e-a49b1da04e2c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=245708209 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_alert_test.245708209
Directory /workspace/43.gpio_alert_test/latest

Test location /workspace/coverage/default/43.gpio_dout_din_regs_random_rw.44802353
Short name T448
Test name
Test status
Simulation time 66413750 ps
CPU time 0.68 seconds
Started Apr 21 12:47:33 PM PDT 24
Finished Apr 21 12:47:34 PM PDT 24
Peak memory 194888 kb
Host smart-34a94906-75b1-47aa-8b89-4e97d5b21029
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=44802353 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_dout_din_regs_random_rw.44802353
Directory /workspace/43.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/43.gpio_filter_stress.1687594708
Short name T541
Test name
Test status
Simulation time 1968185670 ps
CPU time 16.98 seconds
Started Apr 21 12:47:21 PM PDT 24
Finished Apr 21 12:47:39 PM PDT 24
Peak memory 196948 kb
Host smart-080248f5-9451-4703-98ac-d5dad64901cb
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1687594708 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_filter_stre
ss.1687594708
Directory /workspace/43.gpio_filter_stress/latest

Test location /workspace/coverage/default/43.gpio_full_random.1305622464
Short name T374
Test name
Test status
Simulation time 62764016 ps
CPU time 0.92 seconds
Started Apr 21 12:47:44 PM PDT 24
Finished Apr 21 12:47:46 PM PDT 24
Peak memory 196328 kb
Host smart-d77d9f29-dc67-4b7d-b825-0a6196826f31
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1305622464 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_full_random.1305622464
Directory /workspace/43.gpio_full_random/latest

Test location /workspace/coverage/default/43.gpio_intr_rand_pgm.3714561680
Short name T513
Test name
Test status
Simulation time 103619625 ps
CPU time 1.48 seconds
Started Apr 21 12:47:32 PM PDT 24
Finished Apr 21 12:47:34 PM PDT 24
Peak memory 197368 kb
Host smart-a9ceb5ed-cfcf-4367-a020-ef0e18d45f97
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3714561680 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_intr_rand_pgm.3714561680
Directory /workspace/43.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/43.gpio_intr_with_filter_rand_intr_event.3138011087
Short name T471
Test name
Test status
Simulation time 182273068 ps
CPU time 2.72 seconds
Started Apr 21 12:47:23 PM PDT 24
Finished Apr 21 12:47:27 PM PDT 24
Peak memory 196712 kb
Host smart-1a2071e1-5d7d-4b3c-8ae4-ddaf15853ed6
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3138011087 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 43.gpio_intr_with_filter_rand_intr_event.3138011087
Directory /workspace/43.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/43.gpio_rand_intr_trigger.2369248183
Short name T348
Test name
Test status
Simulation time 175302316 ps
CPU time 3.43 seconds
Started Apr 21 12:47:34 PM PDT 24
Finished Apr 21 12:47:37 PM PDT 24
Peak memory 196676 kb
Host smart-4db8b231-1c42-4d16-b50f-aec687d8f55b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2369248183 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_rand_intr_trigger
.2369248183
Directory /workspace/43.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/43.gpio_random_dout_din.1383001495
Short name T662
Test name
Test status
Simulation time 55148942 ps
CPU time 0.87 seconds
Started Apr 21 12:47:29 PM PDT 24
Finished Apr 21 12:47:31 PM PDT 24
Peak memory 197604 kb
Host smart-1f4a32b3-ab5a-4371-97d4-508b5d0d1c9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1383001495 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_random_dout_din.1383001495
Directory /workspace/43.gpio_random_dout_din/latest

Test location /workspace/coverage/default/43.gpio_random_dout_din_no_pullup_pulldown.850121270
Short name T580
Test name
Test status
Simulation time 15942106 ps
CPU time 0.63 seconds
Started Apr 21 12:47:30 PM PDT 24
Finished Apr 21 12:47:31 PM PDT 24
Peak memory 194456 kb
Host smart-3aaa008e-b314-452c-abf5-851976f75053
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=850121270 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_random_dout_din_no_pullup
_pulldown.850121270
Directory /workspace/43.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/43.gpio_random_long_reg_writes_reg_reads.3491705163
Short name T31
Test name
Test status
Simulation time 387186031 ps
CPU time 4.92 seconds
Started Apr 21 12:47:37 PM PDT 24
Finished Apr 21 12:47:42 PM PDT 24
Peak memory 198196 kb
Host smart-4d2db08e-6589-4f55-90fe-01ef8ef9fe28
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3491705163 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_ra
ndom_long_reg_writes_reg_reads.3491705163
Directory /workspace/43.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/43.gpio_smoke.3396575964
Short name T241
Test name
Test status
Simulation time 311669447 ps
CPU time 1.16 seconds
Started Apr 21 12:47:30 PM PDT 24
Finished Apr 21 12:47:32 PM PDT 24
Peak memory 196556 kb
Host smart-9e956a9f-34fe-483a-af61-cd55af2b0812
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3396575964 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_smoke.3396575964
Directory /workspace/43.gpio_smoke/latest

Test location /workspace/coverage/default/43.gpio_smoke_no_pullup_pulldown.92737475
Short name T521
Test name
Test status
Simulation time 159075104 ps
CPU time 1.26 seconds
Started Apr 21 12:47:37 PM PDT 24
Finished Apr 21 12:47:39 PM PDT 24
Peak memory 196948 kb
Host smart-2c230f6c-eb81-4123-907f-6a8291b78f22
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92737475 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_no_pullup_pulldown.92737475
Directory /workspace/43.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/43.gpio_stress_all.2606343549
Short name T50
Test name
Test status
Simulation time 3157355115 ps
CPU time 46.45 seconds
Started Apr 21 12:47:35 PM PDT 24
Finished Apr 21 12:48:22 PM PDT 24
Peak memory 198376 kb
Host smart-f64d9284-6522-4cba-8846-bad098739ea4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2606343549 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.
gpio_stress_all.2606343549
Directory /workspace/43.gpio_stress_all/latest

Test location /workspace/coverage/default/44.gpio_alert_test.2265690124
Short name T368
Test name
Test status
Simulation time 21617444 ps
CPU time 0.56 seconds
Started Apr 21 12:47:44 PM PDT 24
Finished Apr 21 12:47:46 PM PDT 24
Peak memory 194096 kb
Host smart-90b795e9-4a48-428d-9035-2fb8d282bb8b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2265690124 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_alert_test.2265690124
Directory /workspace/44.gpio_alert_test/latest

Test location /workspace/coverage/default/44.gpio_dout_din_regs_random_rw.186718705
Short name T689
Test name
Test status
Simulation time 46410632 ps
CPU time 0.89 seconds
Started Apr 21 12:47:34 PM PDT 24
Finished Apr 21 12:47:36 PM PDT 24
Peak memory 196944 kb
Host smart-58f3913b-7de3-42fe-8814-d6dd0465b576
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=186718705 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_dout_din_regs_random_rw.186718705
Directory /workspace/44.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/44.gpio_filter_stress.2018375967
Short name T181
Test name
Test status
Simulation time 1935599207 ps
CPU time 18.71 seconds
Started Apr 21 12:47:32 PM PDT 24
Finished Apr 21 12:47:52 PM PDT 24
Peak memory 197048 kb
Host smart-bfa55466-ac56-440f-89cb-29ee6cae98bd
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2018375967 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_filter_stre
ss.2018375967
Directory /workspace/44.gpio_filter_stress/latest

Test location /workspace/coverage/default/44.gpio_full_random.472747627
Short name T97
Test name
Test status
Simulation time 47649974 ps
CPU time 0.78 seconds
Started Apr 21 12:47:44 PM PDT 24
Finished Apr 21 12:47:46 PM PDT 24
Peak memory 196000 kb
Host smart-22231fc4-8d34-4ee4-ae7a-52d689e65a20
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=472747627 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_full_random.472747627
Directory /workspace/44.gpio_full_random/latest

Test location /workspace/coverage/default/44.gpio_intr_rand_pgm.2933489233
Short name T529
Test name
Test status
Simulation time 38974527 ps
CPU time 0.87 seconds
Started Apr 21 12:47:44 PM PDT 24
Finished Apr 21 12:47:46 PM PDT 24
Peak memory 197704 kb
Host smart-2beb78e6-d569-4f65-ac6a-539e802870c4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2933489233 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_intr_rand_pgm.2933489233
Directory /workspace/44.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/44.gpio_intr_with_filter_rand_intr_event.1191769163
Short name T350
Test name
Test status
Simulation time 23023219 ps
CPU time 1 seconds
Started Apr 21 12:47:36 PM PDT 24
Finished Apr 21 12:47:38 PM PDT 24
Peak memory 196972 kb
Host smart-0422e26b-7a8a-40fe-98a4-7d4ab603c6b3
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1191769163 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 44.gpio_intr_with_filter_rand_intr_event.1191769163
Directory /workspace/44.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/44.gpio_rand_intr_trigger.62767286
Short name T494
Test name
Test status
Simulation time 104785851 ps
CPU time 3.13 seconds
Started Apr 21 12:47:36 PM PDT 24
Finished Apr 21 12:47:39 PM PDT 24
Peak memory 197172 kb
Host smart-c56ddcf8-0fa7-4ae8-ad8c-a336c1e34202
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62767286 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigger
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_rand_intr_trigger.62767286
Directory /workspace/44.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/44.gpio_random_dout_din.2962160030
Short name T112
Test name
Test status
Simulation time 53600631 ps
CPU time 1.17 seconds
Started Apr 21 12:47:37 PM PDT 24
Finished Apr 21 12:47:38 PM PDT 24
Peak memory 196068 kb
Host smart-74c1b554-3a33-4cde-9b25-1662a0c46896
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2962160030 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_random_dout_din.2962160030
Directory /workspace/44.gpio_random_dout_din/latest

Test location /workspace/coverage/default/44.gpio_random_dout_din_no_pullup_pulldown.3050984714
Short name T191
Test name
Test status
Simulation time 18310768 ps
CPU time 0.67 seconds
Started Apr 21 12:47:44 PM PDT 24
Finished Apr 21 12:47:45 PM PDT 24
Peak memory 194368 kb
Host smart-08a4cb86-df1c-4af4-805b-b8a7bc0d500a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3050984714 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_random_dout_din_no_pullu
p_pulldown.3050984714
Directory /workspace/44.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/44.gpio_random_long_reg_writes_reg_reads.716659559
Short name T364
Test name
Test status
Simulation time 659518368 ps
CPU time 2.08 seconds
Started Apr 21 12:47:39 PM PDT 24
Finished Apr 21 12:47:41 PM PDT 24
Peak memory 198096 kb
Host smart-a5ead340-0f7d-4bb7-99f2-37fa4b707a20
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=716659559 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_ran
dom_long_reg_writes_reg_reads.716659559
Directory /workspace/44.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/44.gpio_smoke.2729290570
Short name T641
Test name
Test status
Simulation time 85232039 ps
CPU time 0.93 seconds
Started Apr 21 12:47:39 PM PDT 24
Finished Apr 21 12:47:41 PM PDT 24
Peak memory 195632 kb
Host smart-63c304a4-1983-4996-86b7-9ac8701f8b75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2729290570 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_smoke.2729290570
Directory /workspace/44.gpio_smoke/latest

Test location /workspace/coverage/default/44.gpio_smoke_no_pullup_pulldown.1009127199
Short name T299
Test name
Test status
Simulation time 215339244 ps
CPU time 1.07 seconds
Started Apr 21 12:47:22 PM PDT 24
Finished Apr 21 12:47:24 PM PDT 24
Peak memory 195860 kb
Host smart-1abda4a3-4ae7-4368-aebf-13b0b045634b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1009127199 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_no_pullup_pulldown.1009127199
Directory /workspace/44.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/44.gpio_stress_all.3777075792
Short name T384
Test name
Test status
Simulation time 23700127531 ps
CPU time 58.72 seconds
Started Apr 21 12:47:40 PM PDT 24
Finished Apr 21 12:48:39 PM PDT 24
Peak memory 198360 kb
Host smart-1ad60a1a-ed4c-49d9-93cf-82168a1df2eb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3777075792 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.
gpio_stress_all.3777075792
Directory /workspace/44.gpio_stress_all/latest

Test location /workspace/coverage/default/44.gpio_stress_all_with_rand_reset.641945715
Short name T702
Test name
Test status
Simulation time 311354492274 ps
CPU time 1321.59 seconds
Started Apr 21 12:47:31 PM PDT 24
Finished Apr 21 01:09:33 PM PDT 24
Peak memory 198352 kb
Host smart-7e8928ab-f4e4-4c77-8009-12086d8ad5e5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=641945715 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_stress_all_with_rand_reset.641945715
Directory /workspace/44.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.gpio_alert_test.3767724540
Short name T596
Test name
Test status
Simulation time 56645814 ps
CPU time 0.59 seconds
Started Apr 21 12:47:50 PM PDT 24
Finished Apr 21 12:47:51 PM PDT 24
Peak memory 194652 kb
Host smart-dcbe8b4b-b5a7-4879-8f29-2af544f40794
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3767724540 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_alert_test.3767724540
Directory /workspace/45.gpio_alert_test/latest

Test location /workspace/coverage/default/45.gpio_dout_din_regs_random_rw.877468790
Short name T556
Test name
Test status
Simulation time 48713390 ps
CPU time 0.73 seconds
Started Apr 21 12:47:34 PM PDT 24
Finished Apr 21 12:47:36 PM PDT 24
Peak memory 195372 kb
Host smart-78bf2519-c237-46d3-b3b2-d7c4969db549
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=877468790 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_dout_din_regs_random_rw.877468790
Directory /workspace/45.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/45.gpio_filter_stress.2967479794
Short name T605
Test name
Test status
Simulation time 415508427 ps
CPU time 11.26 seconds
Started Apr 21 12:47:32 PM PDT 24
Finished Apr 21 12:47:44 PM PDT 24
Peak memory 197004 kb
Host smart-4473a2ac-1939-4ac2-9739-7ebcd5863746
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2967479794 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_filter_stre
ss.2967479794
Directory /workspace/45.gpio_filter_stress/latest

Test location /workspace/coverage/default/45.gpio_full_random.961045379
Short name T649
Test name
Test status
Simulation time 87561644 ps
CPU time 0.67 seconds
Started Apr 21 12:47:46 PM PDT 24
Finished Apr 21 12:47:47 PM PDT 24
Peak memory 194888 kb
Host smart-bfd91f18-96bb-4bd1-bf54-5370f23d2fe3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=961045379 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_full_random.961045379
Directory /workspace/45.gpio_full_random/latest

Test location /workspace/coverage/default/45.gpio_intr_rand_pgm.1109096023
Short name T322
Test name
Test status
Simulation time 107684678 ps
CPU time 1.41 seconds
Started Apr 21 12:47:30 PM PDT 24
Finished Apr 21 12:47:32 PM PDT 24
Peak memory 197216 kb
Host smart-fa7430d8-085c-46fd-b546-ae2d718f7634
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1109096023 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_intr_rand_pgm.1109096023
Directory /workspace/45.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/45.gpio_intr_with_filter_rand_intr_event.2846023611
Short name T248
Test name
Test status
Simulation time 277825503 ps
CPU time 2.85 seconds
Started Apr 21 12:47:39 PM PDT 24
Finished Apr 21 12:47:42 PM PDT 24
Peak memory 198276 kb
Host smart-21fd629c-d465-4288-b5cc-90403c0bb62a
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2846023611 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 45.gpio_intr_with_filter_rand_intr_event.2846023611
Directory /workspace/45.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/45.gpio_rand_intr_trigger.2116199384
Short name T518
Test name
Test status
Simulation time 242875943 ps
CPU time 2.03 seconds
Started Apr 21 12:47:32 PM PDT 24
Finished Apr 21 12:47:34 PM PDT 24
Peak memory 197220 kb
Host smart-f245169a-1fe4-44f8-9141-ccdce27b1479
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2116199384 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_rand_intr_trigger
.2116199384
Directory /workspace/45.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/45.gpio_random_dout_din.1158836868
Short name T188
Test name
Test status
Simulation time 82363291 ps
CPU time 0.88 seconds
Started Apr 21 12:47:24 PM PDT 24
Finished Apr 21 12:47:25 PM PDT 24
Peak memory 196188 kb
Host smart-c522fb1b-2939-4b04-a763-91a3346302b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1158836868 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_random_dout_din.1158836868
Directory /workspace/45.gpio_random_dout_din/latest

Test location /workspace/coverage/default/45.gpio_random_dout_din_no_pullup_pulldown.1178887010
Short name T658
Test name
Test status
Simulation time 37836437 ps
CPU time 0.84 seconds
Started Apr 21 12:47:27 PM PDT 24
Finished Apr 21 12:47:28 PM PDT 24
Peak memory 196656 kb
Host smart-b5fd005f-98d1-497e-863c-cb3e6d8057ea
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1178887010 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_random_dout_din_no_pullu
p_pulldown.1178887010
Directory /workspace/45.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/45.gpio_random_long_reg_writes_reg_reads.4236404232
Short name T555
Test name
Test status
Simulation time 114657212 ps
CPU time 3.15 seconds
Started Apr 21 12:47:42 PM PDT 24
Finished Apr 21 12:47:46 PM PDT 24
Peak memory 198136 kb
Host smart-9ba9b957-90e9-4827-9455-87418c3e0241
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4236404232 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_ra
ndom_long_reg_writes_reg_reads.4236404232
Directory /workspace/45.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/45.gpio_smoke.62806762
Short name T516
Test name
Test status
Simulation time 118806202 ps
CPU time 0.95 seconds
Started Apr 21 12:47:42 PM PDT 24
Finished Apr 21 12:47:44 PM PDT 24
Peak memory 196456 kb
Host smart-0df03073-fc0e-43d4-947c-6424b49f98a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=62806762 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_smoke.62806762
Directory /workspace/45.gpio_smoke/latest

Test location /workspace/coverage/default/45.gpio_smoke_no_pullup_pulldown.4185789509
Short name T98
Test name
Test status
Simulation time 332625024 ps
CPU time 0.96 seconds
Started Apr 21 12:47:49 PM PDT 24
Finished Apr 21 12:47:51 PM PDT 24
Peak memory 196740 kb
Host smart-ed231bbc-5737-42e2-8065-1b4a37c776b6
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4185789509 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_no_pullup_pulldown.4185789509
Directory /workspace/45.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/45.gpio_stress_all.3674019093
Short name T588
Test name
Test status
Simulation time 4008005096 ps
CPU time 58.57 seconds
Started Apr 21 12:47:38 PM PDT 24
Finished Apr 21 12:48:37 PM PDT 24
Peak memory 198316 kb
Host smart-98b44f12-4282-4548-abd0-f3a8a846c5ac
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3674019093 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.
gpio_stress_all.3674019093
Directory /workspace/45.gpio_stress_all/latest

Test location /workspace/coverage/default/46.gpio_alert_test.1057876505
Short name T567
Test name
Test status
Simulation time 111008303 ps
CPU time 0.57 seconds
Started Apr 21 12:47:50 PM PDT 24
Finished Apr 21 12:47:52 PM PDT 24
Peak memory 194852 kb
Host smart-9b0fb6d6-d672-4333-a302-1ec5645721a2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1057876505 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_alert_test.1057876505
Directory /workspace/46.gpio_alert_test/latest

Test location /workspace/coverage/default/46.gpio_dout_din_regs_random_rw.2020292740
Short name T45
Test name
Test status
Simulation time 87319170 ps
CPU time 0.82 seconds
Started Apr 21 12:47:24 PM PDT 24
Finished Apr 21 12:47:26 PM PDT 24
Peak memory 196528 kb
Host smart-82278a06-1527-40ac-ab2c-02b7e16e490c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2020292740 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_dout_din_regs_random_rw.2020292740
Directory /workspace/46.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/46.gpio_filter_stress.4279069680
Short name T695
Test name
Test status
Simulation time 505790414 ps
CPU time 4.79 seconds
Started Apr 21 12:47:33 PM PDT 24
Finished Apr 21 12:47:38 PM PDT 24
Peak memory 196188 kb
Host smart-47fcdbc0-5a53-4273-a162-fe51af24d91b
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4279069680 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_filter_stre
ss.4279069680
Directory /workspace/46.gpio_filter_stress/latest

Test location /workspace/coverage/default/46.gpio_full_random.3097229476
Short name T572
Test name
Test status
Simulation time 65143969 ps
CPU time 0.98 seconds
Started Apr 21 12:47:44 PM PDT 24
Finished Apr 21 12:47:46 PM PDT 24
Peak memory 196756 kb
Host smart-254f1042-cc01-4ffa-9eea-853594fdc23a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3097229476 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_full_random.3097229476
Directory /workspace/46.gpio_full_random/latest

Test location /workspace/coverage/default/46.gpio_intr_rand_pgm.3303097518
Short name T270
Test name
Test status
Simulation time 118138430 ps
CPU time 0.71 seconds
Started Apr 21 12:47:40 PM PDT 24
Finished Apr 21 12:47:41 PM PDT 24
Peak memory 195584 kb
Host smart-4ef63543-8867-45ce-9c68-19798bfd0796
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3303097518 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_intr_rand_pgm.3303097518
Directory /workspace/46.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/46.gpio_intr_with_filter_rand_intr_event.248505648
Short name T678
Test name
Test status
Simulation time 121663235 ps
CPU time 2.32 seconds
Started Apr 21 12:47:45 PM PDT 24
Finished Apr 21 12:47:48 PM PDT 24
Peak memory 198228 kb
Host smart-4ae62aaa-f690-4215-b2d6-5e578df52f0a
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=248505648 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 46.gpio_intr_with_filter_rand_intr_event.248505648
Directory /workspace/46.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/46.gpio_rand_intr_trigger.2317610847
Short name T83
Test name
Test status
Simulation time 152076745 ps
CPU time 3.18 seconds
Started Apr 21 12:47:43 PM PDT 24
Finished Apr 21 12:47:47 PM PDT 24
Peak memory 198264 kb
Host smart-3c625d6d-667f-4788-aabf-51ff4420b1b6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2317610847 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_rand_intr_trigger
.2317610847
Directory /workspace/46.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/46.gpio_random_dout_din.2915014897
Short name T587
Test name
Test status
Simulation time 43657660 ps
CPU time 0.99 seconds
Started Apr 21 12:47:45 PM PDT 24
Finished Apr 21 12:47:47 PM PDT 24
Peak memory 196928 kb
Host smart-8f39d9bc-48c8-4c6d-997b-db606c0f6ae3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2915014897 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_random_dout_din.2915014897
Directory /workspace/46.gpio_random_dout_din/latest

Test location /workspace/coverage/default/46.gpio_random_dout_din_no_pullup_pulldown.3403758152
Short name T358
Test name
Test status
Simulation time 1414020291 ps
CPU time 1.26 seconds
Started Apr 21 12:47:51 PM PDT 24
Finished Apr 21 12:47:53 PM PDT 24
Peak memory 197116 kb
Host smart-f93342f1-dc23-4728-9219-d6653f43e516
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3403758152 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_random_dout_din_no_pullu
p_pulldown.3403758152
Directory /workspace/46.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/46.gpio_random_long_reg_writes_reg_reads.1380324629
Short name T220
Test name
Test status
Simulation time 93477940 ps
CPU time 4.05 seconds
Started Apr 21 12:47:45 PM PDT 24
Finished Apr 21 12:47:50 PM PDT 24
Peak memory 198200 kb
Host smart-e42b9e9e-b8e2-449d-8a26-26428cc33a4d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1380324629 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_ra
ndom_long_reg_writes_reg_reads.1380324629
Directory /workspace/46.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/46.gpio_smoke.3624980810
Short name T33
Test name
Test status
Simulation time 372379642 ps
CPU time 1.07 seconds
Started Apr 21 12:47:45 PM PDT 24
Finished Apr 21 12:47:47 PM PDT 24
Peak memory 195728 kb
Host smart-cdec69ca-2a65-4c86-93ee-fd2514ea79c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3624980810 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_smoke.3624980810
Directory /workspace/46.gpio_smoke/latest

Test location /workspace/coverage/default/46.gpio_smoke_no_pullup_pulldown.1433942447
Short name T452
Test name
Test status
Simulation time 83499852 ps
CPU time 0.88 seconds
Started Apr 21 12:47:43 PM PDT 24
Finished Apr 21 12:47:44 PM PDT 24
Peak memory 195552 kb
Host smart-4436de92-2529-4cee-b1aa-1a5969966cb6
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1433942447 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_no_pullup_pulldown.1433942447
Directory /workspace/46.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/46.gpio_stress_all.2308890733
Short name T24
Test name
Test status
Simulation time 7418625349 ps
CPU time 54.76 seconds
Started Apr 21 12:47:30 PM PDT 24
Finished Apr 21 12:48:26 PM PDT 24
Peak memory 198392 kb
Host smart-7f727120-a88f-42c6-a829-f20d0d1d700b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2308890733 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.
gpio_stress_all.2308890733
Directory /workspace/46.gpio_stress_all/latest

Test location /workspace/coverage/default/46.gpio_stress_all_with_rand_reset.2216420265
Short name T431
Test name
Test status
Simulation time 179647704461 ps
CPU time 1674.55 seconds
Started Apr 21 12:47:45 PM PDT 24
Finished Apr 21 01:15:41 PM PDT 24
Peak memory 198424 kb
Host smart-95dae20a-6319-4269-a751-a4e8db7424dc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2216420265 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_stress_all_with_rand_reset.2216420265
Directory /workspace/46.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.gpio_alert_test.2941252081
Short name T62
Test name
Test status
Simulation time 49688060 ps
CPU time 0.57 seconds
Started Apr 21 12:47:44 PM PDT 24
Finished Apr 21 12:47:46 PM PDT 24
Peak memory 194972 kb
Host smart-e34acf64-7814-4e33-ba69-7c7097205c27
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2941252081 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_alert_test.2941252081
Directory /workspace/47.gpio_alert_test/latest

Test location /workspace/coverage/default/47.gpio_dout_din_regs_random_rw.1723113451
Short name T247
Test name
Test status
Simulation time 95845149 ps
CPU time 0.83 seconds
Started Apr 21 12:47:41 PM PDT 24
Finished Apr 21 12:47:43 PM PDT 24
Peak memory 195520 kb
Host smart-10b2379d-2d55-4767-9fc1-ec67b7302315
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1723113451 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_dout_din_regs_random_rw.1723113451
Directory /workspace/47.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/47.gpio_filter_stress.3094979015
Short name T395
Test name
Test status
Simulation time 5854139066 ps
CPU time 29.43 seconds
Started Apr 21 12:47:53 PM PDT 24
Finished Apr 21 12:48:23 PM PDT 24
Peak memory 196804 kb
Host smart-bff1975a-06d8-43b5-9d01-a99780ed76a5
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3094979015 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_filter_stre
ss.3094979015
Directory /workspace/47.gpio_filter_stress/latest

Test location /workspace/coverage/default/47.gpio_full_random.1664556346
Short name T705
Test name
Test status
Simulation time 378109894 ps
CPU time 1.03 seconds
Started Apr 21 12:47:39 PM PDT 24
Finished Apr 21 12:47:40 PM PDT 24
Peak memory 196860 kb
Host smart-e5d50500-72c0-4837-9608-91fd095f29ba
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1664556346 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_full_random.1664556346
Directory /workspace/47.gpio_full_random/latest

Test location /workspace/coverage/default/47.gpio_intr_rand_pgm.3486102238
Short name T365
Test name
Test status
Simulation time 78539542 ps
CPU time 0.75 seconds
Started Apr 21 12:47:36 PM PDT 24
Finished Apr 21 12:47:38 PM PDT 24
Peak memory 196360 kb
Host smart-4b93a23d-adc1-4d8b-a5a5-e8bbb60cf58f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3486102238 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_intr_rand_pgm.3486102238
Directory /workspace/47.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/47.gpio_intr_with_filter_rand_intr_event.1451398142
Short name T355
Test name
Test status
Simulation time 63853619 ps
CPU time 2.47 seconds
Started Apr 21 12:47:40 PM PDT 24
Finished Apr 21 12:47:43 PM PDT 24
Peak memory 198176 kb
Host smart-30150e04-f011-40c4-9e36-a10033821562
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1451398142 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 47.gpio_intr_with_filter_rand_intr_event.1451398142
Directory /workspace/47.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/47.gpio_rand_intr_trigger.1145354544
Short name T301
Test name
Test status
Simulation time 91373336 ps
CPU time 0.87 seconds
Started Apr 21 12:47:40 PM PDT 24
Finished Apr 21 12:47:42 PM PDT 24
Peak memory 194692 kb
Host smart-2abf219b-cc8c-4eef-9046-f7e8e119da84
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1145354544 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_rand_intr_trigger
.1145354544
Directory /workspace/47.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/47.gpio_random_dout_din.4251928640
Short name T461
Test name
Test status
Simulation time 17908273 ps
CPU time 0.72 seconds
Started Apr 21 12:47:43 PM PDT 24
Finished Apr 21 12:47:44 PM PDT 24
Peak memory 195660 kb
Host smart-9a3d267e-c35d-4687-b17f-a43c56e1f646
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4251928640 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_random_dout_din.4251928640
Directory /workspace/47.gpio_random_dout_din/latest

Test location /workspace/coverage/default/47.gpio_random_dout_din_no_pullup_pulldown.2346001657
Short name T141
Test name
Test status
Simulation time 26595934 ps
CPU time 0.96 seconds
Started Apr 21 12:47:44 PM PDT 24
Finished Apr 21 12:47:46 PM PDT 24
Peak memory 196052 kb
Host smart-a85ddc0e-2f88-45a5-ad6a-3945fc8d4c87
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2346001657 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_random_dout_din_no_pullu
p_pulldown.2346001657
Directory /workspace/47.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/47.gpio_random_long_reg_writes_reg_reads.143544956
Short name T586
Test name
Test status
Simulation time 920947795 ps
CPU time 3.36 seconds
Started Apr 21 12:47:44 PM PDT 24
Finished Apr 21 12:47:48 PM PDT 24
Peak memory 198196 kb
Host smart-d7194a96-0abf-4063-b6db-25ed7300fa6c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=143544956 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_ran
dom_long_reg_writes_reg_reads.143544956
Directory /workspace/47.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/47.gpio_smoke.789109226
Short name T16
Test name
Test status
Simulation time 78101514 ps
CPU time 1.41 seconds
Started Apr 21 12:47:44 PM PDT 24
Finished Apr 21 12:47:47 PM PDT 24
Peak memory 198128 kb
Host smart-32106f4c-975a-47d0-8214-f1b0c3935a20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=789109226 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_smoke.789109226
Directory /workspace/47.gpio_smoke/latest

Test location /workspace/coverage/default/47.gpio_smoke_no_pullup_pulldown.2557348049
Short name T370
Test name
Test status
Simulation time 139806000 ps
CPU time 1.35 seconds
Started Apr 21 12:47:40 PM PDT 24
Finished Apr 21 12:47:42 PM PDT 24
Peak memory 198192 kb
Host smart-e0409acd-422e-4edc-889c-08cc776cf74a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2557348049 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_no_pullup_pulldown.2557348049
Directory /workspace/47.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/47.gpio_stress_all.3970561418
Short name T474
Test name
Test status
Simulation time 27764175777 ps
CPU time 204.24 seconds
Started Apr 21 12:47:45 PM PDT 24
Finished Apr 21 12:51:10 PM PDT 24
Peak memory 198300 kb
Host smart-c29af1ae-92c4-43e1-9eae-c20f2cae9ea0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3970561418 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.
gpio_stress_all.3970561418
Directory /workspace/47.gpio_stress_all/latest

Test location /workspace/coverage/default/47.gpio_stress_all_with_rand_reset.3636426130
Short name T544
Test name
Test status
Simulation time 20417069004 ps
CPU time 585.46 seconds
Started Apr 21 12:47:43 PM PDT 24
Finished Apr 21 12:57:30 PM PDT 24
Peak memory 198256 kb
Host smart-769b2f5a-208c-4733-9048-6fa15c101c44
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3636426130 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_stress_all_with_rand_reset.3636426130
Directory /workspace/47.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.gpio_alert_test.3778686154
Short name T700
Test name
Test status
Simulation time 12247150 ps
CPU time 0.58 seconds
Started Apr 21 12:47:45 PM PDT 24
Finished Apr 21 12:47:47 PM PDT 24
Peak memory 192876 kb
Host smart-1fae9841-1e4c-4178-a914-fa9615920c66
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3778686154 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_alert_test.3778686154
Directory /workspace/48.gpio_alert_test/latest

Test location /workspace/coverage/default/48.gpio_dout_din_regs_random_rw.3562602131
Short name T115
Test name
Test status
Simulation time 40272217 ps
CPU time 0.67 seconds
Started Apr 21 12:47:50 PM PDT 24
Finished Apr 21 12:47:51 PM PDT 24
Peak memory 194268 kb
Host smart-19f6c1f5-0c95-4bf6-8cf2-cf683f6e1d70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3562602131 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_dout_din_regs_random_rw.3562602131
Directory /workspace/48.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/48.gpio_filter_stress.1562558376
Short name T617
Test name
Test status
Simulation time 766436394 ps
CPU time 5.34 seconds
Started Apr 21 12:47:40 PM PDT 24
Finished Apr 21 12:47:46 PM PDT 24
Peak memory 195700 kb
Host smart-7c9a0e3e-f885-4d57-887c-f101d2366ea7
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1562558376 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_filter_stre
ss.1562558376
Directory /workspace/48.gpio_filter_stress/latest

Test location /workspace/coverage/default/48.gpio_full_random.914378852
Short name T1
Test name
Test status
Simulation time 283741712 ps
CPU time 1.05 seconds
Started Apr 21 12:47:42 PM PDT 24
Finished Apr 21 12:47:48 PM PDT 24
Peak memory 198108 kb
Host smart-5e4d1288-a636-4b3c-be12-7c54cdd8b1cc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=914378852 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_full_random.914378852
Directory /workspace/48.gpio_full_random/latest

Test location /workspace/coverage/default/48.gpio_intr_rand_pgm.1247860343
Short name T182
Test name
Test status
Simulation time 394490116 ps
CPU time 1.49 seconds
Started Apr 21 12:47:36 PM PDT 24
Finished Apr 21 12:47:38 PM PDT 24
Peak memory 198264 kb
Host smart-bd3c28b4-81d1-4d16-bded-c6a8919cb664
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1247860343 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_intr_rand_pgm.1247860343
Directory /workspace/48.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/48.gpio_intr_with_filter_rand_intr_event.2295190856
Short name T26
Test name
Test status
Simulation time 46095563 ps
CPU time 1.82 seconds
Started Apr 21 12:47:44 PM PDT 24
Finished Apr 21 12:47:47 PM PDT 24
Peak memory 197448 kb
Host smart-5de99dbe-9b77-4b5a-be66-c3066754cbc9
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2295190856 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 48.gpio_intr_with_filter_rand_intr_event.2295190856
Directory /workspace/48.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/48.gpio_rand_intr_trigger.3335634500
Short name T154
Test name
Test status
Simulation time 59054872 ps
CPU time 1.51 seconds
Started Apr 21 12:47:40 PM PDT 24
Finished Apr 21 12:47:42 PM PDT 24
Peak memory 195992 kb
Host smart-d26eba12-4302-4ac1-92a8-9cf3c80559a0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3335634500 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_rand_intr_trigger
.3335634500
Directory /workspace/48.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/48.gpio_random_dout_din.2136841146
Short name T447
Test name
Test status
Simulation time 108558564 ps
CPU time 1.18 seconds
Started Apr 21 12:47:41 PM PDT 24
Finished Apr 21 12:47:42 PM PDT 24
Peak memory 198236 kb
Host smart-c8192be7-d4f9-4526-86ab-8a24e4fbb22e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2136841146 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_random_dout_din.2136841146
Directory /workspace/48.gpio_random_dout_din/latest

Test location /workspace/coverage/default/48.gpio_random_dout_din_no_pullup_pulldown.1003834260
Short name T554
Test name
Test status
Simulation time 174233014 ps
CPU time 1.09 seconds
Started Apr 21 12:47:45 PM PDT 24
Finished Apr 21 12:47:47 PM PDT 24
Peak memory 196172 kb
Host smart-723da157-0e10-431e-a6be-c4f85d8d6f26
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1003834260 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_random_dout_din_no_pullu
p_pulldown.1003834260
Directory /workspace/48.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/48.gpio_random_long_reg_writes_reg_reads.2901567772
Short name T228
Test name
Test status
Simulation time 476909384 ps
CPU time 4 seconds
Started Apr 21 12:47:44 PM PDT 24
Finished Apr 21 12:47:50 PM PDT 24
Peak memory 198168 kb
Host smart-c0629164-311b-486d-92c6-82d72f919d73
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2901567772 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_ra
ndom_long_reg_writes_reg_reads.2901567772
Directory /workspace/48.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/48.gpio_smoke.1153889043
Short name T687
Test name
Test status
Simulation time 129033473 ps
CPU time 0.82 seconds
Started Apr 21 12:47:34 PM PDT 24
Finished Apr 21 12:47:41 PM PDT 24
Peak memory 195384 kb
Host smart-17c23659-195f-48d2-bcee-797b67732549
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1153889043 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_smoke.1153889043
Directory /workspace/48.gpio_smoke/latest

Test location /workspace/coverage/default/48.gpio_smoke_no_pullup_pulldown.601034558
Short name T467
Test name
Test status
Simulation time 51649146 ps
CPU time 1.04 seconds
Started Apr 21 12:47:36 PM PDT 24
Finished Apr 21 12:47:38 PM PDT 24
Peak memory 195928 kb
Host smart-dcdeb9d8-de26-4884-84cd-c265ee014e56
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=601034558 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_no_pullup_pulldown.601034558
Directory /workspace/48.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/48.gpio_stress_all.3266060314
Short name T327
Test name
Test status
Simulation time 44179194743 ps
CPU time 144.24 seconds
Started Apr 21 12:47:37 PM PDT 24
Finished Apr 21 12:50:02 PM PDT 24
Peak memory 198284 kb
Host smart-7feabe6c-eff8-415d-b05e-17d11d79d327
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3266060314 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.
gpio_stress_all.3266060314
Directory /workspace/48.gpio_stress_all/latest

Test location /workspace/coverage/default/49.gpio_alert_test.3883273753
Short name T157
Test name
Test status
Simulation time 21325912 ps
CPU time 0.54 seconds
Started Apr 21 12:47:31 PM PDT 24
Finished Apr 21 12:47:33 PM PDT 24
Peak memory 194788 kb
Host smart-80828540-9c63-4cf2-a032-a9014eef8603
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3883273753 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_alert_test.3883273753
Directory /workspace/49.gpio_alert_test/latest

Test location /workspace/coverage/default/49.gpio_dout_din_regs_random_rw.1021619179
Short name T613
Test name
Test status
Simulation time 164183106 ps
CPU time 0.79 seconds
Started Apr 21 12:47:46 PM PDT 24
Finished Apr 21 12:47:47 PM PDT 24
Peak memory 196100 kb
Host smart-87b140ca-3f47-4f4f-bdcc-86a7399fc8ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1021619179 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_dout_din_regs_random_rw.1021619179
Directory /workspace/49.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/49.gpio_filter_stress.1108660981
Short name T439
Test name
Test status
Simulation time 437488242 ps
CPU time 13.17 seconds
Started Apr 21 12:47:41 PM PDT 24
Finished Apr 21 12:47:55 PM PDT 24
Peak memory 198268 kb
Host smart-1a0948e6-02e3-4fd5-aae4-69b3f0f8addc
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1108660981 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_filter_stre
ss.1108660981
Directory /workspace/49.gpio_filter_stress/latest

Test location /workspace/coverage/default/49.gpio_full_random.45980489
Short name T41
Test name
Test status
Simulation time 60463612 ps
CPU time 0.87 seconds
Started Apr 21 12:47:36 PM PDT 24
Finished Apr 21 12:47:38 PM PDT 24
Peak memory 197328 kb
Host smart-aa62d351-bfd1-4310-a4aa-6600d1b19e26
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45980489 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_full_random.45980489
Directory /workspace/49.gpio_full_random/latest

Test location /workspace/coverage/default/49.gpio_intr_rand_pgm.950810347
Short name T460
Test name
Test status
Simulation time 54221063 ps
CPU time 1.02 seconds
Started Apr 21 12:47:38 PM PDT 24
Finished Apr 21 12:47:40 PM PDT 24
Peak memory 196124 kb
Host smart-e529b32b-ea6d-4e43-9264-f1748301fef2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=950810347 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_intr_rand_pgm.950810347
Directory /workspace/49.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/49.gpio_intr_with_filter_rand_intr_event.1199841527
Short name T598
Test name
Test status
Simulation time 133694689 ps
CPU time 2.42 seconds
Started Apr 21 12:47:46 PM PDT 24
Finished Apr 21 12:47:49 PM PDT 24
Peak memory 198360 kb
Host smart-8e499246-32a1-4831-a394-58929a76fa32
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1199841527 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 49.gpio_intr_with_filter_rand_intr_event.1199841527
Directory /workspace/49.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/49.gpio_rand_intr_trigger.733715525
Short name T281
Test name
Test status
Simulation time 126483087 ps
CPU time 2.95 seconds
Started Apr 21 12:47:40 PM PDT 24
Finished Apr 21 12:47:43 PM PDT 24
Peak memory 197292 kb
Host smart-7217e56e-83ce-492d-b3c0-efa9829e2ecc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=733715525 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_rand_intr_trigger.
733715525
Directory /workspace/49.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/49.gpio_random_dout_din.3499879197
Short name T482
Test name
Test status
Simulation time 114007852 ps
CPU time 0.92 seconds
Started Apr 21 12:47:46 PM PDT 24
Finished Apr 21 12:47:48 PM PDT 24
Peak memory 196116 kb
Host smart-70a9a4d2-2a11-4c63-914c-ee5a1b841b73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3499879197 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_random_dout_din.3499879197
Directory /workspace/49.gpio_random_dout_din/latest

Test location /workspace/coverage/default/49.gpio_random_dout_din_no_pullup_pulldown.3181663179
Short name T397
Test name
Test status
Simulation time 24079946 ps
CPU time 1.04 seconds
Started Apr 21 12:47:46 PM PDT 24
Finished Apr 21 12:47:48 PM PDT 24
Peak memory 196032 kb
Host smart-bf69da36-eb74-4325-b2b1-0f9d84135911
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3181663179 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_random_dout_din_no_pullu
p_pulldown.3181663179
Directory /workspace/49.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/49.gpio_random_long_reg_writes_reg_reads.3339074675
Short name T638
Test name
Test status
Simulation time 157452519 ps
CPU time 1.05 seconds
Started Apr 21 12:47:50 PM PDT 24
Finished Apr 21 12:47:57 PM PDT 24
Peak memory 196816 kb
Host smart-096608fd-a1b3-417d-8be2-58728a7ae0a3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3339074675 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_ra
ndom_long_reg_writes_reg_reads.3339074675
Directory /workspace/49.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/49.gpio_smoke.2444410481
Short name T623
Test name
Test status
Simulation time 267609537 ps
CPU time 1.19 seconds
Started Apr 21 12:47:42 PM PDT 24
Finished Apr 21 12:47:44 PM PDT 24
Peak memory 196016 kb
Host smart-0fe9d215-abc6-494c-856f-04603b7e3dad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2444410481 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_smoke.2444410481
Directory /workspace/49.gpio_smoke/latest

Test location /workspace/coverage/default/49.gpio_smoke_no_pullup_pulldown.1945967212
Short name T27
Test name
Test status
Simulation time 136636098 ps
CPU time 1.15 seconds
Started Apr 21 12:47:54 PM PDT 24
Finished Apr 21 12:47:56 PM PDT 24
Peak memory 196440 kb
Host smart-915a5eda-ec08-430c-8769-e9c70177741b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1945967212 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_no_pullup_pulldown.1945967212
Directory /workspace/49.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/49.gpio_stress_all.3550465679
Short name T173
Test name
Test status
Simulation time 7574095027 ps
CPU time 150.24 seconds
Started Apr 21 12:47:47 PM PDT 24
Finished Apr 21 12:50:18 PM PDT 24
Peak memory 198268 kb
Host smart-efeb45f6-f9b7-4bd5-a9dc-584c0ba19891
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3550465679 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.
gpio_stress_all.3550465679
Directory /workspace/49.gpio_stress_all/latest

Test location /workspace/coverage/default/49.gpio_stress_all_with_rand_reset.1817052689
Short name T635
Test name
Test status
Simulation time 68124182736 ps
CPU time 78.25 seconds
Started Apr 21 12:47:50 PM PDT 24
Finished Apr 21 12:49:09 PM PDT 24
Peak memory 198300 kb
Host smart-fe3f81c1-a849-409f-a7d5-b545392b7c6e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1817052689 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_stress_all_with_rand_reset.1817052689
Directory /workspace/49.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.gpio_alert_test.1246373313
Short name T363
Test name
Test status
Simulation time 18020830 ps
CPU time 0.61 seconds
Started Apr 21 12:46:02 PM PDT 24
Finished Apr 21 12:46:04 PM PDT 24
Peak memory 194188 kb
Host smart-abea61d4-c96e-46a7-9772-ad5416ce4e8d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1246373313 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_alert_test.1246373313
Directory /workspace/5.gpio_alert_test/latest

Test location /workspace/coverage/default/5.gpio_dout_din_regs_random_rw.350759734
Short name T207
Test name
Test status
Simulation time 106581596 ps
CPU time 0.84 seconds
Started Apr 21 12:45:54 PM PDT 24
Finished Apr 21 12:45:56 PM PDT 24
Peak memory 197448 kb
Host smart-3bdb401c-7c9f-40eb-95b5-850e9e00123e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=350759734 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_dout_din_regs_random_rw.350759734
Directory /workspace/5.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/5.gpio_filter_stress.678590386
Short name T566
Test name
Test status
Simulation time 3603328886 ps
CPU time 24.64 seconds
Started Apr 21 12:46:06 PM PDT 24
Finished Apr 21 12:46:31 PM PDT 24
Peak memory 197664 kb
Host smart-8e25e6ae-f9f6-4222-bf0b-22bb157c494d
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=678590386 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_filter_stress
.678590386
Directory /workspace/5.gpio_filter_stress/latest

Test location /workspace/coverage/default/5.gpio_full_random.2028541409
Short name T714
Test name
Test status
Simulation time 240848808 ps
CPU time 0.79 seconds
Started Apr 21 12:46:05 PM PDT 24
Finished Apr 21 12:46:07 PM PDT 24
Peak memory 196648 kb
Host smart-a4ed5470-b418-436e-8c17-d8ad084c8be3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2028541409 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_full_random.2028541409
Directory /workspace/5.gpio_full_random/latest

Test location /workspace/coverage/default/5.gpio_intr_rand_pgm.2718750273
Short name T300
Test name
Test status
Simulation time 35707730 ps
CPU time 0.71 seconds
Started Apr 21 12:46:06 PM PDT 24
Finished Apr 21 12:46:08 PM PDT 24
Peak memory 196244 kb
Host smart-29537b6d-99ad-49eb-a2b1-e394f83902fa
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2718750273 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_intr_rand_pgm.2718750273
Directory /workspace/5.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/5.gpio_intr_with_filter_rand_intr_event.459032658
Short name T171
Test name
Test status
Simulation time 41991141 ps
CPU time 1.82 seconds
Started Apr 21 12:45:56 PM PDT 24
Finished Apr 21 12:45:58 PM PDT 24
Peak memory 198268 kb
Host smart-ba0d2ef6-cb95-464f-9fd8-bea17b8981b6
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=459032658 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 5.gpio_intr_with_filter_rand_intr_event.459032658
Directory /workspace/5.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/5.gpio_rand_intr_trigger.2559597488
Short name T536
Test name
Test status
Simulation time 105096954 ps
CPU time 2.16 seconds
Started Apr 21 12:46:03 PM PDT 24
Finished Apr 21 12:46:06 PM PDT 24
Peak memory 196496 kb
Host smart-c6c8e8a1-23ba-4044-a09b-7bc9ef480391
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2559597488 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_rand_intr_trigger.
2559597488
Directory /workspace/5.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/5.gpio_random_dout_din.2071746059
Short name T92
Test name
Test status
Simulation time 76093894 ps
CPU time 1.39 seconds
Started Apr 21 12:46:01 PM PDT 24
Finished Apr 21 12:46:03 PM PDT 24
Peak memory 197164 kb
Host smart-df40b0bf-39d4-4c22-bebf-588bcd1d15cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2071746059 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_random_dout_din.2071746059
Directory /workspace/5.gpio_random_dout_din/latest

Test location /workspace/coverage/default/5.gpio_random_dout_din_no_pullup_pulldown.3069772719
Short name T382
Test name
Test status
Simulation time 27014773 ps
CPU time 0.72 seconds
Started Apr 21 12:46:05 PM PDT 24
Finished Apr 21 12:46:07 PM PDT 24
Peak memory 196152 kb
Host smart-55e7ae89-c0ce-4265-a657-e205cd1712e4
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3069772719 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_random_dout_din_no_pullup
_pulldown.3069772719
Directory /workspace/5.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/5.gpio_smoke.2322573343
Short name T239
Test name
Test status
Simulation time 53572358 ps
CPU time 1.02 seconds
Started Apr 21 12:45:57 PM PDT 24
Finished Apr 21 12:46:00 PM PDT 24
Peak memory 196476 kb
Host smart-d0ea74db-5518-4318-9f93-2438317035b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2322573343 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_smoke.2322573343
Directory /workspace/5.gpio_smoke/latest

Test location /workspace/coverage/default/5.gpio_smoke_no_pullup_pulldown.199001451
Short name T38
Test name
Test status
Simulation time 140194366 ps
CPU time 1.51 seconds
Started Apr 21 12:46:05 PM PDT 24
Finished Apr 21 12:46:08 PM PDT 24
Peak memory 196936 kb
Host smart-6a004322-6b8b-43d7-adf3-09b38c8338bf
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=199001451 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_no_pullup_pulldown.199001451
Directory /workspace/5.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/5.gpio_stress_all.465498839
Short name T515
Test name
Test status
Simulation time 73492258417 ps
CPU time 198.19 seconds
Started Apr 21 12:46:08 PM PDT 24
Finished Apr 21 12:49:27 PM PDT 24
Peak memory 198280 kb
Host smart-6378224f-57b9-4b4d-83d2-6afef092b1e1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=465498839 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gp
io_stress_all.465498839
Directory /workspace/5.gpio_stress_all/latest

Test location /workspace/coverage/default/6.gpio_alert_test.2250781510
Short name T293
Test name
Test status
Simulation time 63941468 ps
CPU time 0.58 seconds
Started Apr 21 12:46:04 PM PDT 24
Finished Apr 21 12:46:07 PM PDT 24
Peak memory 195076 kb
Host smart-bebb866e-b0bf-43f2-93ad-675ac749674b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2250781510 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_alert_test.2250781510
Directory /workspace/6.gpio_alert_test/latest

Test location /workspace/coverage/default/6.gpio_dout_din_regs_random_rw.530620776
Short name T421
Test name
Test status
Simulation time 38277175 ps
CPU time 0.88 seconds
Started Apr 21 12:46:03 PM PDT 24
Finished Apr 21 12:46:06 PM PDT 24
Peak memory 196712 kb
Host smart-28ed4545-c273-4cf1-99be-9d0ed54aee77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=530620776 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_dout_din_regs_random_rw.530620776
Directory /workspace/6.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/6.gpio_filter_stress.2713466160
Short name T392
Test name
Test status
Simulation time 1266510091 ps
CPU time 23.33 seconds
Started Apr 21 12:46:04 PM PDT 24
Finished Apr 21 12:46:29 PM PDT 24
Peak memory 197072 kb
Host smart-f0f697a6-7b7e-4493-a017-2352fed99b38
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2713466160 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_filter_stres
s.2713466160
Directory /workspace/6.gpio_filter_stress/latest

Test location /workspace/coverage/default/6.gpio_full_random.1193833152
Short name T287
Test name
Test status
Simulation time 58087337 ps
CPU time 0.6 seconds
Started Apr 21 12:46:11 PM PDT 24
Finished Apr 21 12:46:12 PM PDT 24
Peak memory 195208 kb
Host smart-627f8370-a891-43ef-acc7-d7264269ba3b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1193833152 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_full_random.1193833152
Directory /workspace/6.gpio_full_random/latest

Test location /workspace/coverage/default/6.gpio_intr_rand_pgm.3359139135
Short name T186
Test name
Test status
Simulation time 164431917 ps
CPU time 0.9 seconds
Started Apr 21 12:46:04 PM PDT 24
Finished Apr 21 12:46:06 PM PDT 24
Peak memory 197068 kb
Host smart-79206432-7dab-441d-b3de-2f3fad1b151b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3359139135 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_intr_rand_pgm.3359139135
Directory /workspace/6.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/6.gpio_intr_with_filter_rand_intr_event.3287642264
Short name T153
Test name
Test status
Simulation time 29848702 ps
CPU time 1.39 seconds
Started Apr 21 12:46:07 PM PDT 24
Finished Apr 21 12:46:09 PM PDT 24
Peak memory 196868 kb
Host smart-ab6d572f-fd89-476f-bf23-3f7d57121ac5
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3287642264 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 6.gpio_intr_with_filter_rand_intr_event.3287642264
Directory /workspace/6.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/6.gpio_rand_intr_trigger.2058376710
Short name T229
Test name
Test status
Simulation time 292859451 ps
CPU time 1.73 seconds
Started Apr 21 12:46:03 PM PDT 24
Finished Apr 21 12:46:07 PM PDT 24
Peak memory 196844 kb
Host smart-3f6feb1c-e228-4ff0-82ca-858e3d2c820d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2058376710 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_rand_intr_trigger.
2058376710
Directory /workspace/6.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/6.gpio_random_dout_din.3557183552
Short name T144
Test name
Test status
Simulation time 113807985 ps
CPU time 1.19 seconds
Started Apr 21 12:46:03 PM PDT 24
Finished Apr 21 12:46:07 PM PDT 24
Peak memory 197180 kb
Host smart-618d7d4c-8e5d-41d1-9454-59fd5110a249
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3557183552 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_random_dout_din.3557183552
Directory /workspace/6.gpio_random_dout_din/latest

Test location /workspace/coverage/default/6.gpio_random_dout_din_no_pullup_pulldown.585065648
Short name T142
Test name
Test status
Simulation time 56229606 ps
CPU time 1.24 seconds
Started Apr 21 12:46:03 PM PDT 24
Finished Apr 21 12:46:07 PM PDT 24
Peak memory 197340 kb
Host smart-214757cb-dfb6-4859-a3fd-7b44ebbf6b5e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=585065648 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_random_dout_din_no_pullup_
pulldown.585065648
Directory /workspace/6.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/6.gpio_random_long_reg_writes_reg_reads.1246326095
Short name T626
Test name
Test status
Simulation time 265558845 ps
CPU time 3.17 seconds
Started Apr 21 12:46:06 PM PDT 24
Finished Apr 21 12:46:10 PM PDT 24
Peak memory 198168 kb
Host smart-8f4563b5-b3cb-4cb0-891d-96d9e0aaac46
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1246326095 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_ran
dom_long_reg_writes_reg_reads.1246326095
Directory /workspace/6.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/6.gpio_smoke.2674965131
Short name T273
Test name
Test status
Simulation time 59746549 ps
CPU time 1.01 seconds
Started Apr 21 12:46:05 PM PDT 24
Finished Apr 21 12:46:07 PM PDT 24
Peak memory 195588 kb
Host smart-9901af1f-54a5-4a52-a3f1-96ce5662c889
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2674965131 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_smoke.2674965131
Directory /workspace/6.gpio_smoke/latest

Test location /workspace/coverage/default/6.gpio_smoke_no_pullup_pulldown.970979753
Short name T310
Test name
Test status
Simulation time 29630461 ps
CPU time 0.89 seconds
Started Apr 21 12:46:07 PM PDT 24
Finished Apr 21 12:46:09 PM PDT 24
Peak memory 195812 kb
Host smart-a61f5071-64d3-46f5-aa14-7dcb4e189e95
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=970979753 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_no_pullup_pulldown.970979753
Directory /workspace/6.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/6.gpio_stress_all.3858081085
Short name T640
Test name
Test status
Simulation time 6650430966 ps
CPU time 193.11 seconds
Started Apr 21 12:46:17 PM PDT 24
Finished Apr 21 12:49:30 PM PDT 24
Peak memory 198324 kb
Host smart-26e24603-594d-435d-810d-91479b189a42
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3858081085 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.g
pio_stress_all.3858081085
Directory /workspace/6.gpio_stress_all/latest

Test location /workspace/coverage/default/6.gpio_stress_all_with_rand_reset.3480758469
Short name T100
Test name
Test status
Simulation time 102525447728 ps
CPU time 767.77 seconds
Started Apr 21 12:46:07 PM PDT 24
Finished Apr 21 12:58:56 PM PDT 24
Peak memory 198304 kb
Host smart-ced2de6f-7054-4560-b5d5-05668efe0974
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3480758469 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_stress_all_with_rand_reset.3480758469
Directory /workspace/6.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.gpio_alert_test.1886187974
Short name T78
Test name
Test status
Simulation time 125256329 ps
CPU time 0.56 seconds
Started Apr 21 12:46:12 PM PDT 24
Finished Apr 21 12:46:13 PM PDT 24
Peak memory 194084 kb
Host smart-0a7efa81-872b-4a9a-8099-176f6ab9a28c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1886187974 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_alert_test.1886187974
Directory /workspace/7.gpio_alert_test/latest

Test location /workspace/coverage/default/7.gpio_dout_din_regs_random_rw.200712407
Short name T193
Test name
Test status
Simulation time 62829391 ps
CPU time 0.68 seconds
Started Apr 21 12:46:07 PM PDT 24
Finished Apr 21 12:46:08 PM PDT 24
Peak memory 194156 kb
Host smart-0d7795c3-b9a4-487d-b7be-161db1777db5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=200712407 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_dout_din_regs_random_rw.200712407
Directory /workspace/7.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/7.gpio_filter_stress.469358626
Short name T693
Test name
Test status
Simulation time 602491700 ps
CPU time 8.65 seconds
Started Apr 21 12:46:03 PM PDT 24
Finished Apr 21 12:46:13 PM PDT 24
Peak memory 198124 kb
Host smart-83476080-703d-4b25-9a2c-94ed5d9cb94b
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=469358626 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_filter_stress
.469358626
Directory /workspace/7.gpio_filter_stress/latest

Test location /workspace/coverage/default/7.gpio_full_random.630846356
Short name T344
Test name
Test status
Simulation time 81827616 ps
CPU time 1.01 seconds
Started Apr 21 12:46:08 PM PDT 24
Finished Apr 21 12:46:10 PM PDT 24
Peak memory 196728 kb
Host smart-923e44e2-28f1-4480-a68c-b90f06a46d44
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=630846356 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_full_random.630846356
Directory /workspace/7.gpio_full_random/latest

Test location /workspace/coverage/default/7.gpio_intr_rand_pgm.2576203078
Short name T659
Test name
Test status
Simulation time 83326441 ps
CPU time 1.4 seconds
Started Apr 21 12:46:03 PM PDT 24
Finished Apr 21 12:46:05 PM PDT 24
Peak memory 197004 kb
Host smart-9a02824c-d767-45d8-8eef-70da1f06ce4c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2576203078 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_intr_rand_pgm.2576203078
Directory /workspace/7.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/7.gpio_intr_with_filter_rand_intr_event.1846875298
Short name T289
Test name
Test status
Simulation time 218620313 ps
CPU time 2.32 seconds
Started Apr 21 12:46:06 PM PDT 24
Finished Apr 21 12:46:09 PM PDT 24
Peak memory 198208 kb
Host smart-7e0cbaf7-60ee-48b4-9a76-8764f5827c6f
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1846875298 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 7.gpio_intr_with_filter_rand_intr_event.1846875298
Directory /workspace/7.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/7.gpio_rand_intr_trigger.2127727860
Short name T492
Test name
Test status
Simulation time 91472989 ps
CPU time 1.3 seconds
Started Apr 21 12:46:07 PM PDT 24
Finished Apr 21 12:46:09 PM PDT 24
Peak memory 196556 kb
Host smart-8fd31e66-f258-4944-a9da-96d71cf49014
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2127727860 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_rand_intr_trigger.
2127727860
Directory /workspace/7.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/7.gpio_random_dout_din.2637185913
Short name T674
Test name
Test status
Simulation time 63573072 ps
CPU time 1.19 seconds
Started Apr 21 12:46:13 PM PDT 24
Finished Apr 21 12:46:15 PM PDT 24
Peak memory 197068 kb
Host smart-f9a52c9b-d773-48f8-a6a8-12b11d25d4a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2637185913 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_random_dout_din.2637185913
Directory /workspace/7.gpio_random_dout_din/latest

Test location /workspace/coverage/default/7.gpio_random_dout_din_no_pullup_pulldown.3344126937
Short name T143
Test name
Test status
Simulation time 188167434 ps
CPU time 0.83 seconds
Started Apr 21 12:46:08 PM PDT 24
Finished Apr 21 12:46:10 PM PDT 24
Peak memory 195740 kb
Host smart-7591157b-0a6b-41af-a243-fde5f155a92e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3344126937 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_random_dout_din_no_pullup
_pulldown.3344126937
Directory /workspace/7.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/7.gpio_random_long_reg_writes_reg_reads.952870803
Short name T21
Test name
Test status
Simulation time 349315006 ps
CPU time 2.51 seconds
Started Apr 21 12:46:09 PM PDT 24
Finished Apr 21 12:46:12 PM PDT 24
Peak memory 198160 kb
Host smart-b99a9b2c-d5d0-4006-bb90-9f1609d80e8b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=952870803 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_rand
om_long_reg_writes_reg_reads.952870803
Directory /workspace/7.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/7.gpio_smoke.3666059408
Short name T619
Test name
Test status
Simulation time 120130254 ps
CPU time 1.06 seconds
Started Apr 21 12:46:13 PM PDT 24
Finished Apr 21 12:46:14 PM PDT 24
Peak memory 196320 kb
Host smart-2b31dd2a-3b1d-44d6-855f-18615e030f36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3666059408 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_smoke.3666059408
Directory /workspace/7.gpio_smoke/latest

Test location /workspace/coverage/default/7.gpio_smoke_no_pullup_pulldown.2984172619
Short name T591
Test name
Test status
Simulation time 41668687 ps
CPU time 1.18 seconds
Started Apr 21 12:46:06 PM PDT 24
Finished Apr 21 12:46:08 PM PDT 24
Peak memory 195592 kb
Host smart-adac1086-ba61-4678-8124-08c5974013bb
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2984172619 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_no_pullup_pulldown.2984172619
Directory /workspace/7.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/7.gpio_stress_all.602016102
Short name T286
Test name
Test status
Simulation time 786823567 ps
CPU time 18.72 seconds
Started Apr 21 12:46:11 PM PDT 24
Finished Apr 21 12:46:30 PM PDT 24
Peak memory 197948 kb
Host smart-d7e7727d-f718-4b0a-ad7f-525058e79958
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=602016102 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gp
io_stress_all.602016102
Directory /workspace/7.gpio_stress_all/latest

Test location /workspace/coverage/default/8.gpio_alert_test.2934476249
Short name T517
Test name
Test status
Simulation time 12715139 ps
CPU time 0.55 seconds
Started Apr 21 12:46:14 PM PDT 24
Finished Apr 21 12:46:15 PM PDT 24
Peak memory 193964 kb
Host smart-c375cc68-301b-46c6-8601-017ce6c9bd2e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2934476249 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_alert_test.2934476249
Directory /workspace/8.gpio_alert_test/latest

Test location /workspace/coverage/default/8.gpio_dout_din_regs_random_rw.3173870755
Short name T495
Test name
Test status
Simulation time 34472905 ps
CPU time 0.69 seconds
Started Apr 21 12:46:14 PM PDT 24
Finished Apr 21 12:46:15 PM PDT 24
Peak memory 195452 kb
Host smart-c90d87c3-e762-4eea-9a85-2b3443fa42a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3173870755 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_dout_din_regs_random_rw.3173870755
Directory /workspace/8.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/8.gpio_filter_stress.1379986763
Short name T256
Test name
Test status
Simulation time 2113706804 ps
CPU time 14.67 seconds
Started Apr 21 12:46:08 PM PDT 24
Finished Apr 21 12:46:24 PM PDT 24
Peak memory 197180 kb
Host smart-513f22b1-d50b-463f-a888-afd2b6b69054
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1379986763 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_filter_stres
s.1379986763
Directory /workspace/8.gpio_filter_stress/latest

Test location /workspace/coverage/default/8.gpio_full_random.1138604118
Short name T543
Test name
Test status
Simulation time 84097804 ps
CPU time 0.75 seconds
Started Apr 21 12:46:12 PM PDT 24
Finished Apr 21 12:46:13 PM PDT 24
Peak memory 196184 kb
Host smart-b3dd7d55-9878-45fa-bc8e-eb6cf8e15d63
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1138604118 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_full_random.1138604118
Directory /workspace/8.gpio_full_random/latest

Test location /workspace/coverage/default/8.gpio_intr_rand_pgm.522777892
Short name T530
Test name
Test status
Simulation time 64305634 ps
CPU time 1.02 seconds
Started Apr 21 12:46:07 PM PDT 24
Finished Apr 21 12:46:09 PM PDT 24
Peak memory 197044 kb
Host smart-122abe29-721c-4788-9286-aaf7a2dd45f1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=522777892 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_intr_rand_pgm.522777892
Directory /workspace/8.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/8.gpio_intr_with_filter_rand_intr_event.710459213
Short name T288
Test name
Test status
Simulation time 71505959 ps
CPU time 1.53 seconds
Started Apr 21 12:46:07 PM PDT 24
Finished Apr 21 12:46:09 PM PDT 24
Peak memory 196924 kb
Host smart-6b52daae-2371-4138-8550-357230193425
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=710459213 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 8.gpio_intr_with_filter_rand_intr_event.710459213
Directory /workspace/8.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/8.gpio_rand_intr_trigger.1217106777
Short name T309
Test name
Test status
Simulation time 81920186 ps
CPU time 1.75 seconds
Started Apr 21 12:46:15 PM PDT 24
Finished Apr 21 12:46:17 PM PDT 24
Peak memory 196216 kb
Host smart-110a1c24-a5fc-4ec3-9dee-9f52ee75f62b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1217106777 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_rand_intr_trigger.
1217106777
Directory /workspace/8.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/8.gpio_random_dout_din.3401846061
Short name T244
Test name
Test status
Simulation time 216819590 ps
CPU time 0.99 seconds
Started Apr 21 12:46:16 PM PDT 24
Finished Apr 21 12:46:18 PM PDT 24
Peak memory 196088 kb
Host smart-b5099bc9-1098-4855-be7b-b91c1874a2b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3401846061 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_random_dout_din.3401846061
Directory /workspace/8.gpio_random_dout_din/latest

Test location /workspace/coverage/default/8.gpio_random_dout_din_no_pullup_pulldown.991914736
Short name T381
Test name
Test status
Simulation time 55208678 ps
CPU time 1.13 seconds
Started Apr 21 12:46:08 PM PDT 24
Finished Apr 21 12:46:10 PM PDT 24
Peak memory 196884 kb
Host smart-35dd74c2-8e3e-4ec8-9bf2-e5b70b14ee84
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=991914736 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_random_dout_din_no_pullup_
pulldown.991914736
Directory /workspace/8.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/8.gpio_random_long_reg_writes_reg_reads.1050405702
Short name T328
Test name
Test status
Simulation time 129315568 ps
CPU time 2.92 seconds
Started Apr 21 12:46:09 PM PDT 24
Finished Apr 21 12:46:13 PM PDT 24
Peak memory 198080 kb
Host smart-5c69ca03-8f4f-4064-aca1-3cbc3cabced8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1050405702 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_ran
dom_long_reg_writes_reg_reads.1050405702
Directory /workspace/8.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/8.gpio_smoke.1413280251
Short name T454
Test name
Test status
Simulation time 33001366 ps
CPU time 1.09 seconds
Started Apr 21 12:46:11 PM PDT 24
Finished Apr 21 12:46:13 PM PDT 24
Peak memory 195896 kb
Host smart-122d0306-c45f-442e-ad7d-822dd888bdaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1413280251 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_smoke.1413280251
Directory /workspace/8.gpio_smoke/latest

Test location /workspace/coverage/default/8.gpio_smoke_no_pullup_pulldown.3661837720
Short name T652
Test name
Test status
Simulation time 316930623 ps
CPU time 1.32 seconds
Started Apr 21 12:46:14 PM PDT 24
Finished Apr 21 12:46:16 PM PDT 24
Peak memory 198252 kb
Host smart-064ea123-0e7d-469f-8717-c062b813e014
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3661837720 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_no_pullup_pulldown.3661837720
Directory /workspace/8.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/8.gpio_stress_all.3844629180
Short name T633
Test name
Test status
Simulation time 24411721398 ps
CPU time 146.41 seconds
Started Apr 21 12:46:08 PM PDT 24
Finished Apr 21 12:48:35 PM PDT 24
Peak memory 198308 kb
Host smart-7c103419-6a2b-4629-8e0a-1b09b1288478
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3844629180 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.g
pio_stress_all.3844629180
Directory /workspace/8.gpio_stress_all/latest

Test location /workspace/coverage/default/8.gpio_stress_all_with_rand_reset.970435818
Short name T526
Test name
Test status
Simulation time 23383906761 ps
CPU time 627.13 seconds
Started Apr 21 12:46:17 PM PDT 24
Finished Apr 21 12:56:45 PM PDT 24
Peak memory 198352 kb
Host smart-c7d75685-9a7d-4eac-b4a8-5f2e7dd745b0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=970435818 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_stress_all_with_rand_reset.970435818
Directory /workspace/8.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.gpio_alert_test.1326152639
Short name T246
Test name
Test status
Simulation time 23294718 ps
CPU time 0.61 seconds
Started Apr 21 12:46:18 PM PDT 24
Finished Apr 21 12:46:19 PM PDT 24
Peak memory 194076 kb
Host smart-24c23929-6e45-4e7c-8953-66c2ec9bb359
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1326152639 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_alert_test.1326152639
Directory /workspace/9.gpio_alert_test/latest

Test location /workspace/coverage/default/9.gpio_dout_din_regs_random_rw.2476442203
Short name T403
Test name
Test status
Simulation time 51488991 ps
CPU time 0.88 seconds
Started Apr 21 12:46:12 PM PDT 24
Finished Apr 21 12:46:14 PM PDT 24
Peak memory 196796 kb
Host smart-1479ee9f-3ddc-4976-9df8-3f64c64b3083
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2476442203 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_dout_din_regs_random_rw.2476442203
Directory /workspace/9.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/9.gpio_filter_stress.1490370219
Short name T52
Test name
Test status
Simulation time 1887946402 ps
CPU time 25.24 seconds
Started Apr 21 12:46:17 PM PDT 24
Finished Apr 21 12:46:43 PM PDT 24
Peak memory 197180 kb
Host smart-9cbc233d-b6a7-4601-a9c7-7a13c07ebdf2
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1490370219 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_filter_stres
s.1490370219
Directory /workspace/9.gpio_filter_stress/latest

Test location /workspace/coverage/default/9.gpio_full_random.2422112353
Short name T20
Test name
Test status
Simulation time 108371652 ps
CPU time 1.01 seconds
Started Apr 21 12:46:21 PM PDT 24
Finished Apr 21 12:46:22 PM PDT 24
Peak memory 196220 kb
Host smart-a25f8070-31b6-4868-a53d-17488e12b75a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2422112353 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_full_random.2422112353
Directory /workspace/9.gpio_full_random/latest

Test location /workspace/coverage/default/9.gpio_intr_rand_pgm.385232760
Short name T489
Test name
Test status
Simulation time 24783634 ps
CPU time 0.85 seconds
Started Apr 21 12:46:21 PM PDT 24
Finished Apr 21 12:46:23 PM PDT 24
Peak memory 195620 kb
Host smart-3bcc29e4-97cc-448f-a1ec-43c0514a9d7e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=385232760 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_intr_rand_pgm.385232760
Directory /workspace/9.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/9.gpio_intr_with_filter_rand_intr_event.3897387783
Short name T436
Test name
Test status
Simulation time 377146462 ps
CPU time 3.37 seconds
Started Apr 21 12:46:18 PM PDT 24
Finished Apr 21 12:46:22 PM PDT 24
Peak memory 196568 kb
Host smart-dc68dc32-721d-437d-9400-4f4aa66535eb
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3897387783 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 9.gpio_intr_with_filter_rand_intr_event.3897387783
Directory /workspace/9.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/9.gpio_rand_intr_trigger.3686138900
Short name T670
Test name
Test status
Simulation time 287026146 ps
CPU time 2.04 seconds
Started Apr 21 12:46:16 PM PDT 24
Finished Apr 21 12:46:19 PM PDT 24
Peak memory 198300 kb
Host smart-aa23effb-6fd7-44ac-b9a7-5509f7830449
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3686138900 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_rand_intr_trigger.
3686138900
Directory /workspace/9.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/9.gpio_random_dout_din.255272826
Short name T685
Test name
Test status
Simulation time 41131770 ps
CPU time 0.93 seconds
Started Apr 21 12:46:17 PM PDT 24
Finished Apr 21 12:46:18 PM PDT 24
Peak memory 196192 kb
Host smart-a7359769-49d4-487b-9354-3e4425c8a9cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=255272826 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_random_dout_din.255272826
Directory /workspace/9.gpio_random_dout_din/latest

Test location /workspace/coverage/default/9.gpio_random_dout_din_no_pullup_pulldown.3472286425
Short name T32
Test name
Test status
Simulation time 18098533 ps
CPU time 0.69 seconds
Started Apr 21 12:46:17 PM PDT 24
Finished Apr 21 12:46:18 PM PDT 24
Peak memory 194460 kb
Host smart-22ddd5f5-30f1-459d-9d15-2c3807fffb40
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3472286425 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_random_dout_din_no_pullup
_pulldown.3472286425
Directory /workspace/9.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/9.gpio_random_long_reg_writes_reg_reads.613688836
Short name T672
Test name
Test status
Simulation time 1366227382 ps
CPU time 1.44 seconds
Started Apr 21 12:46:22 PM PDT 24
Finished Apr 21 12:46:24 PM PDT 24
Peak memory 198148 kb
Host smart-5764f721-1e5f-4058-ac58-c5a515316fd5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=613688836 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_rand
om_long_reg_writes_reg_reads.613688836
Directory /workspace/9.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/9.gpio_smoke.2125699451
Short name T505
Test name
Test status
Simulation time 157469245 ps
CPU time 1.46 seconds
Started Apr 21 12:46:23 PM PDT 24
Finished Apr 21 12:46:25 PM PDT 24
Peak memory 196940 kb
Host smart-52124169-36e5-403b-addf-60a6225d9733
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2125699451 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_smoke.2125699451
Directory /workspace/9.gpio_smoke/latest

Test location /workspace/coverage/default/9.gpio_smoke_no_pullup_pulldown.2809176728
Short name T512
Test name
Test status
Simulation time 192816096 ps
CPU time 0.95 seconds
Started Apr 21 12:46:13 PM PDT 24
Finished Apr 21 12:46:14 PM PDT 24
Peak memory 196672 kb
Host smart-af17097a-4aa8-4bde-bc70-dbc851c644b6
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2809176728 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_no_pullup_pulldown.2809176728
Directory /workspace/9.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/9.gpio_stress_all.2220344306
Short name T669
Test name
Test status
Simulation time 14222121892 ps
CPU time 174.23 seconds
Started Apr 21 12:46:21 PM PDT 24
Finished Apr 21 12:49:16 PM PDT 24
Peak memory 197856 kb
Host smart-48a2ae36-8bef-43d4-9c41-35e7908fc923
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2220344306 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.g
pio_stress_all.2220344306
Directory /workspace/9.gpio_stress_all/latest

Test location /workspace/coverage/en_cdc_prims/0.gpio_smoke_en_cdc_prim.3965844679
Short name T903
Test name
Test status
Simulation time 37656649 ps
CPU time 0.83 seconds
Started Apr 21 12:22:28 PM PDT 24
Finished Apr 21 12:22:29 PM PDT 24
Peak memory 195864 kb
Host smart-88f59edb-b418-45ff-b2be-e686d4cf1fc3
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3965844679 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_en_cdc_prim.3965844679
Directory /workspace/0.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1400975533
Short name T921
Test name
Test status
Simulation time 177990777 ps
CPU time 1.07 seconds
Started Apr 21 12:22:28 PM PDT 24
Finished Apr 21 12:22:29 PM PDT 24
Peak memory 191784 kb
Host smart-bb6015c1-173e-42aa-a00d-72f353e94932
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1400975533 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.1400975533
Directory /workspace/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/1.gpio_smoke_en_cdc_prim.3232800157
Short name T906
Test name
Test status
Simulation time 62006792 ps
CPU time 1.06 seconds
Started Apr 21 12:20:48 PM PDT 24
Finished Apr 21 12:20:49 PM PDT 24
Peak memory 191428 kb
Host smart-0a1639fe-ac8b-4d2e-a824-9ae35a0e0a1b
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3232800157 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_en_cdc_prim.3232800157
Directory /workspace/1.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1407995030
Short name T920
Test name
Test status
Simulation time 56435716 ps
CPU time 1.06 seconds
Started Apr 21 12:17:45 PM PDT 24
Finished Apr 21 12:17:47 PM PDT 24
Peak memory 189876 kb
Host smart-a9744839-e9cd-4726-8ef9-62a71fe242dc
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1407995030 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.1407995030
Directory /workspace/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/10.gpio_smoke_en_cdc_prim.678808192
Short name T936
Test name
Test status
Simulation time 190827345 ps
CPU time 1.19 seconds
Started Apr 21 12:22:33 PM PDT 24
Finished Apr 21 12:22:35 PM PDT 24
Peak memory 196108 kb
Host smart-739c49e9-d3d9-4589-a700-84a2981c296e
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=678808192 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_en_cdc_prim.678808192
Directory /workspace/10.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3063835810
Short name T933
Test name
Test status
Simulation time 142003335 ps
CPU time 1.23 seconds
Started Apr 21 12:20:30 PM PDT 24
Finished Apr 21 12:20:32 PM PDT 24
Peak memory 189636 kb
Host smart-8e2e3fcb-46f2-4b92-8fe5-323e23479ece
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3063835810 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3063835810
Directory /workspace/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/11.gpio_smoke_en_cdc_prim.527770714
Short name T867
Test name
Test status
Simulation time 37090856 ps
CPU time 0.81 seconds
Started Apr 21 12:21:19 PM PDT 24
Finished Apr 21 12:21:20 PM PDT 24
Peak memory 191304 kb
Host smart-635282c3-54c5-4dd3-86fd-b135bfdbed44
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=527770714 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_en_cdc_prim.527770714
Directory /workspace/11.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2596966437
Short name T886
Test name
Test status
Simulation time 49744273 ps
CPU time 1.38 seconds
Started Apr 21 12:18:30 PM PDT 24
Finished Apr 21 12:18:33 PM PDT 24
Peak memory 191436 kb
Host smart-24d19900-ffc8-4ea8-88f0-2fd1ba1219a1
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2596966437 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2596966437
Directory /workspace/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/12.gpio_smoke_en_cdc_prim.1434978751
Short name T932
Test name
Test status
Simulation time 44750424 ps
CPU time 1.15 seconds
Started Apr 21 12:22:33 PM PDT 24
Finished Apr 21 12:22:35 PM PDT 24
Peak memory 190816 kb
Host smart-64aad329-a688-4d4f-9108-89fa7fd2b9e6
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1434978751 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_en_cdc_prim.1434978751
Directory /workspace/12.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3811899353
Short name T929
Test name
Test status
Simulation time 67642434 ps
CPU time 1.25 seconds
Started Apr 21 12:22:51 PM PDT 24
Finished Apr 21 12:22:53 PM PDT 24
Peak memory 190400 kb
Host smart-1189ae86-4f86-489b-904e-c3e8c0d45b9e
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3811899353 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3811899353
Directory /workspace/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/13.gpio_smoke_en_cdc_prim.1301721143
Short name T918
Test name
Test status
Simulation time 53775130 ps
CPU time 0.89 seconds
Started Apr 21 12:22:54 PM PDT 24
Finished Apr 21 12:22:56 PM PDT 24
Peak memory 190264 kb
Host smart-bc01904e-8a32-49f4-bf10-8db8372a8c54
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1301721143 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_en_cdc_prim.1301721143
Directory /workspace/13.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2849154968
Short name T866
Test name
Test status
Simulation time 56968132 ps
CPU time 1.03 seconds
Started Apr 21 12:20:51 PM PDT 24
Finished Apr 21 12:20:53 PM PDT 24
Peak memory 189712 kb
Host smart-db0c1355-8806-449f-82bc-f2bd70a13b07
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2849154968 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2849154968
Directory /workspace/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/14.gpio_smoke_en_cdc_prim.2417106235
Short name T895
Test name
Test status
Simulation time 294285830 ps
CPU time 1.34 seconds
Started Apr 21 12:18:55 PM PDT 24
Finished Apr 21 12:18:56 PM PDT 24
Peak memory 191420 kb
Host smart-a7166db4-5b18-47d7-b663-2b8950920549
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2417106235 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_en_cdc_prim.2417106235
Directory /workspace/14.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3238471651
Short name T926
Test name
Test status
Simulation time 254144969 ps
CPU time 1.18 seconds
Started Apr 21 12:21:16 PM PDT 24
Finished Apr 21 12:21:18 PM PDT 24
Peak memory 197700 kb
Host smart-72a9c165-71b6-48ce-bd8e-07b5e4e57678
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3238471651 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3238471651
Directory /workspace/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/15.gpio_smoke_en_cdc_prim.2376004001
Short name T857
Test name
Test status
Simulation time 341910518 ps
CPU time 0.87 seconds
Started Apr 21 12:20:52 PM PDT 24
Finished Apr 21 12:20:53 PM PDT 24
Peak memory 191064 kb
Host smart-7af9a86e-efd2-461b-96ee-779287ea87b7
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2376004001 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_en_cdc_prim.2376004001
Directory /workspace/15.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1618295488
Short name T871
Test name
Test status
Simulation time 31654923 ps
CPU time 0.79 seconds
Started Apr 21 12:19:30 PM PDT 24
Finished Apr 21 12:19:31 PM PDT 24
Peak memory 191296 kb
Host smart-bba60588-1ff7-4b44-aea9-50ace80be89f
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1618295488 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1618295488
Directory /workspace/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/16.gpio_smoke_en_cdc_prim.3497108455
Short name T898
Test name
Test status
Simulation time 161873276 ps
CPU time 0.96 seconds
Started Apr 21 12:22:51 PM PDT 24
Finished Apr 21 12:22:53 PM PDT 24
Peak memory 190624 kb
Host smart-3a26478d-4b43-435b-a0e8-6dcecbd0c99b
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3497108455 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_en_cdc_prim.3497108455
Directory /workspace/16.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3146983434
Short name T890
Test name
Test status
Simulation time 166952307 ps
CPU time 1.19 seconds
Started Apr 21 12:17:53 PM PDT 24
Finished Apr 21 12:17:55 PM PDT 24
Peak memory 191332 kb
Host smart-ebd45e44-b368-47a5-86a8-5d257ad32c4a
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3146983434 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3146983434
Directory /workspace/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/17.gpio_smoke_en_cdc_prim.2090466479
Short name T909
Test name
Test status
Simulation time 27938580 ps
CPU time 0.87 seconds
Started Apr 21 12:19:14 PM PDT 24
Finished Apr 21 12:19:15 PM PDT 24
Peak memory 191308 kb
Host smart-a9bb9f93-ed67-4477-8628-7ec5d47b4764
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2090466479 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_en_cdc_prim.2090466479
Directory /workspace/17.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4260099755
Short name T927
Test name
Test status
Simulation time 57137568 ps
CPU time 1.42 seconds
Started Apr 21 12:22:33 PM PDT 24
Finished Apr 21 12:22:35 PM PDT 24
Peak memory 189564 kb
Host smart-01940841-7545-430a-b324-4778c0b8ffcd
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4260099755 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.4260099755
Directory /workspace/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/18.gpio_smoke_en_cdc_prim.2023842732
Short name T940
Test name
Test status
Simulation time 72252826 ps
CPU time 1.29 seconds
Started Apr 21 12:18:40 PM PDT 24
Finished Apr 21 12:18:42 PM PDT 24
Peak memory 191424 kb
Host smart-fb1c5e19-12ec-4879-a903-b04a98ed3f57
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2023842732 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_en_cdc_prim.2023842732
Directory /workspace/18.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1923810534
Short name T852
Test name
Test status
Simulation time 238052393 ps
CPU time 1.08 seconds
Started Apr 21 12:22:34 PM PDT 24
Finished Apr 21 12:22:36 PM PDT 24
Peak memory 195580 kb
Host smart-1d40532a-4833-4a28-bb55-8a14fafde5dc
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1923810534 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1923810534
Directory /workspace/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/19.gpio_smoke_en_cdc_prim.1447126207
Short name T910
Test name
Test status
Simulation time 42402780 ps
CPU time 1.34 seconds
Started Apr 21 12:17:52 PM PDT 24
Finished Apr 21 12:17:54 PM PDT 24
Peak memory 191368 kb
Host smart-84663b28-e900-4eef-9168-4248cf0da9ab
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1447126207 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_en_cdc_prim.1447126207
Directory /workspace/19.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2021673141
Short name T872
Test name
Test status
Simulation time 78921109 ps
CPU time 1.17 seconds
Started Apr 21 12:17:46 PM PDT 24
Finished Apr 21 12:17:48 PM PDT 24
Peak memory 191376 kb
Host smart-100ca990-5f3a-41f2-aff2-07699ebb3871
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2021673141 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2021673141
Directory /workspace/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/2.gpio_smoke_en_cdc_prim.4048992197
Short name T942
Test name
Test status
Simulation time 384134598 ps
CPU time 0.97 seconds
Started Apr 21 12:17:48 PM PDT 24
Finished Apr 21 12:17:49 PM PDT 24
Peak memory 191764 kb
Host smart-b38a2ffb-c764-4520-ada0-da0cfa357641
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4048992197 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_en_cdc_prim.4048992197
Directory /workspace/2.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1623325754
Short name T888
Test name
Test status
Simulation time 54475712 ps
CPU time 1.33 seconds
Started Apr 21 12:17:45 PM PDT 24
Finished Apr 21 12:17:47 PM PDT 24
Peak memory 196172 kb
Host smart-eb94933f-1de5-4241-bd46-7df04f75ea5b
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1623325754 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.1623325754
Directory /workspace/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/20.gpio_smoke_en_cdc_prim.3403355765
Short name T912
Test name
Test status
Simulation time 184804326 ps
CPU time 1.09 seconds
Started Apr 21 12:23:33 PM PDT 24
Finished Apr 21 12:23:34 PM PDT 24
Peak memory 191364 kb
Host smart-937d42e5-5cb6-4898-b389-4e55431ca263
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3403355765 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_en_cdc_prim.3403355765
Directory /workspace/20.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3999680351
Short name T859
Test name
Test status
Simulation time 45855246 ps
CPU time 0.93 seconds
Started Apr 21 12:23:44 PM PDT 24
Finished Apr 21 12:23:45 PM PDT 24
Peak memory 197704 kb
Host smart-f881d99a-3da3-478a-bfb6-685d23e0913d
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3999680351 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3999680351
Directory /workspace/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/21.gpio_smoke_en_cdc_prim.1696245321
Short name T919
Test name
Test status
Simulation time 36695306 ps
CPU time 0.76 seconds
Started Apr 21 12:22:41 PM PDT 24
Finished Apr 21 12:22:43 PM PDT 24
Peak memory 191236 kb
Host smart-cc65aa73-426c-41f3-8d43-0a34d1cebb55
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1696245321 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_en_cdc_prim.1696245321
Directory /workspace/21.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim.229193037
Short name T935
Test name
Test status
Simulation time 139144500 ps
CPU time 1.19 seconds
Started Apr 21 12:20:32 PM PDT 24
Finished Apr 21 12:20:34 PM PDT 24
Peak memory 198060 kb
Host smart-cd17ca62-b157-4c75-8a85-e1f640ea60bc
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=229193037 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.229193037
Directory /workspace/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/22.gpio_smoke_en_cdc_prim.2332836159
Short name T874
Test name
Test status
Simulation time 53673346 ps
CPU time 1.48 seconds
Started Apr 21 12:18:24 PM PDT 24
Finished Apr 21 12:18:26 PM PDT 24
Peak memory 197668 kb
Host smart-ca3f0b3d-c47c-4adf-86e8-4dc0137a5922
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2332836159 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_en_cdc_prim.2332836159
Directory /workspace/22.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim.130496099
Short name T904
Test name
Test status
Simulation time 112484161 ps
CPU time 0.89 seconds
Started Apr 21 12:19:00 PM PDT 24
Finished Apr 21 12:19:01 PM PDT 24
Peak memory 191304 kb
Host smart-2b5b54d7-d6a3-4d71-abe2-e6baff18eb6d
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=130496099 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.130496099
Directory /workspace/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/23.gpio_smoke_en_cdc_prim.2590919261
Short name T847
Test name
Test status
Simulation time 102611714 ps
CPU time 1.03 seconds
Started Apr 21 12:19:44 PM PDT 24
Finished Apr 21 12:19:45 PM PDT 24
Peak memory 191308 kb
Host smart-5223e404-797c-4454-8ffc-f676027a1e43
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2590919261 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_en_cdc_prim.2590919261
Directory /workspace/23.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2790617202
Short name T913
Test name
Test status
Simulation time 211327031 ps
CPU time 1.13 seconds
Started Apr 21 12:22:52 PM PDT 24
Finished Apr 21 12:22:54 PM PDT 24
Peak memory 197080 kb
Host smart-4a9aab64-0031-4399-a0e6-0320ab5d7789
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2790617202 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2790617202
Directory /workspace/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/24.gpio_smoke_en_cdc_prim.1895840429
Short name T928
Test name
Test status
Simulation time 280110495 ps
CPU time 1.37 seconds
Started Apr 21 12:18:24 PM PDT 24
Finished Apr 21 12:18:26 PM PDT 24
Peak memory 197656 kb
Host smart-f4d9d6ae-7593-4467-9742-afd9769785d8
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1895840429 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_en_cdc_prim.1895840429
Directory /workspace/24.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2712318872
Short name T848
Test name
Test status
Simulation time 43628603 ps
CPU time 0.81 seconds
Started Apr 21 12:22:33 PM PDT 24
Finished Apr 21 12:22:34 PM PDT 24
Peak memory 189864 kb
Host smart-7edbeb8a-f330-4f85-a7cf-b4abc0d33b29
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2712318872 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2712318872
Directory /workspace/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/25.gpio_smoke_en_cdc_prim.224913985
Short name T865
Test name
Test status
Simulation time 50517608 ps
CPU time 0.97 seconds
Started Apr 21 12:23:44 PM PDT 24
Finished Apr 21 12:23:46 PM PDT 24
Peak memory 197600 kb
Host smart-9da23de9-e3cf-4779-a29d-f82dfcce432f
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=224913985 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_en_cdc_prim.224913985
Directory /workspace/25.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3840791903
Short name T896
Test name
Test status
Simulation time 41555619 ps
CPU time 1.11 seconds
Started Apr 21 12:22:40 PM PDT 24
Finished Apr 21 12:22:42 PM PDT 24
Peak memory 190500 kb
Host smart-080fb5f9-d2bd-4a19-8b1c-9b58a8651d48
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3840791903 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3840791903
Directory /workspace/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/26.gpio_smoke_en_cdc_prim.3976623925
Short name T900
Test name
Test status
Simulation time 65245118 ps
CPU time 0.81 seconds
Started Apr 21 12:22:50 PM PDT 24
Finished Apr 21 12:22:51 PM PDT 24
Peak memory 191028 kb
Host smart-0115e92d-758b-472a-9652-3482b8abdba3
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3976623925 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_en_cdc_prim.3976623925
Directory /workspace/26.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2535414130
Short name T897
Test name
Test status
Simulation time 235872743 ps
CPU time 1.11 seconds
Started Apr 21 12:19:43 PM PDT 24
Finished Apr 21 12:19:45 PM PDT 24
Peak memory 191308 kb
Host smart-3180ccff-640f-42a5-be4d-2d00fa8b1b07
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2535414130 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2535414130
Directory /workspace/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/27.gpio_smoke_en_cdc_prim.3964693680
Short name T858
Test name
Test status
Simulation time 38888974 ps
CPU time 1.11 seconds
Started Apr 21 12:20:51 PM PDT 24
Finished Apr 21 12:20:53 PM PDT 24
Peak memory 190420 kb
Host smart-a5660a4d-2c59-42dc-926f-1a7edb08e2a8
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3964693680 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_en_cdc_prim.3964693680
Directory /workspace/27.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim.572332482
Short name T887
Test name
Test status
Simulation time 30829974 ps
CPU time 0.91 seconds
Started Apr 21 12:23:44 PM PDT 24
Finished Apr 21 12:23:45 PM PDT 24
Peak memory 191372 kb
Host smart-40903f73-e11b-42c2-891d-3c1633741693
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=572332482 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.572332482
Directory /workspace/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/28.gpio_smoke_en_cdc_prim.298660656
Short name T863
Test name
Test status
Simulation time 135613346 ps
CPU time 1.18 seconds
Started Apr 21 12:23:44 PM PDT 24
Finished Apr 21 12:23:46 PM PDT 24
Peak memory 196400 kb
Host smart-3a58d498-3dad-4cc6-b01b-8754570515c7
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=298660656 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_en_cdc_prim.298660656
Directory /workspace/28.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2602686938
Short name T851
Test name
Test status
Simulation time 51883341 ps
CPU time 1.65 seconds
Started Apr 21 12:17:46 PM PDT 24
Finished Apr 21 12:17:48 PM PDT 24
Peak memory 197700 kb
Host smart-064b1a2f-3d5e-4ae6-925b-88c1d67f519f
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2602686938 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2602686938
Directory /workspace/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/29.gpio_smoke_en_cdc_prim.3915537383
Short name T894
Test name
Test status
Simulation time 476070631 ps
CPU time 1.06 seconds
Started Apr 21 12:22:42 PM PDT 24
Finished Apr 21 12:22:44 PM PDT 24
Peak memory 197704 kb
Host smart-cf5b3800-7bd9-4046-9c94-181bda87f4b0
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3915537383 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_en_cdc_prim.3915537383
Directory /workspace/29.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3313570791
Short name T885
Test name
Test status
Simulation time 27843471 ps
CPU time 0.85 seconds
Started Apr 21 12:23:29 PM PDT 24
Finished Apr 21 12:23:30 PM PDT 24
Peak memory 190568 kb
Host smart-98b775dc-8351-4d0f-8a4e-b4fd34c9e37f
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3313570791 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3313570791
Directory /workspace/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/3.gpio_smoke_en_cdc_prim.919585903
Short name T902
Test name
Test status
Simulation time 58849067 ps
CPU time 0.83 seconds
Started Apr 21 12:21:44 PM PDT 24
Finished Apr 21 12:21:45 PM PDT 24
Peak memory 195884 kb
Host smart-89d4e72f-3909-4966-b6f2-2b6fc0a221b6
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=919585903 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_en_cdc_prim.919585903
Directory /workspace/3.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3008997375
Short name T878
Test name
Test status
Simulation time 115612741 ps
CPU time 1.18 seconds
Started Apr 21 12:17:49 PM PDT 24
Finished Apr 21 12:17:51 PM PDT 24
Peak memory 190564 kb
Host smart-4d369f96-a94a-4a1b-a42c-dec1f0bd0640
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3008997375 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.3008997375
Directory /workspace/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/30.gpio_smoke_en_cdc_prim.165193956
Short name T850
Test name
Test status
Simulation time 393330792 ps
CPU time 1.31 seconds
Started Apr 21 12:22:49 PM PDT 24
Finished Apr 21 12:22:52 PM PDT 24
Peak memory 189904 kb
Host smart-bfc891a4-c008-4e0b-acbe-6b18da788e89
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=165193956 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_en_cdc_prim.165193956
Directory /workspace/30.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2679703723
Short name T844
Test name
Test status
Simulation time 109015918 ps
CPU time 0.77 seconds
Started Apr 21 12:21:44 PM PDT 24
Finished Apr 21 12:21:46 PM PDT 24
Peak memory 191336 kb
Host smart-a3377b49-9305-4d55-bd89-f363eb49ac73
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2679703723 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2679703723
Directory /workspace/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/31.gpio_smoke_en_cdc_prim.1213545140
Short name T889
Test name
Test status
Simulation time 75853364 ps
CPU time 0.84 seconds
Started Apr 21 12:20:32 PM PDT 24
Finished Apr 21 12:20:33 PM PDT 24
Peak memory 191680 kb
Host smart-6085e8bd-8098-42d5-bda3-d9c39e1fc716
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1213545140 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_en_cdc_prim.1213545140
Directory /workspace/31.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2807460355
Short name T934
Test name
Test status
Simulation time 634523715 ps
CPU time 1.4 seconds
Started Apr 21 12:20:30 PM PDT 24
Finished Apr 21 12:20:32 PM PDT 24
Peak memory 190248 kb
Host smart-f0e27d91-6d53-4572-b50b-b7be01da1f4c
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2807460355 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2807460355
Directory /workspace/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/32.gpio_smoke_en_cdc_prim.2817881804
Short name T881
Test name
Test status
Simulation time 207816990 ps
CPU time 1.12 seconds
Started Apr 21 12:21:48 PM PDT 24
Finished Apr 21 12:21:50 PM PDT 24
Peak memory 191764 kb
Host smart-3e138d6b-9039-45cc-86d2-b320274157ef
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2817881804 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_en_cdc_prim.2817881804
Directory /workspace/32.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1414256670
Short name T869
Test name
Test status
Simulation time 93670198 ps
CPU time 0.9 seconds
Started Apr 21 12:21:30 PM PDT 24
Finished Apr 21 12:21:31 PM PDT 24
Peak memory 191380 kb
Host smart-eb91111e-22bf-40da-a2de-0f01cea05a4f
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1414256670 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1414256670
Directory /workspace/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/33.gpio_smoke_en_cdc_prim.2881977459
Short name T876
Test name
Test status
Simulation time 44568905 ps
CPU time 1.22 seconds
Started Apr 21 12:23:44 PM PDT 24
Finished Apr 21 12:23:46 PM PDT 24
Peak memory 191016 kb
Host smart-f7056ee8-98d2-4baa-a628-4af2850419c0
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2881977459 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_en_cdc_prim.2881977459
Directory /workspace/33.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1892291697
Short name T877
Test name
Test status
Simulation time 145250029 ps
CPU time 1.07 seconds
Started Apr 21 12:22:41 PM PDT 24
Finished Apr 21 12:22:43 PM PDT 24
Peak memory 191308 kb
Host smart-2cd0b219-3f26-4bd7-b0d1-3ae1f1048109
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1892291697 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1892291697
Directory /workspace/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/34.gpio_smoke_en_cdc_prim.4138224929
Short name T880
Test name
Test status
Simulation time 170548459 ps
CPU time 1.39 seconds
Started Apr 21 12:23:44 PM PDT 24
Finished Apr 21 12:23:46 PM PDT 24
Peak memory 197368 kb
Host smart-25887427-61a7-48fe-b4d6-df47cf438d89
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4138224929 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_en_cdc_prim.4138224929
Directory /workspace/34.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3371069851
Short name T907
Test name
Test status
Simulation time 55777761 ps
CPU time 0.94 seconds
Started Apr 21 12:23:33 PM PDT 24
Finished Apr 21 12:23:34 PM PDT 24
Peak memory 197616 kb
Host smart-2b565281-665e-4bdd-9351-48bbcf9399fb
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3371069851 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3371069851
Directory /workspace/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/35.gpio_smoke_en_cdc_prim.696797719
Short name T845
Test name
Test status
Simulation time 65016385 ps
CPU time 1.2 seconds
Started Apr 21 12:22:41 PM PDT 24
Finished Apr 21 12:22:43 PM PDT 24
Peak memory 191132 kb
Host smart-2607e445-b856-44ba-a73c-efcbe6235241
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=696797719 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_en_cdc_prim.696797719
Directory /workspace/35.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim.183531529
Short name T937
Test name
Test status
Simulation time 45519442 ps
CPU time 1.23 seconds
Started Apr 21 12:18:30 PM PDT 24
Finished Apr 21 12:18:33 PM PDT 24
Peak memory 191432 kb
Host smart-140c618c-a380-4613-952a-d618c6c53e7f
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=183531529 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.183531529
Directory /workspace/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/36.gpio_smoke_en_cdc_prim.1952461112
Short name T861
Test name
Test status
Simulation time 65408731 ps
CPU time 1.26 seconds
Started Apr 21 12:18:40 PM PDT 24
Finished Apr 21 12:18:42 PM PDT 24
Peak memory 191384 kb
Host smart-6ca453fc-471a-48bd-85a4-abcb7f5d3ef7
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1952461112 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_en_cdc_prim.1952461112
Directory /workspace/36.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim.350199011
Short name T917
Test name
Test status
Simulation time 102441233 ps
CPU time 1.12 seconds
Started Apr 21 12:18:30 PM PDT 24
Finished Apr 21 12:18:33 PM PDT 24
Peak memory 191400 kb
Host smart-ea3ff30e-d727-4755-90bd-8d71eb169337
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=350199011 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.350199011
Directory /workspace/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/37.gpio_smoke_en_cdc_prim.2437883273
Short name T939
Test name
Test status
Simulation time 33925083 ps
CPU time 1.03 seconds
Started Apr 21 12:23:27 PM PDT 24
Finished Apr 21 12:23:29 PM PDT 24
Peak memory 190468 kb
Host smart-bfebabd3-e365-454f-99d2-03ac6aedf9ae
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2437883273 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_en_cdc_prim.2437883273
Directory /workspace/37.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1664253744
Short name T905
Test name
Test status
Simulation time 247261085 ps
CPU time 1.3 seconds
Started Apr 21 12:22:49 PM PDT 24
Finished Apr 21 12:22:52 PM PDT 24
Peak memory 190324 kb
Host smart-c8abf514-f8c3-4727-853a-7f42da83d609
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1664253744 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1664253744
Directory /workspace/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/38.gpio_smoke_en_cdc_prim.618442829
Short name T923
Test name
Test status
Simulation time 174822745 ps
CPU time 1.15 seconds
Started Apr 21 12:23:44 PM PDT 24
Finished Apr 21 12:23:46 PM PDT 24
Peak memory 191352 kb
Host smart-12e0474b-8dbf-4c06-a6a7-6e6308496033
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=618442829 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_en_cdc_prim.618442829
Directory /workspace/38.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2437355195
Short name T938
Test name
Test status
Simulation time 70845689 ps
CPU time 0.98 seconds
Started Apr 21 12:22:46 PM PDT 24
Finished Apr 21 12:22:49 PM PDT 24
Peak memory 197708 kb
Host smart-e72d80b9-dbaa-44c2-a40d-4a4d0da4db4f
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2437355195 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2437355195
Directory /workspace/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/39.gpio_smoke_en_cdc_prim.563174338
Short name T941
Test name
Test status
Simulation time 1038753688 ps
CPU time 1.15 seconds
Started Apr 21 12:21:29 PM PDT 24
Finished Apr 21 12:21:31 PM PDT 24
Peak memory 191392 kb
Host smart-206aa464-4524-44af-8a0a-77642c7c7924
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=563174338 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_en_cdc_prim.563174338
Directory /workspace/39.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim.717835246
Short name T860
Test name
Test status
Simulation time 906317489 ps
CPU time 1.28 seconds
Started Apr 21 12:22:34 PM PDT 24
Finished Apr 21 12:22:36 PM PDT 24
Peak memory 190684 kb
Host smart-583331b9-eb94-4234-afce-9dc1186480b5
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=717835246 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.717835246
Directory /workspace/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/4.gpio_smoke_en_cdc_prim.3036163715
Short name T873
Test name
Test status
Simulation time 25389621 ps
CPU time 0.72 seconds
Started Apr 21 12:22:31 PM PDT 24
Finished Apr 21 12:22:32 PM PDT 24
Peak memory 191332 kb
Host smart-3b4ddb6a-fe51-4f39-a37f-5ca81ceb0806
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3036163715 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_en_cdc_prim.3036163715
Directory /workspace/4.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4234690186
Short name T864
Test name
Test status
Simulation time 100197757 ps
CPU time 0.9 seconds
Started Apr 21 12:17:45 PM PDT 24
Finished Apr 21 12:17:47 PM PDT 24
Peak memory 189728 kb
Host smart-de7eb3a6-5ad1-4d7e-be6c-f917ec843100
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4234690186 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.4234690186
Directory /workspace/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/40.gpio_smoke_en_cdc_prim.3608553271
Short name T855
Test name
Test status
Simulation time 492778228 ps
CPU time 1.12 seconds
Started Apr 21 12:23:48 PM PDT 24
Finished Apr 21 12:23:49 PM PDT 24
Peak memory 196320 kb
Host smart-b4483505-24de-4978-a0cd-1f24316a6210
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3608553271 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_en_cdc_prim.3608553271
Directory /workspace/40.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2746589500
Short name T882
Test name
Test status
Simulation time 121630863 ps
CPU time 1.08 seconds
Started Apr 21 12:19:30 PM PDT 24
Finished Apr 21 12:19:31 PM PDT 24
Peak memory 191388 kb
Host smart-311cc929-a14a-4805-96ab-995c4af001f9
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2746589500 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2746589500
Directory /workspace/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/41.gpio_smoke_en_cdc_prim.2398375698
Short name T862
Test name
Test status
Simulation time 136237727 ps
CPU time 1.06 seconds
Started Apr 21 12:20:30 PM PDT 24
Finished Apr 21 12:20:32 PM PDT 24
Peak memory 191128 kb
Host smart-d6be41aa-a5fc-49f9-b3cd-7f8e0ab8d816
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2398375698 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_en_cdc_prim.2398375698
Directory /workspace/41.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim.21717686
Short name T870
Test name
Test status
Simulation time 18170124 ps
CPU time 0.77 seconds
Started Apr 21 12:22:42 PM PDT 24
Finished Apr 21 12:22:43 PM PDT 24
Peak memory 191128 kb
Host smart-794b0c56-e3bf-44b3-9302-0c2dd26cdf75
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21717686 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.21717686
Directory /workspace/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/42.gpio_smoke_en_cdc_prim.3484193240
Short name T908
Test name
Test status
Simulation time 509849437 ps
CPU time 1.14 seconds
Started Apr 21 12:19:24 PM PDT 24
Finished Apr 21 12:19:25 PM PDT 24
Peak memory 191400 kb
Host smart-eb91ba29-9dad-47f8-9037-a4e056405618
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3484193240 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_en_cdc_prim.3484193240
Directory /workspace/42.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3865168523
Short name T846
Test name
Test status
Simulation time 46123095 ps
CPU time 0.97 seconds
Started Apr 21 12:22:50 PM PDT 24
Finished Apr 21 12:22:51 PM PDT 24
Peak memory 191048 kb
Host smart-6124902a-20e6-4197-8650-5d047ff60ed9
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3865168523 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3865168523
Directory /workspace/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/43.gpio_smoke_en_cdc_prim.719216775
Short name T856
Test name
Test status
Simulation time 138537833 ps
CPU time 1.03 seconds
Started Apr 21 12:22:50 PM PDT 24
Finished Apr 21 12:22:52 PM PDT 24
Peak memory 196968 kb
Host smart-d8bbea6a-1306-4e84-8f68-6db1afcac573
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=719216775 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_en_cdc_prim.719216775
Directory /workspace/43.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1886222014
Short name T915
Test name
Test status
Simulation time 34771441 ps
CPU time 0.85 seconds
Started Apr 21 12:20:30 PM PDT 24
Finished Apr 21 12:20:32 PM PDT 24
Peak memory 191032 kb
Host smart-b5bd7426-6854-4b26-a849-66c4d171a527
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1886222014 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1886222014
Directory /workspace/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/44.gpio_smoke_en_cdc_prim.212943837
Short name T854
Test name
Test status
Simulation time 193925124 ps
CPU time 1.36 seconds
Started Apr 21 12:18:54 PM PDT 24
Finished Apr 21 12:18:55 PM PDT 24
Peak memory 191432 kb
Host smart-83a80dac-dda5-4ff2-a2c9-0ae2ec5056e4
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=212943837 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_en_cdc_prim.212943837
Directory /workspace/44.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3800116506
Short name T892
Test name
Test status
Simulation time 46373448 ps
CPU time 0.99 seconds
Started Apr 21 12:20:30 PM PDT 24
Finished Apr 21 12:20:31 PM PDT 24
Peak memory 190652 kb
Host smart-3a6a666c-2463-475a-9f68-def68639b9a6
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3800116506 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3800116506
Directory /workspace/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/45.gpio_smoke_en_cdc_prim.3961215835
Short name T914
Test name
Test status
Simulation time 40173030 ps
CPU time 0.88 seconds
Started Apr 21 12:18:50 PM PDT 24
Finished Apr 21 12:18:52 PM PDT 24
Peak memory 191684 kb
Host smart-e7047540-ef80-4cd5-9ad7-839d4b0bb5b1
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3961215835 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_en_cdc_prim.3961215835
Directory /workspace/45.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2638981375
Short name T924
Test name
Test status
Simulation time 45409826 ps
CPU time 0.94 seconds
Started Apr 21 12:20:30 PM PDT 24
Finished Apr 21 12:20:32 PM PDT 24
Peak memory 191036 kb
Host smart-2eb741ca-4e4f-44a3-bda5-15b11cdcc7da
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2638981375 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2638981375
Directory /workspace/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/46.gpio_smoke_en_cdc_prim.31089882
Short name T879
Test name
Test status
Simulation time 409290794 ps
CPU time 1.4 seconds
Started Apr 21 12:22:33 PM PDT 24
Finished Apr 21 12:22:35 PM PDT 24
Peak memory 189812 kb
Host smart-d157141d-fc1e-46a1-ae3a-016a7ae2d8c0
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=31089882 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_en_cdc_prim.31089882
Directory /workspace/46.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2679707245
Short name T916
Test name
Test status
Simulation time 78335253 ps
CPU time 1.21 seconds
Started Apr 21 12:22:33 PM PDT 24
Finished Apr 21 12:22:35 PM PDT 24
Peak memory 191148 kb
Host smart-8aac10b7-f4b4-435b-9f7c-a9d00b5551d4
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2679707245 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2679707245
Directory /workspace/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/47.gpio_smoke_en_cdc_prim.1181612639
Short name T893
Test name
Test status
Simulation time 68558956 ps
CPU time 1.29 seconds
Started Apr 21 12:17:48 PM PDT 24
Finished Apr 21 12:17:50 PM PDT 24
Peak memory 191232 kb
Host smart-79d59f06-7b8c-4cdb-ae09-9cab4ebcc7dd
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1181612639 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_en_cdc_prim.1181612639
Directory /workspace/47.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim.631209426
Short name T931
Test name
Test status
Simulation time 30068567 ps
CPU time 0.84 seconds
Started Apr 21 12:20:30 PM PDT 24
Finished Apr 21 12:20:31 PM PDT 24
Peak memory 194116 kb
Host smart-4951cba8-1440-4397-8ce8-e3ee76fbb627
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=631209426 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.631209426
Directory /workspace/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/48.gpio_smoke_en_cdc_prim.3608282272
Short name T930
Test name
Test status
Simulation time 257957247 ps
CPU time 1 seconds
Started Apr 21 12:20:30 PM PDT 24
Finished Apr 21 12:20:31 PM PDT 24
Peak memory 189472 kb
Host smart-8cd60d18-1d13-46b5-9e80-f8aad3224278
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3608282272 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_en_cdc_prim.3608282272
Directory /workspace/48.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1286270685
Short name T875
Test name
Test status
Simulation time 51910292 ps
CPU time 0.95 seconds
Started Apr 21 12:22:33 PM PDT 24
Finished Apr 21 12:22:34 PM PDT 24
Peak memory 196676 kb
Host smart-d75cf4d7-0f16-4e59-a21a-ff5ca1f209b6
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1286270685 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1286270685
Directory /workspace/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/49.gpio_smoke_en_cdc_prim.14863540
Short name T911
Test name
Test status
Simulation time 65404888 ps
CPU time 1.31 seconds
Started Apr 21 12:22:33 PM PDT 24
Finished Apr 21 12:22:35 PM PDT 24
Peak memory 196216 kb
Host smart-e50f4a4c-2683-406d-bc98-b33c07edde4b
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=14863540 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_en_cdc_prim.14863540
Directory /workspace/49.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim.529985074
Short name T922
Test name
Test status
Simulation time 233351886 ps
CPU time 1.29 seconds
Started Apr 21 12:20:30 PM PDT 24
Finished Apr 21 12:20:32 PM PDT 24
Peak memory 189708 kb
Host smart-110247f9-2c2e-4921-965c-c018caf99b38
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=529985074 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.529985074
Directory /workspace/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/5.gpio_smoke_en_cdc_prim.1173461753
Short name T925
Test name
Test status
Simulation time 76642147 ps
CPU time 0.98 seconds
Started Apr 21 12:17:53 PM PDT 24
Finished Apr 21 12:17:55 PM PDT 24
Peak memory 191368 kb
Host smart-29a2b9b4-f7c4-4dd7-b819-ca5fa426dd4b
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1173461753 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_en_cdc_prim.1173461753
Directory /workspace/5.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4170071237
Short name T884
Test name
Test status
Simulation time 65746590 ps
CPU time 1.07 seconds
Started Apr 21 12:21:14 PM PDT 24
Finished Apr 21 12:21:16 PM PDT 24
Peak memory 196268 kb
Host smart-14d46872-c255-4a3d-860c-79c894131473
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4170071237 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.4170071237
Directory /workspace/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/6.gpio_smoke_en_cdc_prim.2648413340
Short name T849
Test name
Test status
Simulation time 335832514 ps
CPU time 1.49 seconds
Started Apr 21 12:21:37 PM PDT 24
Finished Apr 21 12:21:39 PM PDT 24
Peak memory 191764 kb
Host smart-6c1ec479-51ce-4bdc-a06a-6e4c49590edf
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2648413340 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_en_cdc_prim.2648413340
Directory /workspace/6.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1437632487
Short name T853
Test name
Test status
Simulation time 452155763 ps
CPU time 0.84 seconds
Started Apr 21 12:23:02 PM PDT 24
Finished Apr 21 12:23:03 PM PDT 24
Peak memory 191292 kb
Host smart-ed9eccbc-f31b-4869-8a71-f2bea4156fc8
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1437632487 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.1437632487
Directory /workspace/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/7.gpio_smoke_en_cdc_prim.2942098874
Short name T868
Test name
Test status
Simulation time 261403482 ps
CPU time 1.09 seconds
Started Apr 21 12:17:53 PM PDT 24
Finished Apr 21 12:17:55 PM PDT 24
Peak memory 191336 kb
Host smart-6224718a-6dc0-4cdb-90e1-561378061f27
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2942098874 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_en_cdc_prim.2942098874
Directory /workspace/7.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2778448899
Short name T883
Test name
Test status
Simulation time 133282852 ps
CPU time 1.01 seconds
Started Apr 21 12:22:33 PM PDT 24
Finished Apr 21 12:22:35 PM PDT 24
Peak memory 197448 kb
Host smart-2e211f19-8ae8-40ea-826f-4d9799d15f24
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2778448899 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.2778448899
Directory /workspace/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/8.gpio_smoke_en_cdc_prim.1742367183
Short name T899
Test name
Test status
Simulation time 75943114 ps
CPU time 0.88 seconds
Started Apr 21 12:22:52 PM PDT 24
Finished Apr 21 12:22:54 PM PDT 24
Peak memory 191156 kb
Host smart-7aad1556-65ec-4856-a4f1-6f1655c9b1f3
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1742367183 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_en_cdc_prim.1742367183
Directory /workspace/8.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4122397016
Short name T843
Test name
Test status
Simulation time 111030834 ps
CPU time 0.84 seconds
Started Apr 21 12:22:33 PM PDT 24
Finished Apr 21 12:22:34 PM PDT 24
Peak memory 195040 kb
Host smart-12d0e026-b217-49b6-a9f9-b22782368ebe
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4122397016 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.4122397016
Directory /workspace/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/9.gpio_smoke_en_cdc_prim.641000510
Short name T891
Test name
Test status
Simulation time 159839377 ps
CPU time 1.47 seconds
Started Apr 21 12:17:52 PM PDT 24
Finished Apr 21 12:17:54 PM PDT 24
Peak memory 197620 kb
Host smart-d0f2d66c-4cef-4155-a207-0437edb92c1b
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=641000510 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_en_cdc_prim.641000510
Directory /workspace/9.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4120975003
Short name T901
Test name
Test status
Simulation time 39224027 ps
CPU time 1.2 seconds
Started Apr 21 12:18:26 PM PDT 24
Finished Apr 21 12:18:28 PM PDT 24
Peak memory 191744 kb
Host smart-ca7d282b-7b12-434a-8ff5-c526184ff019
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4120975003 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.4120975003
Directory /workspace/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest
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