Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	36	0	36	100.00
Crosses	128	0	128	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	32	0	32	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	128	0	128	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	3869572	1			T23	27		T24	1		T1	25447
all_pins[1]	3869572	1			T23	27		T24	1		T1	25447
all_pins[2]	3869572	1			T23	27		T24	1		T1	25447
all_pins[3]	3869572	1			T23	27		T24	1		T1	25447
all_pins[4]	3869572	1			T23	27		T24	1		T1	25447
all_pins[5]	3869572	1			T23	27		T24	1		T1	25447
all_pins[6]	3869572	1			T23	27		T24	1		T1	25447
all_pins[7]	3869572	1			T23	27		T24	1		T1	25447
all_pins[8]	3869572	1			T23	27		T24	1		T1	25447
all_pins[9]	3869572	1			T23	27		T24	1		T1	25447
all_pins[10]	3869572	1			T23	27		T24	1		T1	25447
all_pins[11]	3869572	1			T23	27		T24	1		T1	25447
all_pins[12]	3869572	1			T23	27		T24	1		T1	25447
all_pins[13]	3869572	1			T23	27		T24	1		T1	25447
all_pins[14]	3869572	1			T23	27		T24	1		T1	25447
all_pins[15]	3869572	1			T23	27		T24	1		T1	25447
all_pins[16]	3869572	1			T23	27		T24	1		T1	25447
all_pins[17]	3869572	1			T23	27		T24	1		T1	25447
all_pins[18]	3869572	1			T23	27		T24	1		T1	25447
all_pins[19]	3869572	1			T23	27		T24	1		T1	25447
all_pins[20]	3869572	1			T23	27		T24	1		T1	25447
all_pins[21]	3869572	1			T23	27		T24	1		T1	25447
all_pins[22]	3869572	1			T23	27		T24	1		T1	25447
all_pins[23]	3869572	1			T23	27		T24	1		T1	25447
all_pins[24]	3869572	1			T23	27		T24	1		T1	25447
all_pins[25]	3869572	1			T23	27		T24	1		T1	25447
all_pins[26]	3869572	1			T23	27		T24	1		T1	25447
all_pins[27]	3869572	1			T23	27		T24	1		T1	25447
all_pins[28]	3869572	1			T23	27		T24	1		T1	25447
all_pins[29]	3869572	1			T23	27		T24	1		T1	25447
all_pins[30]	3869572	1			T23	27		T24	1		T1	25447
all_pins[31]	3869572	1			T23	27		T24	1		T1	25447

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	76914003	1			T23	466		T24	32		T1	506674
values[0x1]	46912301	1			T23	398		T1	307630		T11	2214
transitions[0x0=>0x1]	28100658	1			T23	208		T1	184573		T11	1402
transitions[0x1=>0x0]	28100492	1			T23	207		T1	184572		T11	1402

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	2400668	1			T23	21		T24	1		T1	15937
all_pins[0]	values[0x1]	1468904	1			T23	6		T1	9510		T11	49
all_pins[0]	transitions[0x0=>0x1]	907043	1			T23	2		T1	5877		T11	38
all_pins[0]	transitions[0x1=>0x0]	906758	1			T23	12		T1	5828		T11	42
all_pins[1]	values[0x0]	2411587	1			T23	19		T24	1		T1	15971
all_pins[1]	values[0x1]	1457985	1			T23	8		T1	9476		T11	83
all_pins[1]	transitions[0x0=>0x1]	872337	1			T23	7		T1	5773		T11	54
all_pins[1]	transitions[0x1=>0x0]	883256	1			T23	5		T1	5807		T11	20
all_pins[2]	values[0x0]	2407856	1			T23	12		T24	1		T1	15598
all_pins[2]	values[0x1]	1461716	1			T23	15		T1	9849		T11	72
all_pins[2]	transitions[0x0=>0x1]	877004	1			T23	11		T1	5808		T11	43
all_pins[2]	transitions[0x1=>0x0]	873273	1			T23	4		T1	5435		T11	54
all_pins[3]	values[0x0]	2405264	1			T23	13		T24	1		T1	15958
all_pins[3]	values[0x1]	1464308	1			T23	14		T1	9489		T11	69
all_pins[3]	transitions[0x0=>0x1]	878967	1			T23	5		T1	5641		T11	45
all_pins[3]	transitions[0x1=>0x0]	876375	1			T23	6		T1	6001		T11	48
all_pins[4]	values[0x0]	2403976	1			T23	15		T24	1		T1	15845
all_pins[4]	values[0x1]	1465596	1			T23	12		T1	9602		T11	80
all_pins[4]	transitions[0x0=>0x1]	878457	1			T23	6		T1	5720		T11	45
all_pins[4]	transitions[0x1=>0x0]	877169	1			T23	8		T1	5607		T11	34
all_pins[5]	values[0x0]	2402873	1			T23	13		T24	1		T1	15920
all_pins[5]	values[0x1]	1466699	1			T23	14		T1	9527		T11	93
all_pins[5]	transitions[0x0=>0x1]	876074	1			T23	8		T1	5785		T11	60
all_pins[5]	transitions[0x1=>0x0]	874971	1			T23	6		T1	5860		T11	47
all_pins[6]	values[0x0]	2404186	1			T23	15		T24	1		T1	15915
all_pins[6]	values[0x1]	1465386	1			T23	12		T1	9532		T11	68
all_pins[6]	transitions[0x0=>0x1]	874450	1			T23	6		T1	5790		T11	28
all_pins[6]	transitions[0x1=>0x0]	875763	1			T23	8		T1	5785		T11	53
all_pins[7]	values[0x0]	2405777	1			T23	17		T24	1		T1	15813
all_pins[7]	values[0x1]	1463795	1			T23	10		T1	9634		T11	107
all_pins[7]	transitions[0x0=>0x1]	875715	1			T23	4		T1	5780		T11	70
all_pins[7]	transitions[0x1=>0x0]	877306	1			T23	6		T1	5678		T11	31
all_pins[8]	values[0x0]	2405434	1			T23	13		T24	1		T1	15872
all_pins[8]	values[0x1]	1464138	1			T23	14		T1	9575		T11	103
all_pins[8]	transitions[0x0=>0x1]	876259	1			T23	9		T1	5634		T11	49
all_pins[8]	transitions[0x1=>0x0]	875916	1			T23	5		T1	5693		T11	53
all_pins[9]	values[0x0]	2404752	1			T23	10		T24	1		T1	15559
all_pins[9]	values[0x1]	1464820	1			T23	17		T1	9888		T11	88
all_pins[9]	transitions[0x0=>0x1]	880322	1			T23	9		T1	6021		T11	39
all_pins[9]	transitions[0x1=>0x0]	879640	1			T23	6		T1	5708		T11	54
all_pins[10]	values[0x0]	2401148	1			T23	13		T24	1		T1	15882
all_pins[10]	values[0x1]	1468424	1			T23	14		T1	9565		T11	59
all_pins[10]	transitions[0x0=>0x1]	879176	1			T23	3		T1	5714		T11	40
all_pins[10]	transitions[0x1=>0x0]	875572	1			T23	6		T1	6037		T11	69
all_pins[11]	values[0x0]	2406723	1			T23	16		T24	1		T1	16005
all_pins[11]	values[0x1]	1462849	1			T23	11		T1	9442		T11	98
all_pins[11]	transitions[0x0=>0x1]	874027	1			T23	5		T1	5812		T11	70
all_pins[11]	transitions[0x1=>0x0]	879602	1			T23	8		T1	5935		T11	31
all_pins[12]	values[0x0]	2404315	1			T23	16		T24	1		T1	15594
all_pins[12]	values[0x1]	1465257	1			T23	11		T1	9853		T11	71
all_pins[12]	transitions[0x0=>0x1]	879451	1			T23	4		T1	5988		T11	34
all_pins[12]	transitions[0x1=>0x0]	877043	1			T23	4		T1	5577		T11	61
all_pins[13]	values[0x0]	2402096	1			T23	16		T24	1		T1	15880
all_pins[13]	values[0x1]	1467476	1			T23	11		T1	9567		T11	74
all_pins[13]	transitions[0x0=>0x1]	878322	1			T23	6		T1	5681		T11	54
all_pins[13]	transitions[0x1=>0x0]	876103	1			T23	6		T1	5967		T11	51
all_pins[14]	values[0x0]	2404123	1			T23	12		T24	1		T1	16013
all_pins[14]	values[0x1]	1465449	1			T23	15		T1	9434		T11	66
all_pins[14]	transitions[0x0=>0x1]	877254	1			T23	10		T1	5769		T11	32
all_pins[14]	transitions[0x1=>0x0]	879281	1			T23	6		T1	5902		T11	40
all_pins[15]	values[0x0]	2400292	1			T23	18		T24	1		T1	15453
all_pins[15]	values[0x1]	1469280	1			T23	9		T1	9994		T11	79
all_pins[15]	transitions[0x0=>0x1]	879193	1			T23	5		T1	6134		T11	44
all_pins[15]	transitions[0x1=>0x0]	875362	1			T23	11		T1	5574		T11	31
all_pins[16]	values[0x0]	2397191	1			T23	16		T24	1		T1	15669
all_pins[16]	values[0x1]	1472381	1			T23	11		T1	9778		T11	68
all_pins[16]	transitions[0x0=>0x1]	880396	1			T23	8		T1	5733		T11	37
all_pins[16]	transitions[0x1=>0x0]	877295	1			T23	6		T1	5949		T11	48
all_pins[17]	values[0x0]	2397920	1			T23	11		T24	1		T1	16066
all_pins[17]	values[0x1]	1471652	1			T23	16		T1	9381		T11	81
all_pins[17]	transitions[0x0=>0x1]	878715	1			T23	11		T1	5672		T11	49
all_pins[17]	transitions[0x1=>0x0]	879444	1			T23	6		T1	6069		T11	36
all_pins[18]	values[0x0]	2401192	1			T23	11		T24	1		T1	15791
all_pins[18]	values[0x1]	1468380	1			T23	16		T1	9656		T11	40
all_pins[18]	transitions[0x0=>0x1]	875690	1			T23	8		T1	6082		T11	27
all_pins[18]	transitions[0x1=>0x0]	878962	1			T23	8		T1	5807		T11	68
all_pins[19]	values[0x0]	2407853	1			T23	13		T24	1		T1	15860
all_pins[19]	values[0x1]	1461719	1			T23	14		T1	9587		T11	79
all_pins[19]	transitions[0x0=>0x1]	875097	1			T23	2		T1	5566		T11	62
all_pins[19]	transitions[0x1=>0x0]	881758	1			T23	4		T1	5635		T11	23
all_pins[20]	values[0x0]	2406023	1			T23	17		T24	1		T1	16041
all_pins[20]	values[0x1]	1463549	1			T23	10		T1	9406		T11	33
all_pins[20]	transitions[0x0=>0x1]	876684	1			T23	5		T1	5588		T11	21
all_pins[20]	transitions[0x1=>0x0]	874854	1			T23	9		T1	5769		T11	67
all_pins[21]	values[0x0]	2405312	1			T23	11		T24	1		T1	15530
all_pins[21]	values[0x1]	1464260	1			T23	16		T1	9917		T11	47
all_pins[21]	transitions[0x0=>0x1]	874996	1			T23	10		T1	6039		T11	36
all_pins[21]	transitions[0x1=>0x0]	874285	1			T23	4		T1	5528		T11	22
all_pins[22]	values[0x0]	2403324	1			T23	13		T24	1		T1	15529
all_pins[22]	values[0x1]	1466248	1			T23	14		T1	9918		T11	40
all_pins[22]	transitions[0x0=>0x1]	877443	1			T23	6		T1	5770		T11	33
all_pins[22]	transitions[0x1=>0x0]	875455	1			T23	8		T1	5769		T11	40
all_pins[23]	values[0x0]	2404603	1			T23	15		T24	1		T1	15762
all_pins[23]	values[0x1]	1464969	1			T23	12		T1	9685		T11	51
all_pins[23]	transitions[0x0=>0x1]	876791	1			T23	5		T1	5563		T11	49
all_pins[23]	transitions[0x1=>0x0]	878070	1			T23	7		T1	5796		T11	38
all_pins[24]	values[0x0]	2398559	1			T23	21		T24	1		T1	16109
all_pins[24]	values[0x1]	1471013	1			T23	6		T1	9338		T11	62
all_pins[24]	transitions[0x0=>0x1]	882864	1			T23	3		T1	5635		T11	44
all_pins[24]	transitions[0x1=>0x0]	876820	1			T23	9		T1	5982		T11	33
all_pins[25]	values[0x0]	2398314	1			T23	15		T24	1		T1	15750
all_pins[25]	values[0x1]	1471258	1			T23	12		T1	9697		T11	71
all_pins[25]	transitions[0x0=>0x1]	875275	1			T23	10		T1	5738		T11	58
all_pins[25]	transitions[0x1=>0x0]	875030	1			T23	4		T1	5379		T11	49
all_pins[26]	values[0x0]	2403749	1			T23	10		T24	1		T1	15654
all_pins[26]	values[0x1]	1465823	1			T23	17		T1	9793		T11	58
all_pins[26]	transitions[0x0=>0x1]	875559	1			T23	9		T1	5919		T11	27
all_pins[26]	transitions[0x1=>0x0]	880994	1			T23	4		T1	5823		T11	40
all_pins[27]	values[0x0]	2409478	1			T23	16		T24	1		T1	15715
all_pins[27]	values[0x1]	1460094	1			T23	11		T1	9732		T11	52
all_pins[27]	transitions[0x0=>0x1]	873046	1			T23	4		T1	5784		T11	33
all_pins[27]	transitions[0x1=>0x0]	878775	1			T23	10		T1	5845		T11	39
all_pins[28]	values[0x0]	2401260	1			T23	17		T24	1		T1	15624
all_pins[28]	values[0x1]	1468312	1			T23	10		T1	9823		T11	51
all_pins[28]	transitions[0x0=>0x1]	881212	1			T23	7		T1	5751		T11	40
all_pins[28]	transitions[0x1=>0x0]	872994	1			T23	8		T1	5660		T11	41
all_pins[29]	values[0x0]	2404950	1			T23	14		T24	1		T1	16088
all_pins[29]	values[0x1]	1464622	1			T23	13		T1	9359		T11	82
all_pins[29]	transitions[0x0=>0x1]	875487	1			T23	6		T1	5438		T11	66
all_pins[29]	transitions[0x1=>0x0]	879177	1			T23	3		T1	5902		T11	35
all_pins[30]	values[0x0]	2402418	1			T23	17		T24	1		T1	16286
all_pins[30]	values[0x1]	1467154	1			T23	10		T1	9161		T11	87
all_pins[30]	transitions[0x0=>0x1]	878580	1			T23	4		T1	5574		T11	38
all_pins[30]	transitions[0x1=>0x0]	876048	1			T23	7		T1	5772		T11	33
all_pins[31]	values[0x0]	2400787	1			T23	10		T24	1		T1	15985
all_pins[31]	values[0x1]	1468785	1			T23	17		T1	9462		T11	53
all_pins[31]	transitions[0x0=>0x1]	878772	1			T23	10		T1	5794		T11	37
all_pins[31]	transitions[0x1=>0x0]	877141	1			T23	3		T1	5493		T11	71