Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	192	0	192	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	32	0	32	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	192	0	192	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	12963129	1			T23	490		T24	152		T1	81968
all_values[1]	12963129	1			T23	490		T24	152		T1	81968
all_values[2]	12963129	1			T23	490		T24	152		T1	81968
all_values[3]	12963129	1			T23	490		T24	152		T1	81968
all_values[4]	12963129	1			T23	490		T24	152		T1	81968
all_values[5]	12963129	1			T23	490		T24	152		T1	81968
all_values[6]	12963129	1			T23	490		T24	152		T1	81968
all_values[7]	12963129	1			T23	490		T24	152		T1	81968
all_values[8]	12963129	1			T23	490		T24	152		T1	81968
all_values[9]	12963129	1			T23	490		T24	152		T1	81968
all_values[10]	12963129	1			T23	490		T24	152		T1	81968
all_values[11]	12963129	1			T23	490		T24	152		T1	81968
all_values[12]	12963129	1			T23	490		T24	152		T1	81968
all_values[13]	12963129	1			T23	490		T24	152		T1	81968
all_values[14]	12963129	1			T23	490		T24	152		T1	81968
all_values[15]	12963129	1			T23	490		T24	152		T1	81968
all_values[16]	12963129	1			T23	490		T24	152		T1	81968
all_values[17]	12963129	1			T23	490		T24	152		T1	81968
all_values[18]	12963129	1			T23	490		T24	152		T1	81968
all_values[19]	12963129	1			T23	490		T24	152		T1	81968
all_values[20]	12963129	1			T23	490		T24	152		T1	81968
all_values[21]	12963129	1			T23	490		T24	152		T1	81968
all_values[22]	12963129	1			T23	490		T24	152		T1	81968
all_values[23]	12963129	1			T23	490		T24	152		T1	81968
all_values[24]	12963129	1			T23	490		T24	152		T1	81968
all_values[25]	12963129	1			T23	490		T24	152		T1	81968
all_values[26]	12963129	1			T23	490		T24	152		T1	81968
all_values[27]	12963129	1			T23	490		T24	152		T1	81968
all_values[28]	12963129	1			T23	490		T24	152		T1	81968
all_values[29]	12963129	1			T23	490		T24	152		T1	81968
all_values[30]	12963129	1			T23	490		T24	152		T1	81968
all_values[31]	12963129	1			T23	490		T24	152		T1	81968

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

239125033

1

T23

15680

T24

4864

T1

146319

auto[1]

175695095

1

T1

115977

T11

4354

T12

239

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

97148472

1

T23

15680

T24

4864

T1

509989

auto[1]

317671656

1

T1

211298

T11

7267

T12

297

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

410259865

1

T23

15680

T24

4864

T1

257586

auto[1]

4560263

1

T1

47110

T12

29

T16

231

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	192	0	192	100.00
Automatically Generated Cross Bins	192	0	192	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	2503579	1			T23	490		T24	152		T1	12238
all_values[0]	auto[0]	auto[0]	auto[1]	4897707	1			T1	32491		T11	81		T12	3
all_values[0]	auto[0]	auto[1]	auto[0]	527356	1			T1	3926		T11	50		T12	2
all_values[0]	auto[0]	auto[1]	auto[1]	4892129	1			T1	31841		T11	89		T12	4
all_values[0]	auto[1]	auto[0]	auto[1]	71499	1			T1	724		T12	1		T16	5
all_values[0]	auto[1]	auto[1]	auto[1]	70859	1			T1	748		T16	2		T127	5
all_values[1]	auto[0]	auto[0]	auto[0]	2512453	1			T23	490		T24	152		T1	12305
all_values[1]	auto[0]	auto[0]	auto[1]	4920171	1			T1	32284		T11	96		T12	2
all_values[1]	auto[0]	auto[1]	auto[0]	538025	1			T1	3403		T11	20		T12	7
all_values[1]	auto[0]	auto[1]	auto[1]	4849990	1			T1	32545		T11	124		T12	4
all_values[1]	auto[1]	auto[0]	auto[1]	71452	1			T1	737		T12	2		T16	3
all_values[1]	auto[1]	auto[1]	auto[1]	71038	1			T1	694		T16	2		T17	1
all_values[2]	auto[0]	auto[0]	auto[0]	2503170	1			T23	490		T24	152		T1	12143
all_values[2]	auto[0]	auto[0]	auto[1]	4917157	1			T1	32025		T11	117		T12	2
all_values[2]	auto[0]	auto[1]	auto[0]	527323	1			T1	3675		T11	30		T12	2
all_values[2]	auto[0]	auto[1]	auto[1]	4873223	1			T1	32662		T11	111		T12	9
all_values[2]	auto[1]	auto[0]	auto[1]	71414	1			T1	731		T12	2		T16	6
all_values[2]	auto[1]	auto[1]	auto[1]	70842	1			T1	732		T16	2		T17	1
all_values[3]	auto[0]	auto[0]	auto[0]	2514206	1			T23	490		T24	152		T1	12323
all_values[3]	auto[0]	auto[0]	auto[1]	4907684	1			T1	33150		T11	103		T12	7
all_values[3]	auto[0]	auto[1]	auto[0]	528852	1			T1	3363		T11	43		T12	5
all_values[3]	auto[0]	auto[1]	auto[1]	4869940	1			T1	31692		T11	115		T16	6
all_values[3]	auto[1]	auto[0]	auto[1]	71674	1			T1	720		T12	2		T16	3
all_values[3]	auto[1]	auto[1]	auto[1]	70773	1			T1	720		T16	2		T17	2
all_values[4]	auto[0]	auto[0]	auto[0]	2510839	1			T23	490		T24	152		T1	12192
all_values[4]	auto[0]	auto[0]	auto[1]	4886483	1			T1	32771		T11	87		T12	14
all_values[4]	auto[0]	auto[1]	auto[0]	532838	1			T1	3948		T11	23		T12	3
all_values[4]	auto[0]	auto[1]	auto[1]	4890883	1			T1	31631		T11	133		T12	2
all_values[4]	auto[1]	auto[0]	auto[1]	71024	1			T1	724		T16	6		T17	2
all_values[4]	auto[1]	auto[1]	auto[1]	71062	1			T1	702		T16	2		T17	1
all_values[5]	auto[0]	auto[0]	auto[0]	2506595	1			T23	490		T24	152		T1	11768
all_values[5]	auto[0]	auto[0]	auto[1]	4863431	1			T1	33725		T11	111		T12	8
all_values[5]	auto[0]	auto[1]	auto[0]	530711	1			T1	3486		T11	12		T12	11
all_values[5]	auto[0]	auto[1]	auto[1]	4919752	1			T1	31488		T11	144		T16	9
all_values[5]	auto[1]	auto[0]	auto[1]	71015	1			T1	798		T12	1		T16	6
all_values[5]	auto[1]	auto[1]	auto[1]	71625	1			T1	703		T16	2		T17	1
all_values[6]	auto[0]	auto[0]	auto[0]	2508776	1			T23	490		T24	152		T1	12471
all_values[6]	auto[0]	auto[0]	auto[1]	4891963	1			T1	33942		T11	135		T12	3
all_values[6]	auto[0]	auto[1]	auto[0]	532176	1			T1	3483		T11	11		T12	11
all_values[6]	auto[0]	auto[1]	auto[1]	4888106	1			T1	30616		T11	104		T16	9
all_values[6]	auto[1]	auto[0]	auto[1]	71161	1			T1	780		T12	1		T16	6
all_values[6]	auto[1]	auto[1]	auto[1]	70947	1			T1	676		T127	2		T128	42
all_values[7]	auto[0]	auto[0]	auto[0]	2502927	1			T23	490		T24	152		T1	12248
all_values[7]	auto[0]	auto[0]	auto[1]	4929027	1			T1	33703		T11	69		T12	1
all_values[7]	auto[0]	auto[1]	auto[0]	527047	1			T1	3338		T11	41		T12	6
all_values[7]	auto[0]	auto[1]	auto[1]	4861238	1			T1	31109		T11	143		T12	5
all_values[7]	auto[1]	auto[0]	auto[1]	71977	1			T1	812		T16	9		T17	3
all_values[7]	auto[1]	auto[1]	auto[1]	70913	1			T1	758		T16	1		T127	1
all_values[8]	auto[0]	auto[0]	auto[0]	2502031	1			T23	490		T24	152		T1	12295
all_values[8]	auto[0]	auto[0]	auto[1]	4898110	1			T1	32476		T11	105		T12	3
all_values[8]	auto[0]	auto[1]	auto[0]	530596	1			T1	3930		T11	24		T16	19
all_values[8]	auto[0]	auto[1]	auto[1]	4889816	1			T1	31794		T11	147		T12	6
all_values[8]	auto[1]	auto[0]	auto[1]	71429	1			T1	715		T16	3		T17	1
all_values[8]	auto[1]	auto[1]	auto[1]	71147	1			T1	758		T17	1		T127	1
all_values[9]	auto[0]	auto[0]	auto[0]	2505356	1			T23	490		T24	152		T1	12145
all_values[9]	auto[0]	auto[0]	auto[1]	4874536	1			T1	32106		T11	103		T12	1
all_values[9]	auto[0]	auto[1]	auto[0]	530352	1			T1	3498		T11	43		T12	11
all_values[9]	auto[0]	auto[1]	auto[1]	4910504	1			T1	32753		T11	131		T16	13
all_values[9]	auto[1]	auto[0]	auto[1]	71648	1			T1	698		T12	1		T16	5
all_values[9]	auto[1]	auto[1]	auto[1]	70733	1			T1	768		T16	4		T127	3
all_values[10]	auto[0]	auto[0]	auto[0]	2504020	1			T23	490		T24	152		T1	12158
all_values[10]	auto[0]	auto[0]	auto[1]	4902610	1			T1	32737		T11	146		T12	1
all_values[10]	auto[0]	auto[1]	auto[0]	529750	1			T1	3592		T11	23		T12	6
all_values[10]	auto[0]	auto[1]	auto[1]	4883848	1			T1	32004		T11	91		T16	5
all_values[10]	auto[1]	auto[0]	auto[1]	71383	1			T1	787		T12	1		T16	4
all_values[10]	auto[1]	auto[1]	auto[1]	71518	1			T1	690		T17	1		T127	1
all_values[11]	auto[0]	auto[0]	auto[0]	2505865	1			T23	490		T24	152		T1	12257
all_values[11]	auto[0]	auto[0]	auto[1]	4899137	1			T1	33018		T11	105		T12	13
all_values[11]	auto[0]	auto[1]	auto[0]	528951	1			T1	3784		T11	9		T12	2
all_values[11]	auto[0]	auto[1]	auto[1]	4886451	1			T1	31429		T11	140		T12	3
all_values[11]	auto[1]	auto[0]	auto[1]	71983	1			T1	730		T12	2		T16	8
all_values[11]	auto[1]	auto[1]	auto[1]	70742	1			T1	750		T16	1		T17	2
all_values[12]	auto[0]	auto[0]	auto[0]	2503790	1			T23	490		T24	152		T1	11899
all_values[12]	auto[0]	auto[0]	auto[1]	4893232	1			T1	32709		T11	85		T12	3
all_values[12]	auto[0]	auto[1]	auto[0]	528643	1			T1	3726		T11	52		T12	1
all_values[12]	auto[0]	auto[1]	auto[1]	4894604	1			T1	32107		T11	113		T12	5
all_values[12]	auto[1]	auto[0]	auto[1]	71151	1			T1	749		T12	1		T16	5
all_values[12]	auto[1]	auto[1]	auto[1]	71709	1			T1	778		T16	5		T17	2
all_values[13]	auto[0]	auto[0]	auto[0]	2502109	1			T23	490		T24	152		T1	12273
all_values[13]	auto[0]	auto[0]	auto[1]	4885773	1			T1	33540		T11	107		T12	6
all_values[13]	auto[0]	auto[1]	auto[0]	532410	1			T1	3573		T11	27		T16	16
all_values[13]	auto[0]	auto[1]	auto[1]	4900585	1			T1	31109		T11	125		T16	32
all_values[13]	auto[1]	auto[0]	auto[1]	71330	1			T1	738		T12	1		T16	6
all_values[13]	auto[1]	auto[1]	auto[1]	70922	1			T1	735		T16	2		T128	44
all_values[14]	auto[0]	auto[0]	auto[0]	2504128	1			T23	490		T24	152		T1	12614
all_values[14]	auto[0]	auto[0]	auto[1]	4883405	1			T1	32360		T11	143		T12	3
all_values[14]	auto[0]	auto[1]	auto[0]	527481	1			T1	3764		T11	3		T16	13
all_values[14]	auto[0]	auto[1]	auto[1]	4905472	1			T1	31757		T11	115		T12	6
all_values[14]	auto[1]	auto[0]	auto[1]	71438	1			T1	763		T16	8		T17	1
all_values[14]	auto[1]	auto[1]	auto[1]	71205	1			T1	710		T16	1		T128	49
all_values[15]	auto[0]	auto[0]	auto[0]	2507211	1			T23	490		T24	152		T1	12076
all_values[15]	auto[0]	auto[0]	auto[1]	4867021	1			T1	31774		T11	117		T12	2
all_values[15]	auto[0]	auto[1]	auto[0]	526026	1			T1	3693		T11	28		T12	6
all_values[15]	auto[0]	auto[1]	auto[1]	4920671	1			T1	32935		T11	112		T16	28
all_values[15]	auto[1]	auto[0]	auto[1]	71280	1			T1	720		T12	2		T16	4
all_values[15]	auto[1]	auto[1]	auto[1]	70920	1			T1	770		T16	2		T17	1
all_values[16]	auto[0]	auto[0]	auto[0]	2497526	1			T23	490		T24	152		T1	12678
all_values[16]	auto[0]	auto[0]	auto[1]	4892429	1			T1	31885		T11	152		T12	6
all_values[16]	auto[0]	auto[1]	auto[0]	531460	1			T1	3619		T11	7		T12	7
all_values[16]	auto[0]	auto[1]	auto[1]	4899379	1			T1	32324		T11	104		T12	4
all_values[16]	auto[1]	auto[0]	auto[1]	71573	1			T1	769		T12	1		T16	5
all_values[16]	auto[1]	auto[1]	auto[1]	70762	1			T1	693		T17	2		T127	2
all_values[17]	auto[0]	auto[0]	auto[0]	2503877	1			T23	490		T24	152		T1	12456
all_values[17]	auto[0]	auto[0]	auto[1]	4895033	1			T1	34163		T11	118		T12	6
all_values[17]	auto[0]	auto[1]	auto[0]	537717	1			T1	3444		T11	20		T16	21
all_values[17]	auto[0]	auto[1]	auto[1]	4883819	1			T1	30496		T11	116		T16	22
all_values[17]	auto[1]	auto[0]	auto[1]	71828	1			T1	694		T12	1		T16	6
all_values[17]	auto[1]	auto[1]	auto[1]	70855	1			T1	715		T16	5		T127	3
all_values[18]	auto[0]	auto[0]	auto[0]	2503745	1			T23	490		T24	152		T1	12221
all_values[18]	auto[0]	auto[0]	auto[1]	4893986	1			T1	32998		T11	168		T12	9
all_values[18]	auto[0]	auto[1]	auto[0]	535171	1			T1	3344		T11	4		T16	22
all_values[18]	auto[0]	auto[1]	auto[1]	4887813	1			T1	31911		T11	77		T16	16
all_values[18]	auto[1]	auto[0]	auto[1]	71649	1			T1	794		T16	7		T17	1
all_values[18]	auto[1]	auto[1]	auto[1]	70765	1			T1	700		T16	1		T127	3
all_values[19]	auto[0]	auto[0]	auto[0]	2503874	1			T23	490		T24	152		T1	12163
all_values[19]	auto[0]	auto[0]	auto[1]	4901264	1			T1	32714		T11	119		T12	2
all_values[19]	auto[0]	auto[1]	auto[0]	536754	1			T1	4041		T11	34		T12	11
all_values[19]	auto[0]	auto[1]	auto[1]	4878532	1			T1	31614		T11	115		T16	20
all_values[19]	auto[1]	auto[0]	auto[1]	71460	1			T1	762		T12	2		T16	1
all_values[19]	auto[1]	auto[1]	auto[1]	71245	1			T1	674		T16	2		T17	3
all_values[20]	auto[0]	auto[0]	auto[0]	2502301	1			T23	490		T24	152		T1	12347
all_values[20]	auto[0]	auto[0]	auto[1]	4916872	1			T1	33183		T11	166		T12	5
all_values[20]	auto[0]	auto[1]	auto[0]	524293	1			T1	3708		T11	23		T12	2
all_values[20]	auto[0]	auto[1]	auto[1]	4877388	1			T1	31291		T11	69		T12	4
all_values[20]	auto[1]	auto[0]	auto[1]	71731	1			T1	735		T12	2		T16	6
all_values[20]	auto[1]	auto[1]	auto[1]	70544	1			T1	704		T16	2		T17	1
all_values[21]	auto[0]	auto[0]	auto[0]	2506624	1			T23	490		T24	152		T1	12337
all_values[21]	auto[0]	auto[0]	auto[1]	4880094	1			T1	32391		T11	130		T12	1
all_values[21]	auto[0]	auto[1]	auto[0]	541692	1			T1	3910		T11	40		T12	11
all_values[21]	auto[0]	auto[1]	auto[1]	4892529	1			T1	31815		T11	83		T16	10
all_values[21]	auto[1]	auto[0]	auto[1]	71349	1			T1	734		T16	7		T17	1
all_values[21]	auto[1]	auto[1]	auto[1]	70841	1			T1	781		T127	3		T128	35
all_values[22]	auto[0]	auto[0]	auto[0]	2507649	1			T23	490		T24	152		T1	12164
all_values[22]	auto[0]	auto[0]	auto[1]	4891649	1			T1	30755		T11	145		T16	21
all_values[22]	auto[0]	auto[1]	auto[0]	533901	1			T1	3779		T11	23		T12	11
all_values[22]	auto[0]	auto[1]	auto[1]	4886938	1			T1	33743		T11	59		T16	31
all_values[22]	auto[1]	auto[0]	auto[1]	71759	1			T1	750		T16	4		T17	3
all_values[22]	auto[1]	auto[1]	auto[1]	71233	1			T1	777		T16	4		T127	4
all_values[23]	auto[0]	auto[0]	auto[0]	2502940	1			T23	490		T24	152		T1	12072
all_values[23]	auto[0]	auto[0]	auto[1]	4928824	1			T1	32887		T11	111		T12	13
all_values[23]	auto[0]	auto[1]	auto[0]	528664	1			T1	3553		T11	34		T12	2
all_values[23]	auto[0]	auto[1]	auto[1]	4860221	1			T1	32015		T11	86		T12	3
all_values[23]	auto[1]	auto[0]	auto[1]	71424	1			T1	715		T16	6		T17	1
all_values[23]	auto[1]	auto[1]	auto[1]	71056	1			T1	726		T16	4		T127	2
all_values[24]	auto[0]	auto[0]	auto[0]	2500953	1			T23	490		T24	152		T1	12586
all_values[24]	auto[0]	auto[0]	auto[1]	4869769	1			T1	33237		T11	100		T12	8
all_values[24]	auto[0]	auto[1]	auto[0]	532958	1			T1	3500		T11	68		T12	11
all_values[24]	auto[0]	auto[1]	auto[1]	4916685	1			T1	31097		T11	95		T16	4
all_values[24]	auto[1]	auto[0]	auto[1]	71675	1			T1	793		T12	1		T16	6
all_values[24]	auto[1]	auto[1]	auto[1]	71089	1			T1	755		T16	1		T17	3
all_values[25]	auto[0]	auto[0]	auto[0]	2506100	1			T23	490		T24	152		T1	12126
all_values[25]	auto[0]	auto[0]	auto[1]	4905910	1			T1	31635		T11	121		T12	10
all_values[25]	auto[0]	auto[1]	auto[0]	531092	1			T1	4062		T11	23		T16	8
all_values[25]	auto[0]	auto[1]	auto[1]	4877479	1			T1	32672		T11	107		T12	6
all_values[25]	auto[1]	auto[0]	auto[1]	71304	1			T1	734		T12	1		T16	3
all_values[25]	auto[1]	auto[1]	auto[1]	71244	1			T1	739		T16	1		T17	3
all_values[26]	auto[0]	auto[0]	auto[0]	2497462	1			T23	490		T24	152		T1	12112
all_values[26]	auto[0]	auto[0]	auto[1]	4932095	1			T1	32470		T11	107		T12	10
all_values[26]	auto[0]	auto[1]	auto[0]	528685	1			T1	3692		T11	42		T12	3
all_values[26]	auto[0]	auto[1]	auto[1]	4862489	1			T1	32225		T11	102		T12	2
all_values[26]	auto[1]	auto[0]	auto[1]	71068	1			T1	739		T12	1		T16	4
all_values[26]	auto[1]	auto[1]	auto[1]	71330	1			T1	730		T16	4		T17	3
all_values[27]	auto[0]	auto[0]	auto[0]	2505412	1			T23	490		T24	152		T1	12397
all_values[27]	auto[0]	auto[0]	auto[1]	4881833	1			T1	33287		T11	145		T12	5
all_values[27]	auto[0]	auto[1]	auto[0]	525890	1			T1	3652		T11	26		T12	11
all_values[27]	auto[0]	auto[1]	auto[1]	4907609	1			T1	31176		T11	90		T16	5
all_values[27]	auto[1]	auto[0]	auto[1]	71491	1			T1	686		T12	2		T16	7
all_values[27]	auto[1]	auto[1]	auto[1]	70894	1			T1	770		T127	2		T128	54
all_values[28]	auto[0]	auto[0]	auto[0]	2500966	1			T23	490		T24	152		T1	12310
all_values[28]	auto[0]	auto[0]	auto[1]	4902669	1			T1	32241		T11	157		T12	4
all_values[28]	auto[0]	auto[1]	auto[0]	532630	1			T1	3735		T11	13		T16	9
all_values[28]	auto[0]	auto[1]	auto[1]	4884372	1			T1	32211		T11	79		T12	6
all_values[28]	auto[1]	auto[0]	auto[1]	71379	1			T1	701		T16	3		T127	4
all_values[28]	auto[1]	auto[1]	auto[1]	71113	1			T1	770		T16	1		T17	2
all_values[29]	auto[0]	auto[0]	auto[0]	2504860	1			T23	490		T24	152		T1	12646
all_values[29]	auto[0]	auto[0]	auto[1]	4891636	1			T1	32324		T11	81		T12	12
all_values[29]	auto[0]	auto[1]	auto[0]	532539	1			T1	3914		T11	48		T17	1
all_values[29]	auto[0]	auto[1]	auto[1]	4891585	1			T1	31662		T11	140		T12	6
all_values[29]	auto[1]	auto[0]	auto[1]	71139	1			T1	763		T16	11		T17	2
all_values[29]	auto[1]	auto[1]	auto[1]	71370	1			T1	659		T16	1		T17	2
all_values[30]	auto[0]	auto[0]	auto[0]	2513784	1			T23	490		T24	152		T1	12224
all_values[30]	auto[0]	auto[0]	auto[1]	4876920	1			T1	33250		T11	90		T12	3
all_values[30]	auto[0]	auto[1]	auto[0]	529186	1			T1	3496		T11	23		T12	2
all_values[30]	auto[0]	auto[1]	auto[1]	4900420	1			T1	31496		T11	137		T12	9
all_values[30]	auto[1]	auto[0]	auto[1]	71669	1			T1	797		T12	1		T16	5
all_values[30]	auto[1]	auto[1]	auto[1]	71150	1			T1	705		T17	2		T127	1
all_values[31]	auto[0]	auto[0]	auto[0]	2500832	1			T23	490		T24	152		T1	12246
all_values[31]	auto[0]	auto[0]	auto[1]	4904038	1			T1	32645		T11	166		T12	9
all_values[31]	auto[0]	auto[1]	auto[0]	531343	1			T1	3868		T11	6		T12	2
all_values[31]	auto[0]	auto[1]	auto[1]	4884455	1			T1	31781		T11	85		T12	9
all_values[31]	auto[1]	auto[0]	auto[1]	71249	1			T1	739		T16	7		T17	1
all_values[31]	auto[1]	auto[1]	auto[1]	71212	1			T1	689		T16	2		T17	2

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal