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Group Instance : masked_out_upper_cov_obj_pin21
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance masked_out_upper_cov_obj_pin21

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 4 0 4 100.00


Variables for Group Instance masked_out_upper_cov_obj_pin21
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_transitions 2 0 2 100.00 100 1 1 0
cp_value 2 0 2 100.00 100 1 1 2


Group Instance : masked_out_upper_cov_obj_pin22
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance masked_out_upper_cov_obj_pin22

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 4 0 4 100.00


Variables for Group Instance masked_out_upper_cov_obj_pin22
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_transitions 2 0 2 100.00 100 1 1 0
cp_value 2 0 2 100.00 100 1 1 2


Group Instance : masked_out_upper_cov_obj_pin23
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance masked_out_upper_cov_obj_pin23

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 4 0 4 100.00


Variables for Group Instance masked_out_upper_cov_obj_pin23
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_transitions 2 0 2 100.00 100 1 1 0
cp_value 2 0 2 100.00 100 1 1 2


Group Instance : masked_out_upper_cov_obj_pin24
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance masked_out_upper_cov_obj_pin24

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 4 0 4 100.00


Variables for Group Instance masked_out_upper_cov_obj_pin24
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_transitions 2 0 2 100.00 100 1 1 0
cp_value 2 0 2 100.00 100 1 1 2


Group Instance : masked_out_upper_cov_obj_pin25
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance masked_out_upper_cov_obj_pin25

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 4 0 4 100.00


Variables for Group Instance masked_out_upper_cov_obj_pin25
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_transitions 2 0 2 100.00 100 1 1 0
cp_value 2 0 2 100.00 100 1 1 2


Group Instance : masked_out_upper_cov_obj_pin26
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance masked_out_upper_cov_obj_pin26

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 4 0 4 100.00


Variables for Group Instance masked_out_upper_cov_obj_pin26
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_transitions 2 0 2 100.00 100 1 1 0
cp_value 2 0 2 100.00 100 1 1 2


Group Instance : masked_out_upper_cov_obj_pin27
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance masked_out_upper_cov_obj_pin27

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 4 0 4 100.00


Variables for Group Instance masked_out_upper_cov_obj_pin27
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_transitions 2 0 2 100.00 100 1 1 0
cp_value 2 0 2 100.00 100 1 1 2


Group Instance : masked_out_upper_cov_obj_pin28
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance masked_out_upper_cov_obj_pin28

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 4 0 4 100.00


Variables for Group Instance masked_out_upper_cov_obj_pin28
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_transitions 2 0 2 100.00 100 1 1 0
cp_value 2 0 2 100.00 100 1 1 2


Group Instance : masked_out_upper_cov_obj_pin29
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance masked_out_upper_cov_obj_pin29

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 4 0 4 100.00


Variables for Group Instance masked_out_upper_cov_obj_pin29
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_transitions 2 0 2 100.00 100 1 1 0
cp_value 2 0 2 100.00 100 1 1 2


Group Instance : masked_out_upper_cov_obj_pin3
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance masked_out_upper_cov_obj_pin3

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 4 0 4 100.00


Variables for Group Instance masked_out_upper_cov_obj_pin3
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_transitions 2 0 2 100.00 100 1 1 0
cp_value 2 0 2 100.00 100 1 1 2


Group Instance : masked_out_upper_cov_obj_pin30
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance masked_out_upper_cov_obj_pin30

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 4 0 4 100.00


Variables for Group Instance masked_out_upper_cov_obj_pin30
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_transitions 2 0 2 100.00 100 1 1 0
cp_value 2 0 2 100.00 100 1 1 2


Group Instance : masked_out_upper_cov_obj_pin31
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance masked_out_upper_cov_obj_pin31

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 4 0 4 100.00


Variables for Group Instance masked_out_upper_cov_obj_pin31
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_transitions 2 0 2 100.00 100 1 1 0
cp_value 2 0 2 100.00 100 1 1 2


Group Instance : masked_out_upper_cov_obj_pin4
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance masked_out_upper_cov_obj_pin4

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 4 0 4 100.00


Variables for Group Instance masked_out_upper_cov_obj_pin4
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_transitions 2 0 2 100.00 100 1 1 0
cp_value 2 0 2 100.00 100 1 1 2


Group Instance : masked_out_upper_cov_obj_pin5
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance masked_out_upper_cov_obj_pin5

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 4 0 4 100.00


Variables for Group Instance masked_out_upper_cov_obj_pin5
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_transitions 2 0 2 100.00 100 1 1 0
cp_value 2 0 2 100.00 100 1 1 2


Group Instance : masked_out_upper_cov_obj_pin6
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance masked_out_upper_cov_obj_pin6

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 4 0 4 100.00


Variables for Group Instance masked_out_upper_cov_obj_pin6
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_transitions 2 0 2 100.00 100 1 1 0
cp_value 2 0 2 100.00 100 1 1 2


Group Instance : masked_out_upper_cov_obj_pin7
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance masked_out_upper_cov_obj_pin7

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 4 0 4 100.00


Variables for Group Instance masked_out_upper_cov_obj_pin7
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_transitions 2 0 2 100.00 100 1 1 0
cp_value 2 0 2 100.00 100 1 1 2


Group Instance : masked_out_upper_cov_obj_pin8
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance masked_out_upper_cov_obj_pin8

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 4 0 4 100.00


Variables for Group Instance masked_out_upper_cov_obj_pin8
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_transitions 2 0 2 100.00 100 1 1 0
cp_value 2 0 2 100.00 100 1 1 2


Group Instance : masked_out_upper_cov_obj_pin9
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance masked_out_upper_cov_obj_pin9

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 4 0 4 100.00


Variables for Group Instance masked_out_upper_cov_obj_pin9
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_transitions 2 0 2 100.00 100 1 1 0
cp_value 2 0 2 100.00 100 1 1 2


Group Instance : uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::PutFullData_mask_not_match_size
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::PutFullData_mask_not_match_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 4 0 4 100.00


Variables for Group Instance uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::PutFullData_mask_not_match_size
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_transitions 2 0 2 100.00 100 1 1 0
cp_value 2 0 2 100.00 100 1 1 2


Group Instance : uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::addr_not_align_mask
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::addr_not_align_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 4 0 4 100.00


Variables for Group Instance uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::addr_not_align_mask
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_transitions 2 0 2 100.00 100 1 1 0
cp_value 2 0 2 100.00 100 1 1 2


Group Instance : uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::addr_not_align_size
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::addr_not_align_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 4 0 4 100.00


Variables for Group Instance uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::addr_not_align_size
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_transitions 2 0 2 100.00 100 1 1 0
cp_value 2 0 2 100.00 100 1 1 2


Group Instance : uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::invalid_a_opcode
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::invalid_a_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 4 0 4 100.00


Variables for Group Instance uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::invalid_a_opcode
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_transitions 2 0 2 100.00 100 1 1 0
cp_value 2 0 2 100.00 100 1 1 2


Group Instance : uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::mask_not_in_enabled_lanes
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::mask_not_in_enabled_lanes

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 4 0 4 100.00


Variables for Group Instance uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::mask_not_in_enabled_lanes
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_transitions 2 0 2 100.00 100 1 1 0
cp_value 2 0 2 100.00 100 1 1 2


Group Instance : uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::size_over_max
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::size_over_max

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 4 0 4 100.00


Variables for Group Instance uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::size_over_max
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_transitions 2 0 2 100.00 100 1 1 0
cp_value 2 0 2 100.00 100 1 1 2

Go back
Group Instances:
masked_out_upper_cov_obj_pin21
masked_out_upper_cov_obj_pin22
masked_out_upper_cov_obj_pin23
masked_out_upper_cov_obj_pin24
masked_out_upper_cov_obj_pin25
masked_out_upper_cov_obj_pin26
masked_out_upper_cov_obj_pin27
masked_out_upper_cov_obj_pin28
masked_out_upper_cov_obj_pin29
masked_out_upper_cov_obj_pin3
masked_out_upper_cov_obj_pin30
masked_out_upper_cov_obj_pin31
masked_out_upper_cov_obj_pin4
masked_out_upper_cov_obj_pin5
masked_out_upper_cov_obj_pin6
masked_out_upper_cov_obj_pin7
masked_out_upper_cov_obj_pin8
masked_out_upper_cov_obj_pin9
uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::PutFullData_mask_not_match_size
uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::addr_not_align_mask
uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::addr_not_align_size
uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::invalid_a_opcode
uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::mask_not_in_enabled_lanes
uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::size_over_max

Summary for Variable cp_transitions

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_transitions

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
falling 96102 1 T24 4 T1 893 T12 1
rising 96082 1 T24 5 T1 892 T16 4


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 191929 1 T24 9 T1 1750 T12 1
auto[1] 191466 1 T24 8 T1 1766 T12 1


Summary for Variable cp_transitions

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_transitions

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
falling 95640 1 T24 4 T1 887 T16 3
rising 95644 1 T24 4 T1 887 T16 4


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 191493 1 T24 8 T1 1815 T16 7
auto[1] 191902 1 T24 9 T1 1701 T12 2


Summary for Variable cp_transitions

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_transitions

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
falling 95630 1 T24 4 T1 897 T16 2
rising 95636 1 T24 4 T1 896 T16 3


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 191676 1 T24 7 T1 1758 T16 10
auto[1] 191719 1 T24 10 T1 1758 T12 2


Summary for Variable cp_transitions

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_transitions

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
falling 95933 1 T24 3 T1 874 T16 2
rising 95932 1 T24 3 T1 875 T12 1


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 191536 1 T24 14 T1 1724 T12 1
auto[1] 191859 1 T24 3 T1 1792 T12 1


Summary for Variable cp_transitions

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_transitions

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
falling 95636 1 T24 3 T1 868 T16 4
rising 95635 1 T24 2 T1 867 T12 1


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 191844 1 T24 10 T1 1806 T12 1
auto[1] 191551 1 T24 7 T1 1710 T12 1


Summary for Variable cp_transitions

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_transitions

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
falling 95524 1 T24 3 T1 868 T16 2
rising 95522 1 T24 4 T1 869 T16 1


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 191251 1 T24 10 T1 1770 T16 4
auto[1] 192144 1 T24 7 T1 1746 T12 2


Summary for Variable cp_transitions

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_transitions

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
falling 95642 1 T24 6 T1 885 T12 1
rising 95624 1 T24 6 T1 886 T16 3


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 191337 1 T24 7 T1 1765 T12 1
auto[1] 192058 1 T24 10 T1 1751 T12 1


Summary for Variable cp_transitions

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_transitions

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
falling 95722 1 T24 3 T1 856 T16 3
rising 95720 1 T24 4 T1 856 T16 2


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 191807 1 T24 11 T1 1800 T16 8
auto[1] 191588 1 T24 6 T1 1716 T12 2


Summary for Variable cp_transitions

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_transitions

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
falling 95976 1 T24 5 T1 898 T12 1
rising 95972 1 T24 4 T1 897 T16 4


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 191581 1 T24 8 T1 1734 T12 1
auto[1] 191814 1 T24 9 T1 1782 T12 1


Summary for Variable cp_transitions

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_transitions

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
falling 95695 1 T24 4 T1 883 T16 4
rising 95686 1 T24 5 T1 882 T16 4


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 191297 1 T24 10 T1 1711 T16 9
auto[1] 192098 1 T24 7 T1 1805 T12 2


Summary for Variable cp_transitions

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_transitions

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
falling 95713 1 T24 5 T1 899 T16 2
rising 95728 1 T24 5 T1 899 T16 3


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 191871 1 T24 5 T1 1752 T12 2
auto[1] 191524 1 T24 12 T1 1764 T16 5


Summary for Variable cp_transitions

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_transitions

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
falling 95919 1 T24 4 T1 858 T12 1
rising 95929 1 T24 3 T1 857 T16 4


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 191712 1 T24 6 T1 1732 T12 1
auto[1] 191683 1 T24 11 T1 1784 T12 1


Summary for Variable cp_transitions

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_transitions

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
falling 95725 1 T24 4 T1 879 T16 4
rising 95741 1 T24 3 T1 880 T16 3


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 192137 1 T24 4 T1 1710 T12 2
auto[1] 191258 1 T24 13 T1 1806 T16 9


Summary for Variable cp_transitions

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_transitions

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
falling 95820 1 T24 4 T1 856 T12 1
rising 95827 1 T24 4 T1 855 T16 3


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 191892 1 T24 9 T1 1783 T12 1
auto[1] 191503 1 T24 8 T1 1733 T12 1


Summary for Variable cp_transitions

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_transitions

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
falling 95994 1 T24 6 T1 852 T16 3
rising 95996 1 T24 6 T1 851 T16 3


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 191330 1 T24 9 T1 1716 T12 2
auto[1] 192065 1 T24 8 T1 1800 T16 9


Summary for Variable cp_transitions

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_transitions

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
falling 95698 1 T24 3 T1 878 T16 2
rising 95685 1 T24 3 T1 878 T16 2


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 191771 1 T24 7 T1 1758 T16 8
auto[1] 191624 1 T24 10 T1 1758 T12 2


Summary for Variable cp_transitions

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_transitions

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
falling 95771 1 T24 3 T1 877 T16 4
rising 95780 1 T24 3 T1 876 T16 3


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 191969 1 T24 13 T1 1752 T16 10
auto[1] 191426 1 T24 4 T1 1764 T12 2


Summary for Variable cp_transitions

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_transitions

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
falling 95848 1 T24 3 T1 891 T16 3
rising 95838 1 T24 3 T1 890 T16 4


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 191509 1 T24 14 T1 1741 T16 6
auto[1] 191886 1 T24 3 T1 1775 T12 2


Summary for Variable cp_transitions

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_transitions

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
falling 711667 1 T25 3957 T26 42770 T27 11928
rising 711661 1 T25 3957 T26 42769 T27 11929


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 3577853 1 T25 20033 T26 214831 T27 58723
auto[1] 937526 1 T25 5231 T26 56265 T27 15746


Summary for Variable cp_transitions

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_transitions

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
falling 893319 1 T25 5092 T26 53555 T27 14747
rising 893334 1 T25 5092 T26 53555 T27 14746


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 3277529 1 T25 18258 T26 196945 T27 54001
auto[1] 1237850 1 T25 7006 T26 74151 T27 20468


Summary for Variable cp_transitions

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_transitions

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
falling 893319 1 T25 5092 T26 53555 T27 14747
rising 893334 1 T25 5092 T26 53555 T27 14746


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 3277529 1 T25 18258 T26 196945 T27 54001
auto[1] 1237850 1 T25 7006 T26 74151 T27 20468


Summary for Variable cp_transitions

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_transitions

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
falling 896428 1 T25 4974 T26 53786 T27 14753
rising 896431 1 T25 4975 T26 53786 T27 14753


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 3219623 1 T25 18055 T26 193261 T27 53220
auto[1] 1295756 1 T25 7209 T26 77835 T27 21249


Summary for Variable cp_transitions

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_transitions

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
falling 849931 1 T25 4704 T26 50893 T27 14047
rising 849915 1 T25 4704 T26 50893 T27 14047


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 3340886 1 T25 18684 T26 201103 T27 55109
auto[1] 1174493 1 T25 6580 T26 69993 T27 19360


Summary for Variable cp_transitions

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_transitions

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
falling 781413 1 T25 4405 T26 46901 T27 12818
rising 781419 1 T25 4405 T26 46902 T27 12818


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 3505054 1 T25 19607 T26 210271 T27 57790
auto[1] 1010325 1 T25 5657 T26 60825 T27 16679

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%