Unified Coverage Report :: Group :: gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

Group : gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_gpio_env_0.1/gpio_env_cov.sv

---

Summary for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	192	0	192	100.00

Variables for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_pin	32	0	32	100.00	100	1	1	0
data_in	2	0	2	100.00	100	1	1	2
data_oe	2	0	2	100.00	100	1	1	2
data_out	2	0	2	100.00	100	1	1	2

Crosses for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_cross_all	192	0	192	100.00	100	1	1	0

Summary for Variable cp_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	12805574	1			T23	490		T24	280		T1	80866
bins_for_gpio_bits[1]	12805574	1			T23	490		T24	280		T1	80866
bins_for_gpio_bits[2]	12805574	1			T23	490		T24	280		T1	80866
bins_for_gpio_bits[3]	12805574	1			T23	490		T24	280		T1	80866
bins_for_gpio_bits[4]	12805574	1			T23	490		T24	280		T1	80866
bins_for_gpio_bits[5]	12805574	1			T23	490		T24	280		T1	80866
bins_for_gpio_bits[6]	12805574	1			T23	490		T24	280		T1	80866
bins_for_gpio_bits[7]	12805574	1			T23	490		T24	280		T1	80866
bins_for_gpio_bits[8]	12805574	1			T23	490		T24	280		T1	80866
bins_for_gpio_bits[9]	12805574	1			T23	490		T24	280		T1	80866
bins_for_gpio_bits[10]	12805574	1			T23	490		T24	280		T1	80866
bins_for_gpio_bits[11]	12805574	1			T23	490		T24	280		T1	80866
bins_for_gpio_bits[12]	12805574	1			T23	490		T24	280		T1	80866
bins_for_gpio_bits[13]	12805574	1			T23	490		T24	280		T1	80866
bins_for_gpio_bits[14]	12805574	1			T23	490		T24	280		T1	80866
bins_for_gpio_bits[15]	12805574	1			T23	490		T24	280		T1	80866
bins_for_gpio_bits[16]	12805574	1			T23	490		T24	280		T1	80866
bins_for_gpio_bits[17]	12805574	1			T23	490		T24	280		T1	80866
bins_for_gpio_bits[18]	12805574	1			T23	490		T24	280		T1	80866
bins_for_gpio_bits[19]	12805574	1			T23	490		T24	280		T1	80866
bins_for_gpio_bits[20]	12805574	1			T23	490		T24	280		T1	80866
bins_for_gpio_bits[21]	12805574	1			T23	490		T24	280		T1	80866
bins_for_gpio_bits[22]	12805574	1			T23	490		T24	280		T1	80866
bins_for_gpio_bits[23]	12805574	1			T23	490		T24	280		T1	80866
bins_for_gpio_bits[24]	12805574	1			T23	490		T24	280		T1	80866
bins_for_gpio_bits[25]	12805574	1			T23	490		T24	280		T1	80866
bins_for_gpio_bits[26]	12805574	1			T23	490		T24	280		T1	80866
bins_for_gpio_bits[27]	12805574	1			T23	490		T24	280		T1	80866
bins_for_gpio_bits[28]	12805574	1			T23	490		T24	280		T1	80866
bins_for_gpio_bits[29]	12805574	1			T23	490		T24	280		T1	80866
bins_for_gpio_bits[30]	12805574	1			T23	490		T24	280		T1	80866
bins_for_gpio_bits[31]	12805574	1			T23	490		T24	280		T1	80866

---

Summary for Variable data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

240521230

1

T23

8021

T24

7072

T1

175771

auto[1]

169257138

1

T23

7659

T24

1888

T1

829995

---

Summary for Variable data_oe

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_oe

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

327833706

1

T23

15680

T24

6519

T1

190496

auto[1]

81944662

1

T24

2441

T1

682743

T12

196

---

Summary for Variable data_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_out

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

303701929

1

T23

15680

T24

4889

T1

172614

auto[1]

106076439

1

T24

4071

T1

861565

T12

564

---

Summary for Cross cp_cross_all

Samples crossed: cp_pin data_out data_oe data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	192	0	192	100.00
Automatically Generated Cross Bins	192	0	192	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cp_cross_all

Bins

cp_pin	data_out	data_oe	data_in	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	auto[0]	auto[0]	auto[0]	4671264	1			T23	301		T24	119		T1	28850
bins_for_gpio_bits[0]	auto[0]	auto[0]	auto[1]	3536719	1			T23	189		T24	11		T1	14258
bins_for_gpio_bits[0]	auto[0]	auto[1]	auto[0]	1291248	1			T24	11		T1	10981		T15	80
bins_for_gpio_bits[0]	auto[1]	auto[0]	auto[0]	1560678	1			T24	93		T1	15313		T12	4
bins_for_gpio_bits[0]	auto[1]	auto[0]	auto[1]	471341	1			T24	14		T1	1054		T12	2
bins_for_gpio_bits[0]	auto[1]	auto[1]	auto[1]	1274324	1			T24	32		T1	10410		T12	7
bins_for_gpio_bits[1]	auto[0]	auto[0]	auto[0]	4673495	1			T23	280		T24	88		T1	28963
bins_for_gpio_bits[1]	auto[0]	auto[0]	auto[1]	3530187	1			T23	210		T24	18		T1	14298
bins_for_gpio_bits[1]	auto[0]	auto[1]	auto[0]	1289545	1			T24	52		T1	10869		T15	106
bins_for_gpio_bits[1]	auto[1]	auto[0]	auto[0]	1560440	1			T24	54		T1	15404		T15	90
bins_for_gpio_bits[1]	auto[1]	auto[0]	auto[1]	473907	1			T24	10		T1	934		T12	6
bins_for_gpio_bits[1]	auto[1]	auto[1]	auto[1]	1278000	1			T24	58		T1	10398		T12	17
bins_for_gpio_bits[2]	auto[0]	auto[0]	auto[0]	4662125	1			T23	258		T24	72		T1	29006
bins_for_gpio_bits[2]	auto[0]	auto[0]	auto[1]	3536594	1			T23	232		T24	8		T1	14424
bins_for_gpio_bits[2]	auto[0]	auto[1]	auto[0]	1289503	1			T24	42		T1	10890		T15	72
bins_for_gpio_bits[2]	auto[1]	auto[0]	auto[0]	1566152	1			T24	83		T1	15544		T15	108
bins_for_gpio_bits[2]	auto[1]	auto[0]	auto[1]	472511	1			T24	16		T1	892		T16	9
bins_for_gpio_bits[2]	auto[1]	auto[1]	auto[1]	1278689	1			T24	59		T1	10110		T15	148
bins_for_gpio_bits[3]	auto[0]	auto[0]	auto[0]	4662676	1			T23	224		T24	143		T1	29194
bins_for_gpio_bits[3]	auto[0]	auto[0]	auto[1]	3541765	1			T23	266		T24	14		T1	14267
bins_for_gpio_bits[3]	auto[0]	auto[1]	auto[0]	1286713	1			T24	52		T1	10785		T15	112
bins_for_gpio_bits[3]	auto[1]	auto[0]	auto[0]	1566665	1			T24	47		T1	15243		T12	13
bins_for_gpio_bits[3]	auto[1]	auto[0]	auto[1]	471650	1			T24	9		T1	955		T12	3
bins_for_gpio_bits[3]	auto[1]	auto[1]	auto[1]	1276105	1			T24	15		T1	10422		T12	9
bins_for_gpio_bits[4]	auto[0]	auto[0]	auto[0]	4657811	1			T23	289		T24	104		T1	29175
bins_for_gpio_bits[4]	auto[0]	auto[0]	auto[1]	3539957	1			T23	201		T24	12		T1	14427
bins_for_gpio_bits[4]	auto[0]	auto[1]	auto[0]	1289642	1			T24	38		T1	11079		T15	95
bins_for_gpio_bits[4]	auto[1]	auto[0]	auto[0]	1567367	1			T24	79		T1	14478		T15	102
bins_for_gpio_bits[4]	auto[1]	auto[0]	auto[1]	473074	1			T24	9		T1	900		T12	2
bins_for_gpio_bits[4]	auto[1]	auto[1]	auto[1]	1277723	1			T24	38		T1	10807		T12	1
bins_for_gpio_bits[5]	auto[0]	auto[0]	auto[0]	4660457	1			T23	229		T24	92		T1	28554
bins_for_gpio_bits[5]	auto[0]	auto[0]	auto[1]	3541517	1			T23	261		T24	7		T1	14459
bins_for_gpio_bits[5]	auto[0]	auto[1]	auto[0]	1290139	1			T24	45		T1	11045		T15	94
bins_for_gpio_bits[5]	auto[1]	auto[0]	auto[0]	1561535	1			T24	80		T1	15023		T12	8
bins_for_gpio_bits[5]	auto[1]	auto[0]	auto[1]	473286	1			T24	20		T1	911		T12	3
bins_for_gpio_bits[5]	auto[1]	auto[1]	auto[1]	1278640	1			T24	36		T1	10874		T12	12
bins_for_gpio_bits[6]	auto[0]	auto[0]	auto[0]	4660360	1			T23	255		T24	53		T1	29097
bins_for_gpio_bits[6]	auto[0]	auto[0]	auto[1]	3540879	1			T23	235		T24	8		T1	14422
bins_for_gpio_bits[6]	auto[0]	auto[1]	auto[0]	1288393	1			T24	43		T1	10452		T15	80
bins_for_gpio_bits[6]	auto[1]	auto[0]	auto[0]	1565091	1			T24	127		T1	15638		T12	8
bins_for_gpio_bits[6]	auto[1]	auto[0]	auto[1]	472089	1			T24	6		T1	993		T12	3
bins_for_gpio_bits[6]	auto[1]	auto[1]	auto[1]	1278762	1			T24	43		T1	10264		T12	3
bins_for_gpio_bits[7]	auto[0]	auto[0]	auto[0]	4657773	1			T23	260		T24	88		T1	28562
bins_for_gpio_bits[7]	auto[0]	auto[0]	auto[1]	3545747	1			T23	230		T24	14		T1	14329
bins_for_gpio_bits[7]	auto[0]	auto[1]	auto[0]	1288822	1			T24	56		T1	10677		T15	109
bins_for_gpio_bits[7]	auto[1]	auto[0]	auto[0]	1562166	1			T24	85		T1	15550		T12	4
bins_for_gpio_bits[7]	auto[1]	auto[0]	auto[1]	470453	1			T24	10		T1	989		T12	2
bins_for_gpio_bits[7]	auto[1]	auto[1]	auto[1]	1280613	1			T24	27		T1	10759		T12	13
bins_for_gpio_bits[8]	auto[0]	auto[0]	auto[0]	4656611	1			T23	284		T24	114		T1	28765
bins_for_gpio_bits[8]	auto[0]	auto[0]	auto[1]	3549213	1			T23	206		T24	14		T1	14163
bins_for_gpio_bits[8]	auto[0]	auto[1]	auto[0]	1288568	1			T24	58		T1	10651		T15	90
bins_for_gpio_bits[8]	auto[1]	auto[0]	auto[0]	1561370	1			T24	47		T1	15277		T12	18
bins_for_gpio_bits[8]	auto[1]	auto[0]	auto[1]	471915	1			T24	12		T1	963		T16	16
bins_for_gpio_bits[8]	auto[1]	auto[1]	auto[1]	1277897	1			T24	35		T1	11047		T12	2
bins_for_gpio_bits[9]	auto[0]	auto[0]	auto[0]	4663490	1			T23	218		T24	144		T1	28767
bins_for_gpio_bits[9]	auto[0]	auto[0]	auto[1]	3540528	1			T23	272		T24	26		T1	14273
bins_for_gpio_bits[9]	auto[0]	auto[1]	auto[0]	1289518	1			T24	48		T1	10535		T15	96
bins_for_gpio_bits[9]	auto[1]	auto[0]	auto[0]	1562392	1			T24	37		T1	15282		T12	10
bins_for_gpio_bits[9]	auto[1]	auto[0]	auto[1]	474504	1			T24	3		T1	1035		T12	3
bins_for_gpio_bits[9]	auto[1]	auto[1]	auto[1]	1275142	1			T24	22		T1	10974		T12	13
bins_for_gpio_bits[10]	auto[0]	auto[0]	auto[0]	4658493	1			T23	275		T24	82		T1	29085
bins_for_gpio_bits[10]	auto[0]	auto[0]	auto[1]	3540676	1			T23	215		T24	13		T1	14331
bins_for_gpio_bits[10]	auto[0]	auto[1]	auto[0]	1287013	1			T24	62		T1	10733		T15	91
bins_for_gpio_bits[10]	auto[1]	auto[0]	auto[0]	1563463	1			T24	65		T1	15227		T12	18
bins_for_gpio_bits[10]	auto[1]	auto[0]	auto[1]	475094	1			T24	9		T1	935		T16	17
bins_for_gpio_bits[10]	auto[1]	auto[1]	auto[1]	1280835	1			T24	49		T1	10555		T12	2
bins_for_gpio_bits[11]	auto[0]	auto[0]	auto[0]	4671715	1			T23	234		T24	83		T1	29321
bins_for_gpio_bits[11]	auto[0]	auto[0]	auto[1]	3531526	1			T23	256		T24	13		T1	14164
bins_for_gpio_bits[11]	auto[0]	auto[1]	auto[0]	1283509	1			T24	38		T1	10502		T15	91
bins_for_gpio_bits[11]	auto[1]	auto[0]	auto[0]	1565847	1			T24	92		T1	15438		T12	12
bins_for_gpio_bits[11]	auto[1]	auto[0]	auto[1]	474126	1			T24	14		T1	1041		T12	3
bins_for_gpio_bits[11]	auto[1]	auto[1]	auto[1]	1278851	1			T24	40		T1	10400		T12	5
bins_for_gpio_bits[12]	auto[0]	auto[0]	auto[0]	4663885	1			T23	259		T24	141		T1	28802
bins_for_gpio_bits[12]	auto[0]	auto[0]	auto[1]	3538550	1			T23	231		T24	13		T1	14358
bins_for_gpio_bits[12]	auto[0]	auto[1]	auto[0]	1290117	1			T24	32		T1	10350		T12	2
bins_for_gpio_bits[12]	auto[1]	auto[0]	auto[0]	1562586	1			T24	43		T1	15457		T12	6
bins_for_gpio_bits[12]	auto[1]	auto[0]	auto[1]	473598	1			T24	16		T1	941		T12	4
bins_for_gpio_bits[12]	auto[1]	auto[1]	auto[1]	1276838	1			T24	35		T1	10958		T12	20
bins_for_gpio_bits[13]	auto[0]	auto[0]	auto[0]	4674099	1			T23	197		T24	93		T1	28846
bins_for_gpio_bits[13]	auto[0]	auto[0]	auto[1]	3535181	1			T23	293		T24	16		T1	14130
bins_for_gpio_bits[13]	auto[0]	auto[1]	auto[0]	1288445	1			T24	51		T1	10374		T15	98
bins_for_gpio_bits[13]	auto[1]	auto[0]	auto[0]	1563129	1			T24	65		T1	15626		T12	1
bins_for_gpio_bits[13]	auto[1]	auto[0]	auto[1]	472860	1			T24	6		T1	1018		T12	5
bins_for_gpio_bits[13]	auto[1]	auto[1]	auto[1]	1271860	1			T24	49		T1	10872		T12	4
bins_for_gpio_bits[14]	auto[0]	auto[0]	auto[0]	4666617	1			T23	241		T24	78		T1	28817
bins_for_gpio_bits[14]	auto[0]	auto[0]	auto[1]	3539721	1			T23	249		T24	6		T1	14310
bins_for_gpio_bits[14]	auto[0]	auto[1]	auto[0]	1286038	1			T24	30		T1	10905		T15	128
bins_for_gpio_bits[14]	auto[1]	auto[0]	auto[0]	1565565	1			T24	110		T1	15482		T12	24
bins_for_gpio_bits[14]	auto[1]	auto[0]	auto[1]	473507	1			T24	18		T1	1023		T12	2
bins_for_gpio_bits[14]	auto[1]	auto[1]	auto[1]	1274126	1			T24	38		T1	10329		T12	7
bins_for_gpio_bits[15]	auto[0]	auto[0]	auto[0]	4657824	1			T23	219		T24	94		T1	28952
bins_for_gpio_bits[15]	auto[0]	auto[0]	auto[1]	3545986	1			T23	271		T24	14		T1	14487
bins_for_gpio_bits[15]	auto[0]	auto[1]	auto[0]	1289134	1			T24	45		T1	10613		T15	106
bins_for_gpio_bits[15]	auto[1]	auto[0]	auto[0]	1563900	1			T24	86		T1	15508		T12	10
bins_for_gpio_bits[15]	auto[1]	auto[0]	auto[1]	470225	1			T24	7		T1	953		T12	3
bins_for_gpio_bits[15]	auto[1]	auto[1]	auto[1]	1278505	1			T24	34		T1	10353		T12	3
bins_for_gpio_bits[16]	auto[0]	auto[0]	auto[0]	4666080	1			T23	290		T24	75		T1	29528
bins_for_gpio_bits[16]	auto[0]	auto[0]	auto[1]	3542368	1			T23	200		T24	16		T1	14452
bins_for_gpio_bits[16]	auto[0]	auto[1]	auto[0]	1286515	1			T24	56		T1	11184		T12	1
bins_for_gpio_bits[16]	auto[1]	auto[0]	auto[0]	1565021	1			T24	103		T1	14418		T12	2
bins_for_gpio_bits[16]	auto[1]	auto[0]	auto[1]	472392	1			T24	8		T1	836		T12	4
bins_for_gpio_bits[16]	auto[1]	auto[1]	auto[1]	1273198	1			T24	22		T1	10448		T12	12
bins_for_gpio_bits[17]	auto[0]	auto[0]	auto[0]	4664171	1			T23	237		T24	141		T1	29237
bins_for_gpio_bits[17]	auto[0]	auto[0]	auto[1]	3543647	1			T23	253		T24	23		T1	14380
bins_for_gpio_bits[17]	auto[0]	auto[1]	auto[0]	1282196	1			T24	53		T1	10671		T12	1
bins_for_gpio_bits[17]	auto[1]	auto[0]	auto[0]	1568616	1			T24	50		T1	15200		T12	16
bins_for_gpio_bits[17]	auto[1]	auto[0]	auto[1]	475028	1			T24	5		T1	920		T12	5
bins_for_gpio_bits[17]	auto[1]	auto[1]	auto[1]	1271916	1			T24	8		T1	10458		T12	8
bins_for_gpio_bits[18]	auto[0]	auto[0]	auto[0]	4666686	1			T23	258		T24	85		T1	28562
bins_for_gpio_bits[18]	auto[0]	auto[0]	auto[1]	3543862	1			T23	232		T24	12		T1	14291
bins_for_gpio_bits[18]	auto[0]	auto[1]	auto[0]	1282461	1			T24	6		T1	10774		T15	101
bins_for_gpio_bits[18]	auto[1]	auto[0]	auto[0]	1566052	1			T24	132		T1	15070		T12	17
bins_for_gpio_bits[18]	auto[1]	auto[0]	auto[1]	475026	1			T24	11		T1	942		T16	19
bins_for_gpio_bits[18]	auto[1]	auto[1]	auto[1]	1271487	1			T24	34		T1	11227		T15	96
bins_for_gpio_bits[19]	auto[0]	auto[0]	auto[0]	4659934	1			T23	214		T24	86		T1	29340
bins_for_gpio_bits[19]	auto[0]	auto[0]	auto[1]	3544438	1			T23	276		T24	11		T1	14325
bins_for_gpio_bits[19]	auto[0]	auto[1]	auto[0]	1283322	1			T24	36		T1	10269		T15	94
bins_for_gpio_bits[19]	auto[1]	auto[0]	auto[0]	1571549	1			T24	85		T1	15531		T12	10
bins_for_gpio_bits[19]	auto[1]	auto[0]	auto[1]	475342	1			T24	14		T1	932		T12	4
bins_for_gpio_bits[19]	auto[1]	auto[1]	auto[1]	1270989	1			T24	48		T1	10469		T12	2
bins_for_gpio_bits[20]	auto[0]	auto[0]	auto[0]	4662491	1			T23	259		T24	77		T1	28115
bins_for_gpio_bits[20]	auto[0]	auto[0]	auto[1]	3538150	1			T23	231		T24	7		T1	14373
bins_for_gpio_bits[20]	auto[0]	auto[1]	auto[0]	1286328	1			T24	24		T1	10180		T12	1
bins_for_gpio_bits[20]	auto[1]	auto[0]	auto[0]	1568837	1			T24	113		T1	16075		T12	2
bins_for_gpio_bits[20]	auto[1]	auto[0]	auto[1]	473576	1			T24	14		T1	1012		T12	3
bins_for_gpio_bits[20]	auto[1]	auto[1]	auto[1]	1276192	1			T24	45		T1	11111		T15	81
bins_for_gpio_bits[21]	auto[0]	auto[0]	auto[0]	4671553	1			T23	221		T24	116		T1	28983
bins_for_gpio_bits[21]	auto[0]	auto[0]	auto[1]	3537858	1			T23	269		T24	15		T1	14605
bins_for_gpio_bits[21]	auto[0]	auto[1]	auto[0]	1284258	1			T24	45		T1	10816		T15	131
bins_for_gpio_bits[21]	auto[1]	auto[0]	auto[0]	1566080	1			T24	65		T1	15158		T12	4
bins_for_gpio_bits[21]	auto[1]	auto[0]	auto[1]	475110	1			T24	3		T1	911		T12	2
bins_for_gpio_bits[21]	auto[1]	auto[1]	auto[1]	1270715	1			T24	36		T1	10393		T12	7
bins_for_gpio_bits[22]	auto[0]	auto[0]	auto[0]	4669166	1			T23	281		T24	74		T1	28636
bins_for_gpio_bits[22]	auto[0]	auto[0]	auto[1]	3530962	1			T23	209		T24	14		T1	14230
bins_for_gpio_bits[22]	auto[0]	auto[1]	auto[0]	1278543	1			T24	32		T1	10393		T12	1
bins_for_gpio_bits[22]	auto[1]	auto[0]	auto[0]	1571432	1			T24	83		T1	15918		T12	2
bins_for_gpio_bits[22]	auto[1]	auto[0]	auto[1]	474209	1			T24	15		T1	960		T12	5
bins_for_gpio_bits[22]	auto[1]	auto[1]	auto[1]	1281262	1			T24	62		T1	10729		T12	5
bins_for_gpio_bits[23]	auto[0]	auto[0]	auto[0]	4673707	1			T23	293		T24	81		T1	28870
bins_for_gpio_bits[23]	auto[0]	auto[0]	auto[1]	3537281	1			T23	197		T24	9		T1	14521
bins_for_gpio_bits[23]	auto[0]	auto[1]	auto[0]	1281157	1			T24	39		T1	10670		T15	124
bins_for_gpio_bits[23]	auto[1]	auto[0]	auto[0]	1569265	1			T24	113		T1	15200		T12	17
bins_for_gpio_bits[23]	auto[1]	auto[0]	auto[1]	476715	1			T24	12		T1	922		T12	3
bins_for_gpio_bits[23]	auto[1]	auto[1]	auto[1]	1267449	1			T24	26		T1	10683		T12	2
bins_for_gpio_bits[24]	auto[0]	auto[0]	auto[0]	4672655	1			T23	280		T24	91		T1	28836
bins_for_gpio_bits[24]	auto[0]	auto[0]	auto[1]	3539502	1			T23	210		T24	10		T1	14201
bins_for_gpio_bits[24]	auto[0]	auto[1]	auto[0]	1283157	1			T24	36		T1	10658		T15	112
bins_for_gpio_bits[24]	auto[1]	auto[0]	auto[0]	1565570	1			T24	92		T1	15162		T12	6
bins_for_gpio_bits[24]	auto[1]	auto[0]	auto[1]	471704	1			T24	11		T1	987		T12	4
bins_for_gpio_bits[24]	auto[1]	auto[1]	auto[1]	1272986	1			T24	40		T1	11022		T12	6
bins_for_gpio_bits[25]	auto[0]	auto[0]	auto[0]	4657185	1			T23	259		T24	124		T1	28397
bins_for_gpio_bits[25]	auto[0]	auto[0]	auto[1]	3548020	1			T23	231		T24	14		T1	14245
bins_for_gpio_bits[25]	auto[0]	auto[1]	auto[0]	1280649	1			T24	44		T1	10851		T15	118
bins_for_gpio_bits[25]	auto[1]	auto[0]	auto[0]	1568460	1			T24	67		T1	15683		T12	4
bins_for_gpio_bits[25]	auto[1]	auto[0]	auto[1]	476110	1			T24	6		T1	1083		T12	7
bins_for_gpio_bits[25]	auto[1]	auto[1]	auto[1]	1275150	1			T24	25		T1	10607		T12	13
bins_for_gpio_bits[26]	auto[0]	auto[0]	auto[0]	4661320	1			T23	248		T24	88		T1	28645
bins_for_gpio_bits[26]	auto[0]	auto[0]	auto[1]	3548327	1			T23	242		T24	9		T1	14369
bins_for_gpio_bits[26]	auto[0]	auto[1]	auto[0]	1284534	1			T24	48		T1	10752		T15	114
bins_for_gpio_bits[26]	auto[1]	auto[0]	auto[0]	1566326	1			T24	86		T1	15395		T12	17
bins_for_gpio_bits[26]	auto[1]	auto[0]	auto[1]	475970	1			T24	10		T1	992		T12	2
bins_for_gpio_bits[26]	auto[1]	auto[1]	auto[1]	1269097	1			T24	39		T1	10713		T12	3
bins_for_gpio_bits[27]	auto[0]	auto[0]	auto[0]	4658101	1			T23	282		T24	114		T1	28759
bins_for_gpio_bits[27]	auto[0]	auto[0]	auto[1]	3543323	1			T23	208		T24	14		T1	14464
bins_for_gpio_bits[27]	auto[0]	auto[1]	auto[0]	1278207	1			T24	34		T1	10828		T15	125
bins_for_gpio_bits[27]	auto[1]	auto[0]	auto[0]	1577168	1			T24	89		T1	15057		T12	4
bins_for_gpio_bits[27]	auto[1]	auto[0]	auto[1]	475973	1			T24	9		T1	974		T12	7
bins_for_gpio_bits[27]	auto[1]	auto[1]	auto[1]	1272802	1			T24	20		T1	10784		T12	4
bins_for_gpio_bits[28]	auto[0]	auto[0]	auto[0]	4669848	1			T23	251		T24	86		T1	28550
bins_for_gpio_bits[28]	auto[0]	auto[0]	auto[1]	3537648	1			T23	239		T24	7		T1	14269
bins_for_gpio_bits[28]	auto[0]	auto[1]	auto[0]	1285519	1			T24	28		T1	10478		T12	1
bins_for_gpio_bits[28]	auto[1]	auto[0]	auto[0]	1564114	1			T24	107		T1	15690		T12	8
bins_for_gpio_bits[28]	auto[1]	auto[0]	auto[1]	474165	1			T24	13		T1	989		T12	3
bins_for_gpio_bits[28]	auto[1]	auto[1]	auto[1]	1274280	1			T24	39		T1	10890		T12	2
bins_for_gpio_bits[29]	auto[0]	auto[0]	auto[0]	4656945	1			T23	163		T24	121		T1	29427
bins_for_gpio_bits[29]	auto[0]	auto[0]	auto[1]	3542934	1			T23	327		T24	11		T1	14351
bins_for_gpio_bits[29]	auto[0]	auto[1]	auto[0]	1283239	1			T24	44		T1	10826		T12	1
bins_for_gpio_bits[29]	auto[1]	auto[0]	auto[0]	1573100	1			T24	76		T1	15374		T12	22
bins_for_gpio_bits[29]	auto[1]	auto[0]	auto[1]	475743	1			T24	12		T1	920		T16	7
bins_for_gpio_bits[29]	auto[1]	auto[1]	auto[1]	1273613	1			T24	16		T1	9968		T15	147
bins_for_gpio_bits[30]	auto[0]	auto[0]	auto[0]	4665936	1			T23	254		T24	118		T1	28796
bins_for_gpio_bits[30]	auto[0]	auto[0]	auto[1]	3541754	1			T23	236		T24	13		T1	14394
bins_for_gpio_bits[30]	auto[0]	auto[1]	auto[0]	1281895	1			T24	58		T1	10808		T15	92
bins_for_gpio_bits[30]	auto[1]	auto[0]	auto[0]	1569452	1			T24	55		T1	15127		T12	1
bins_for_gpio_bits[30]	auto[1]	auto[0]	auto[1]	475366	1			T24	10		T1	983		T12	4
bins_for_gpio_bits[30]	auto[1]	auto[1]	auto[1]	1271171	1			T24	26		T1	10758		T12	2
bins_for_gpio_bits[31]	auto[0]	auto[0]	auto[0]	4669014	1			T23	208		T24	112		T1	29213
bins_for_gpio_bits[31]	auto[0]	auto[0]	auto[1]	3539786	1			T23	282		T24	14		T1	14442
bins_for_gpio_bits[31]	auto[0]	auto[1]	auto[0]	1285509	1			T24	20		T1	10886		T12	1
bins_for_gpio_bits[31]	auto[1]	auto[0]	auto[0]	1564519	1			T24	80		T1	15034		T12	12
bins_for_gpio_bits[31]	auto[1]	auto[0]	auto[1]	475137	1			T24	15		T1	825		T12	3
bins_for_gpio_bits[31]	auto[1]	auto[1]	auto[1]	1271609	1			T24	39		T1	10466		T12	3

User Defined Cross Bins for cp_cross_all

Excluded/Illegal bins

NAME	COUNT	STATUS
data_oe_1_data_out_0_data_in_1	0	Illegal
data_oe_1_data_out_1_data_in_0	0	Illegal