Unified Coverage Report :: Group :: gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

Group : gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_gpio_env_0.1/gpio_env_cov.sv

---

Summary for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	36	0	36	100.00
Crosses	128	0	128	100.00

Variables for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_pin	32	0	32	100.00	100	1	1	0
data_in	2	0	2	100.00	100	1	1	2
gpio_value	2	0	2	100.00	100	1	1	2

Crosses for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_cross_pins_data_in	128	0	128	100.00	100	1	1	0

Summary for Variable cp_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	12805574	1			T23	490		T24	280		T1	80866
bins_for_gpio_bits[1]	12805574	1			T23	490		T24	280		T1	80866
bins_for_gpio_bits[2]	12805574	1			T23	490		T24	280		T1	80866
bins_for_gpio_bits[3]	12805574	1			T23	490		T24	280		T1	80866
bins_for_gpio_bits[4]	12805574	1			T23	490		T24	280		T1	80866
bins_for_gpio_bits[5]	12805574	1			T23	490		T24	280		T1	80866
bins_for_gpio_bits[6]	12805574	1			T23	490		T24	280		T1	80866
bins_for_gpio_bits[7]	12805574	1			T23	490		T24	280		T1	80866
bins_for_gpio_bits[8]	12805574	1			T23	490		T24	280		T1	80866
bins_for_gpio_bits[9]	12805574	1			T23	490		T24	280		T1	80866
bins_for_gpio_bits[10]	12805574	1			T23	490		T24	280		T1	80866
bins_for_gpio_bits[11]	12805574	1			T23	490		T24	280		T1	80866
bins_for_gpio_bits[12]	12805574	1			T23	490		T24	280		T1	80866
bins_for_gpio_bits[13]	12805574	1			T23	490		T24	280		T1	80866
bins_for_gpio_bits[14]	12805574	1			T23	490		T24	280		T1	80866
bins_for_gpio_bits[15]	12805574	1			T23	490		T24	280		T1	80866
bins_for_gpio_bits[16]	12805574	1			T23	490		T24	280		T1	80866
bins_for_gpio_bits[17]	12805574	1			T23	490		T24	280		T1	80866
bins_for_gpio_bits[18]	12805574	1			T23	490		T24	280		T1	80866
bins_for_gpio_bits[19]	12805574	1			T23	490		T24	280		T1	80866
bins_for_gpio_bits[20]	12805574	1			T23	490		T24	280		T1	80866
bins_for_gpio_bits[21]	12805574	1			T23	490		T24	280		T1	80866
bins_for_gpio_bits[22]	12805574	1			T23	490		T24	280		T1	80866
bins_for_gpio_bits[23]	12805574	1			T23	490		T24	280		T1	80866
bins_for_gpio_bits[24]	12805574	1			T23	490		T24	280		T1	80866
bins_for_gpio_bits[25]	12805574	1			T23	490		T24	280		T1	80866
bins_for_gpio_bits[26]	12805574	1			T23	490		T24	280		T1	80866
bins_for_gpio_bits[27]	12805574	1			T23	490		T24	280		T1	80866
bins_for_gpio_bits[28]	12805574	1			T23	490		T24	280		T1	80866
bins_for_gpio_bits[29]	12805574	1			T23	490		T24	280		T1	80866
bins_for_gpio_bits[30]	12805574	1			T23	490		T24	280		T1	80866
bins_for_gpio_bits[31]	12805574	1			T23	490		T24	280		T1	80866

---

Summary for Variable data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

240521230

1

T23

8021

T24

7072

T1

175771

auto[1]

169257138

1

T23

7659

T24

1888

T1

829995

---

Summary for Variable gpio_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for gpio_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

240514386

1

T23

8021

T24

7072

T1

175746

auto[1]

169263982

1

T23

7659

T24

1888

T1

830246

---

Summary for Cross cp_cross_pins_data_in

Samples crossed: cp_pin gpio_value data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cp_cross_pins_data_in

Bins

cp_pin	gpio_value	data_in	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	auto[0]	auto[0]	7293821	1			T23	301		T24	217		T1	53378
bins_for_gpio_bits[0]	auto[0]	auto[1]	229160	1			T24	6		T1	1755		T15	28
bins_for_gpio_bits[0]	auto[1]	auto[0]	229369	1			T24	6		T1	1766		T15	28
bins_for_gpio_bits[0]	auto[1]	auto[1]	5053224	1			T23	189		T24	51		T1	23967
bins_for_gpio_bits[1]	auto[0]	auto[0]	7293516	1			T23	280		T24	186		T1	53466
bins_for_gpio_bits[1]	auto[0]	auto[1]	229767	1			T24	8		T1	1758		T15	29
bins_for_gpio_bits[1]	auto[1]	auto[0]	229964	1			T24	8		T1	1770		T15	29
bins_for_gpio_bits[1]	auto[1]	auto[1]	5052327	1			T23	210		T24	78		T1	23872
bins_for_gpio_bits[2]	auto[0]	auto[0]	7287237	1			T23	258		T24	187		T1	53700
bins_for_gpio_bits[2]	auto[0]	auto[1]	230280	1			T24	10		T1	1731		T15	29
bins_for_gpio_bits[2]	auto[1]	auto[0]	230543	1			T24	10		T1	1740		T15	29
bins_for_gpio_bits[2]	auto[1]	auto[1]	5057514	1			T23	232		T24	73		T1	23695
bins_for_gpio_bits[3]	auto[0]	auto[0]	7286220	1			T23	224		T24	239		T1	53453
bins_for_gpio_bits[3]	auto[0]	auto[1]	229637	1			T24	3		T1	1758		T15	27
bins_for_gpio_bits[3]	auto[1]	auto[0]	229834	1			T24	3		T1	1769		T12	1
bins_for_gpio_bits[3]	auto[1]	auto[1]	5059883	1			T23	266		T24	35		T1	23886
bins_for_gpio_bits[4]	auto[0]	auto[0]	7284981	1			T23	289		T24	214		T1	52963
bins_for_gpio_bits[4]	auto[0]	auto[1]	229641	1			T24	7		T1	1761		T15	28
bins_for_gpio_bits[4]	auto[1]	auto[0]	229839	1			T24	7		T1	1769		T15	28
bins_for_gpio_bits[4]	auto[1]	auto[1]	5061113	1			T23	201		T24	52		T1	24373
bins_for_gpio_bits[5]	auto[0]	auto[0]	7282560	1			T23	229		T24	211		T1	52795
bins_for_gpio_bits[5]	auto[0]	auto[1]	229348	1			T24	6		T1	1818		T15	28
bins_for_gpio_bits[5]	auto[1]	auto[0]	229571	1			T24	6		T1	1827		T12	1
bins_for_gpio_bits[5]	auto[1]	auto[1]	5064095	1			T23	261		T24	57		T1	24426
bins_for_gpio_bits[6]	auto[0]	auto[0]	7283186	1			T23	255		T24	217		T1	53404
bins_for_gpio_bits[6]	auto[0]	auto[1]	230439	1			T24	6		T1	1776		T15	27
bins_for_gpio_bits[6]	auto[1]	auto[0]	230658	1			T24	6		T1	1783		T15	27
bins_for_gpio_bits[6]	auto[1]	auto[1]	5061291	1			T23	235		T24	51		T1	23903
bins_for_gpio_bits[7]	auto[0]	auto[0]	7278730	1			T23	260		T24	223		T1	53000
bins_for_gpio_bits[7]	auto[0]	auto[1]	229814	1			T24	6		T1	1784		T15	22
bins_for_gpio_bits[7]	auto[1]	auto[0]	230031	1			T24	6		T1	1789		T12	1
bins_for_gpio_bits[7]	auto[1]	auto[1]	5066999	1			T23	230		T24	45		T1	24293
bins_for_gpio_bits[8]	auto[0]	auto[0]	7276717	1			T23	284		T24	213		T1	52891
bins_for_gpio_bits[8]	auto[0]	auto[1]	229634	1			T24	6		T1	1797		T15	30
bins_for_gpio_bits[8]	auto[1]	auto[0]	229832	1			T24	6		T1	1802		T12	1
bins_for_gpio_bits[8]	auto[1]	auto[1]	5069391	1			T23	206		T24	55		T1	24376
bins_for_gpio_bits[9]	auto[0]	auto[0]	7285725	1			T23	218		T24	225		T1	52761
bins_for_gpio_bits[9]	auto[0]	auto[1]	229464	1			T24	4		T1	1817		T15	29
bins_for_gpio_bits[9]	auto[1]	auto[0]	229675	1			T24	4		T1	1823		T12	1
bins_for_gpio_bits[9]	auto[1]	auto[1]	5060710	1			T23	272		T24	47		T1	24465
bins_for_gpio_bits[10]	auto[0]	auto[0]	7278344	1			T23	275		T24	202		T1	53266
bins_for_gpio_bits[10]	auto[0]	auto[1]	230428	1			T24	7		T1	1769		T15	20
bins_for_gpio_bits[10]	auto[1]	auto[0]	230625	1			T24	7		T1	1779		T12	1
bins_for_gpio_bits[10]	auto[1]	auto[1]	5066177	1			T23	215		T24	64		T1	24052
bins_for_gpio_bits[11]	auto[0]	auto[0]	7291055	1			T23	234		T24	204		T1	53486
bins_for_gpio_bits[11]	auto[0]	auto[1]	229809	1			T24	9		T1	1768		T15	23
bins_for_gpio_bits[11]	auto[1]	auto[0]	230016	1			T24	9		T1	1775		T12	1
bins_for_gpio_bits[11]	auto[1]	auto[1]	5054694	1			T23	256		T24	58		T1	23837
bins_for_gpio_bits[12]	auto[0]	auto[0]	7286977	1			T23	259		T24	208		T1	52835
bins_for_gpio_bits[12]	auto[0]	auto[1]	229396	1			T24	8		T1	1767		T12	1
bins_for_gpio_bits[12]	auto[1]	auto[0]	229611	1			T24	8		T1	1774		T12	2
bins_for_gpio_bits[12]	auto[1]	auto[1]	5059590	1			T23	231		T24	56		T1	24490
bins_for_gpio_bits[13]	auto[0]	auto[0]	7296175	1			T23	197		T24	201		T1	53031
bins_for_gpio_bits[13]	auto[0]	auto[1]	229278	1			T24	8		T1	1809		T15	29
bins_for_gpio_bits[13]	auto[1]	auto[0]	229498	1			T24	8		T1	1815		T15	29
bins_for_gpio_bits[13]	auto[1]	auto[1]	5050623	1			T23	293		T24	63		T1	24211
bins_for_gpio_bits[14]	auto[0]	auto[0]	7288786	1			T23	241		T24	212		T1	53433
bins_for_gpio_bits[14]	auto[0]	auto[1]	229214	1			T24	6		T1	1760		T15	29
bins_for_gpio_bits[14]	auto[1]	auto[0]	229434	1			T24	6		T1	1771		T12	1
bins_for_gpio_bits[14]	auto[1]	auto[1]	5058140	1			T23	249		T24	56		T1	23902
bins_for_gpio_bits[15]	auto[0]	auto[0]	7280885	1			T23	219		T24	220		T1	53302
bins_for_gpio_bits[15]	auto[0]	auto[1]	229778	1			T24	5		T1	1762		T15	28
bins_for_gpio_bits[15]	auto[1]	auto[0]	229973	1			T24	5		T1	1771		T15	29
bins_for_gpio_bits[15]	auto[1]	auto[1]	5064938	1			T23	271		T24	50		T1	24031
bins_for_gpio_bits[16]	auto[0]	auto[0]	7287734	1			T23	290		T24	229		T1	53370
bins_for_gpio_bits[16]	auto[0]	auto[1]	229702	1			T24	5		T1	1754		T15	27
bins_for_gpio_bits[16]	auto[1]	auto[0]	229882	1			T24	5		T1	1760		T15	27
bins_for_gpio_bits[16]	auto[1]	auto[1]	5058256	1			T23	200		T24	41		T1	23982
bins_for_gpio_bits[17]	auto[0]	auto[0]	7284924	1			T23	237		T24	241		T1	53428
bins_for_gpio_bits[17]	auto[0]	auto[1]	229817	1			T24	3		T1	1672		T15	26
bins_for_gpio_bits[17]	auto[1]	auto[0]	230059	1			T24	3		T1	1680		T15	26
bins_for_gpio_bits[17]	auto[1]	auto[1]	5060774	1			T23	253		T24	33		T1	24086
bins_for_gpio_bits[18]	auto[0]	auto[0]	7285520	1			T23	258		T24	216		T1	52597
bins_for_gpio_bits[18]	auto[0]	auto[1]	229428	1			T24	7		T1	1798		T15	21
bins_for_gpio_bits[18]	auto[1]	auto[0]	229679	1			T24	7		T1	1809		T15	21
bins_for_gpio_bits[18]	auto[1]	auto[1]	5060947	1			T23	232		T24	50		T1	24662
bins_for_gpio_bits[19]	auto[0]	auto[0]	7284529	1			T23	214		T24	196		T1	53394
bins_for_gpio_bits[19]	auto[0]	auto[1]	230083	1			T24	11		T1	1742		T15	26
bins_for_gpio_bits[19]	auto[1]	auto[0]	230276	1			T24	11		T1	1746		T15	26
bins_for_gpio_bits[19]	auto[1]	auto[1]	5060686	1			T23	276		T24	62		T1	23984
bins_for_gpio_bits[20]	auto[0]	auto[0]	7287438	1			T23	259		T24	203		T1	52567
bins_for_gpio_bits[20]	auto[0]	auto[1]	229988	1			T24	11		T1	1795		T15	21
bins_for_gpio_bits[20]	auto[1]	auto[0]	230218	1			T24	11		T1	1803		T15	22
bins_for_gpio_bits[20]	auto[1]	auto[1]	5057930	1			T23	231		T24	55		T1	24701
bins_for_gpio_bits[21]	auto[0]	auto[0]	7292481	1			T23	221		T24	218		T1	53185
bins_for_gpio_bits[21]	auto[0]	auto[1]	229182	1			T24	8		T1	1761		T15	26
bins_for_gpio_bits[21]	auto[1]	auto[0]	229410	1			T24	8		T1	1772		T12	1
bins_for_gpio_bits[21]	auto[1]	auto[1]	5054501	1			T23	269		T24	46		T1	24148
bins_for_gpio_bits[22]	auto[0]	auto[0]	7287964	1			T23	281		T24	181		T1	53154
bins_for_gpio_bits[22]	auto[0]	auto[1]	230965	1			T24	8		T1	1783		T15	24
bins_for_gpio_bits[22]	auto[1]	auto[0]	231177	1			T24	8		T1	1793		T15	25
bins_for_gpio_bits[22]	auto[1]	auto[1]	5055468	1			T23	209		T24	83		T1	24136
bins_for_gpio_bits[23]	auto[0]	auto[0]	7294751	1			T23	293		T24	226		T1	52945
bins_for_gpio_bits[23]	auto[0]	auto[1]	229163	1			T24	7		T1	1790		T15	22
bins_for_gpio_bits[23]	auto[1]	auto[0]	229378	1			T24	7		T1	1795		T12	1
bins_for_gpio_bits[23]	auto[1]	auto[1]	5052282	1			T23	197		T24	40		T1	24336
bins_for_gpio_bits[24]	auto[0]	auto[0]	7291474	1			T23	280		T24	214		T1	52871
bins_for_gpio_bits[24]	auto[0]	auto[1]	229695	1			T24	5		T1	1781		T15	19
bins_for_gpio_bits[24]	auto[1]	auto[0]	229908	1			T24	5		T1	1785		T15	20
bins_for_gpio_bits[24]	auto[1]	auto[1]	5054497	1			T23	210		T24	56		T1	24429
bins_for_gpio_bits[25]	auto[0]	auto[0]	7275746	1			T23	259		T24	231		T1	53145
bins_for_gpio_bits[25]	auto[0]	auto[1]	230352	1			T24	4		T1	1780		T15	22
bins_for_gpio_bits[25]	auto[1]	auto[0]	230548	1			T24	4		T1	1786		T15	23
bins_for_gpio_bits[25]	auto[1]	auto[1]	5068928	1			T23	231		T24	41		T1	24155
bins_for_gpio_bits[26]	auto[0]	auto[0]	7283141	1			T23	248		T24	214		T1	53020
bins_for_gpio_bits[26]	auto[0]	auto[1]	228854	1			T24	8		T1	1763		T15	22
bins_for_gpio_bits[26]	auto[1]	auto[0]	229039	1			T24	8		T1	1772		T12	1
bins_for_gpio_bits[26]	auto[1]	auto[1]	5064540	1			T23	242		T24	50		T1	24311
bins_for_gpio_bits[27]	auto[0]	auto[0]	7283312	1			T23	282		T24	232		T1	52823
bins_for_gpio_bits[27]	auto[0]	auto[1]	229933	1			T24	5		T1	1814		T15	25
bins_for_gpio_bits[27]	auto[1]	auto[0]	230164	1			T24	5		T1	1821		T12	1
bins_for_gpio_bits[27]	auto[1]	auto[1]	5062165	1			T23	208		T24	38		T1	24408
bins_for_gpio_bits[28]	auto[0]	auto[0]	7289376	1			T23	251		T24	210		T1	52936
bins_for_gpio_bits[28]	auto[0]	auto[1]	229871	1			T24	11		T1	1776		T15	25
bins_for_gpio_bits[28]	auto[1]	auto[0]	230105	1			T24	11		T1	1782		T12	1
bins_for_gpio_bits[28]	auto[1]	auto[1]	5056222	1			T23	239		T24	48		T1	24372
bins_for_gpio_bits[29]	auto[0]	auto[0]	7282905	1			T23	163		T24	238		T1	53900
bins_for_gpio_bits[29]	auto[0]	auto[1]	230176	1			T24	3		T1	1723		T15	29
bins_for_gpio_bits[29]	auto[1]	auto[0]	230379	1			T24	3		T1	1727		T15	30
bins_for_gpio_bits[29]	auto[1]	auto[1]	5062114	1			T23	327		T24	36		T1	23516
bins_for_gpio_bits[30]	auto[0]	auto[0]	7287716	1			T23	254		T24	224		T1	52937
bins_for_gpio_bits[30]	auto[0]	auto[1]	229338	1			T24	7		T1	1785		T15	30
bins_for_gpio_bits[30]	auto[1]	auto[0]	229567	1			T24	7		T1	1794		T15	31
bins_for_gpio_bits[30]	auto[1]	auto[1]	5058953	1			T23	236		T24	42		T1	24350
bins_for_gpio_bits[31]	auto[0]	auto[0]	7288977	1			T23	208		T24	204		T1	53385
bins_for_gpio_bits[31]	auto[0]	auto[1]	229849	1			T24	8		T1	1738		T15	26
bins_for_gpio_bits[31]	auto[1]	auto[0]	230065	1			T24	8		T1	1748		T15	27
bins_for_gpio_bits[31]	auto[1]	auto[1]	5056683	1			T23	282		T24	60		T1	23995