Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7472785 |
1 |
|
|
T23 |
490 |
|
T24 |
152 |
|
T1 |
45453 |
| auto[1] |
5490344 |
1 |
|
|
T1 |
36515 |
|
T11 |
139 |
|
T12 |
6 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12257988 |
1 |
|
|
T23 |
490 |
|
T24 |
152 |
|
T1 |
78050 |
| auto[1] |
705141 |
1 |
|
|
T1 |
3918 |
|
T11 |
3 |
|
T16 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7446688 |
1 |
|
|
T23 |
490 |
|
T24 |
152 |
|
T1 |
45975 |
| auto[1] |
5516441 |
1 |
|
|
T1 |
35993 |
|
T11 |
81 |
|
T12 |
13 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2405117 |
1 |
|
|
T1 |
16252 |
|
T11 |
50 |
|
T12 |
7 |
| auto[1] |
auto[0] |
auto[1] |
352067 |
1 |
|
|
T1 |
2032 |
|
T11 |
3 |
|
T16 |
1 |
| auto[1] |
auto[1] |
auto[0] |
2406183 |
1 |
|
|
T1 |
15823 |
|
T11 |
28 |
|
T12 |
6 |
| auto[1] |
auto[1] |
auto[1] |
353074 |
1 |
|
|
T1 |
1886 |
|
T129 |
70 |
|
T130 |
3 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7504076 |
1 |
|
|
T23 |
490 |
|
T24 |
152 |
|
T1 |
45326 |
| auto[1] |
5459053 |
1 |
|
|
T1 |
36642 |
|
T11 |
144 |
|
T12 |
11 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12265189 |
1 |
|
|
T23 |
490 |
|
T24 |
152 |
|
T1 |
78020 |
| auto[1] |
697940 |
1 |
|
|
T1 |
3948 |
|
T11 |
9 |
|
T16 |
2 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7500690 |
1 |
|
|
T23 |
490 |
|
T24 |
152 |
|
T1 |
44865 |
| auto[1] |
5462439 |
1 |
|
|
T1 |
37103 |
|
T11 |
146 |
|
T12 |
3 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2404152 |
1 |
|
|
T1 |
17006 |
|
T11 |
55 |
|
T12 |
3 |
| auto[1] |
auto[0] |
auto[1] |
352754 |
1 |
|
|
T1 |
2051 |
|
T11 |
2 |
|
T16 |
1 |
| auto[1] |
auto[1] |
auto[0] |
2360347 |
1 |
|
|
T1 |
16149 |
|
T11 |
82 |
|
T16 |
26 |
| auto[1] |
auto[1] |
auto[1] |
345186 |
1 |
|
|
T1 |
1897 |
|
T11 |
7 |
|
T16 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7478013 |
1 |
|
|
T23 |
490 |
|
T24 |
152 |
|
T1 |
45682 |
| auto[1] |
5485116 |
1 |
|
|
T1 |
36286 |
|
T11 |
114 |
|
T12 |
6 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12259818 |
1 |
|
|
T23 |
490 |
|
T24 |
152 |
|
T1 |
77754 |
| auto[1] |
703311 |
1 |
|
|
T1 |
4214 |
|
T11 |
8 |
|
T16 |
4 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7477347 |
1 |
|
|
T23 |
490 |
|
T24 |
152 |
|
T1 |
44158 |
| auto[1] |
5485782 |
1 |
|
|
T1 |
37810 |
|
T11 |
117 |
|
T12 |
16 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2389442 |
1 |
|
|
T1 |
17403 |
|
T11 |
75 |
|
T12 |
10 |
| auto[1] |
auto[0] |
auto[1] |
352296 |
1 |
|
|
T1 |
2073 |
|
T11 |
7 |
|
T16 |
4 |
| auto[1] |
auto[1] |
auto[0] |
2393029 |
1 |
|
|
T1 |
16193 |
|
T11 |
34 |
|
T12 |
6 |
| auto[1] |
auto[1] |
auto[1] |
351015 |
1 |
|
|
T1 |
2141 |
|
T11 |
1 |
|
T129 |
81 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7476985 |
1 |
|
|
T23 |
490 |
|
T24 |
152 |
|
T1 |
46005 |
| auto[1] |
5486144 |
1 |
|
|
T1 |
35963 |
|
T11 |
149 |
|
T12 |
5 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12258400 |
1 |
|
|
T23 |
490 |
|
T24 |
152 |
|
T1 |
78025 |
| auto[1] |
704729 |
1 |
|
|
T1 |
3943 |
|
T11 |
10 |
|
T16 |
2 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7446293 |
1 |
|
|
T23 |
490 |
|
T24 |
152 |
|
T1 |
45041 |
| auto[1] |
5516836 |
1 |
|
|
T1 |
36927 |
|
T11 |
142 |
|
T12 |
6 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2409101 |
1 |
|
|
T1 |
17279 |
|
T11 |
54 |
|
T12 |
6 |
| auto[1] |
auto[0] |
auto[1] |
353306 |
1 |
|
|
T1 |
2141 |
|
T11 |
5 |
|
T16 |
2 |
| auto[1] |
auto[1] |
auto[0] |
2403006 |
1 |
|
|
T1 |
15705 |
|
T11 |
78 |
|
T16 |
12 |
| auto[1] |
auto[1] |
auto[1] |
351423 |
1 |
|
|
T1 |
1802 |
|
T11 |
5 |
|
T129 |
78 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7468173 |
1 |
|
|
T23 |
490 |
|
T24 |
152 |
|
T1 |
45357 |
| auto[1] |
5494956 |
1 |
|
|
T1 |
36611 |
|
T11 |
165 |
|
T12 |
6 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12260266 |
1 |
|
|
T23 |
490 |
|
T24 |
152 |
|
T1 |
78045 |
| auto[1] |
702863 |
1 |
|
|
T1 |
3923 |
|
T11 |
6 |
|
T12 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7467988 |
1 |
|
|
T23 |
490 |
|
T24 |
152 |
|
T1 |
45765 |
| auto[1] |
5495141 |
1 |
|
|
T1 |
36203 |
|
T11 |
112 |
|
T12 |
13 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2412177 |
1 |
|
|
T1 |
16367 |
|
T11 |
37 |
|
T12 |
7 |
| auto[1] |
auto[0] |
auto[1] |
355613 |
1 |
|
|
T1 |
2025 |
|
T11 |
2 |
|
T16 |
1 |
| auto[1] |
auto[1] |
auto[0] |
2380101 |
1 |
|
|
T1 |
15913 |
|
T11 |
69 |
|
T12 |
5 |
| auto[1] |
auto[1] |
auto[1] |
347250 |
1 |
|
|
T1 |
1898 |
|
T11 |
4 |
|
T12 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7459212 |
1 |
|
|
T23 |
490 |
|
T24 |
152 |
|
T1 |
46551 |
| auto[1] |
5503917 |
1 |
|
|
T1 |
35417 |
|
T11 |
152 |
|
T16 |
50 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12260872 |
1 |
|
|
T23 |
490 |
|
T24 |
152 |
|
T1 |
77836 |
| auto[1] |
702257 |
1 |
|
|
T1 |
4132 |
|
T11 |
10 |
|
T12 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7481108 |
1 |
|
|
T23 |
490 |
|
T24 |
152 |
|
T1 |
44990 |
| auto[1] |
5482021 |
1 |
|
|
T1 |
36978 |
|
T11 |
116 |
|
T12 |
9 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2388013 |
1 |
|
|
T1 |
17304 |
|
T11 |
49 |
|
T12 |
8 |
| auto[1] |
auto[0] |
auto[1] |
350174 |
1 |
|
|
T1 |
2235 |
|
T11 |
4 |
|
T12 |
1 |
| auto[1] |
auto[1] |
auto[0] |
2391751 |
1 |
|
|
T1 |
15542 |
|
T11 |
57 |
|
T16 |
6 |
| auto[1] |
auto[1] |
auto[1] |
352083 |
1 |
|
|
T1 |
1897 |
|
T11 |
6 |
|
T16 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7458971 |
1 |
|
|
T23 |
490 |
|
T24 |
152 |
|
T1 |
45737 |
| auto[1] |
5504158 |
1 |
|
|
T1 |
36231 |
|
T11 |
118 |
|
T12 |
6 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12262117 |
1 |
|
|
T23 |
490 |
|
T24 |
152 |
|
T1 |
78136 |
| auto[1] |
701012 |
1 |
|
|
T1 |
3832 |
|
T11 |
8 |
|
T16 |
2 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7472708 |
1 |
|
|
T23 |
490 |
|
T24 |
152 |
|
T1 |
45580 |
| auto[1] |
5490421 |
1 |
|
|
T1 |
36388 |
|
T11 |
148 |
|
T12 |
6 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2397371 |
1 |
|
|
T1 |
16152 |
|
T11 |
74 |
|
T12 |
6 |
| auto[1] |
auto[0] |
auto[1] |
351186 |
1 |
|
|
T1 |
1918 |
|
T11 |
2 |
|
T16 |
2 |
| auto[1] |
auto[1] |
auto[0] |
2392038 |
1 |
|
|
T1 |
16404 |
|
T11 |
66 |
|
T16 |
6 |
| auto[1] |
auto[1] |
auto[1] |
349826 |
1 |
|
|
T1 |
1914 |
|
T11 |
6 |
|
T129 |
86 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7445512 |
1 |
|
|
T23 |
490 |
|
T24 |
152 |
|
T1 |
44570 |
| auto[1] |
5517617 |
1 |
|
|
T1 |
37398 |
|
T11 |
140 |
|
T12 |
6 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12262147 |
1 |
|
|
T23 |
490 |
|
T24 |
152 |
|
T1 |
77938 |
| auto[1] |
700982 |
1 |
|
|
T1 |
4030 |
|
T11 |
10 |
|
T16 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7477331 |
1 |
|
|
T23 |
490 |
|
T24 |
152 |
|
T1 |
45824 |
| auto[1] |
5485798 |
1 |
|
|
T1 |
36144 |
|
T11 |
150 |
|
T12 |
13 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2400519 |
1 |
|
|
T1 |
15932 |
|
T11 |
66 |
|
T12 |
7 |
| auto[1] |
auto[0] |
auto[1] |
350683 |
1 |
|
|
T1 |
1933 |
|
T11 |
5 |
|
T17 |
1 |
| auto[1] |
auto[1] |
auto[0] |
2384297 |
1 |
|
|
T1 |
16182 |
|
T11 |
74 |
|
T12 |
6 |
| auto[1] |
auto[1] |
auto[1] |
350299 |
1 |
|
|
T1 |
2097 |
|
T11 |
5 |
|
T16 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7461528 |
1 |
|
|
T23 |
490 |
|
T24 |
152 |
|
T1 |
45332 |
| auto[1] |
5501601 |
1 |
|
|
T1 |
36636 |
|
T11 |
111 |
|
T12 |
11 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12259209 |
1 |
|
|
T23 |
490 |
|
T24 |
152 |
|
T1 |
77869 |
| auto[1] |
703920 |
1 |
|
|
T1 |
4099 |
|
T11 |
12 |
|
T16 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7461070 |
1 |
|
|
T23 |
490 |
|
T24 |
152 |
|
T1 |
44812 |
| auto[1] |
5502059 |
1 |
|
|
T1 |
37156 |
|
T11 |
157 |
|
T12 |
16 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2387423 |
1 |
|
|
T1 |
16661 |
|
T11 |
90 |
|
T12 |
6 |
| auto[1] |
auto[0] |
auto[1] |
348763 |
1 |
|
|
T1 |
2048 |
|
T11 |
6 |
|
T16 |
1 |
| auto[1] |
auto[1] |
auto[0] |
2410716 |
1 |
|
|
T1 |
16396 |
|
T11 |
55 |
|
T12 |
10 |
| auto[1] |
auto[1] |
auto[1] |
355157 |
1 |
|
|
T1 |
2051 |
|
T11 |
6 |
|
T129 |
64 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7470738 |
1 |
|
|
T23 |
490 |
|
T24 |
152 |
|
T1 |
47313 |
| auto[1] |
5492391 |
1 |
|
|
T1 |
34655 |
|
T11 |
136 |
|
T16 |
48 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12256674 |
1 |
|
|
T23 |
490 |
|
T24 |
152 |
|
T1 |
78210 |
| auto[1] |
706455 |
1 |
|
|
T1 |
3758 |
|
T11 |
6 |
|
T12 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7459813 |
1 |
|
|
T23 |
490 |
|
T24 |
152 |
|
T1 |
45790 |
| auto[1] |
5503316 |
1 |
|
|
T1 |
36178 |
|
T11 |
115 |
|
T12 |
3 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2403103 |
1 |
|
|
T1 |
16715 |
|
T11 |
77 |
|
T12 |
2 |
| auto[1] |
auto[0] |
auto[1] |
353777 |
1 |
|
|
T1 |
2039 |
|
T11 |
4 |
|
T12 |
1 |
| auto[1] |
auto[1] |
auto[0] |
2393758 |
1 |
|
|
T1 |
15705 |
|
T11 |
32 |
|
T16 |
16 |
| auto[1] |
auto[1] |
auto[1] |
352678 |
1 |
|
|
T1 |
1719 |
|
T11 |
2 |
|
T16 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7469380 |
1 |
|
|
T23 |
490 |
|
T24 |
152 |
|
T1 |
46013 |
| auto[1] |
5493749 |
1 |
|
|
T1 |
35955 |
|
T11 |
81 |
|
T16 |
39 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12261583 |
1 |
|
|
T23 |
490 |
|
T24 |
152 |
|
T1 |
77936 |
| auto[1] |
701546 |
1 |
|
|
T1 |
4032 |
|
T11 |
11 |
|
T16 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7475794 |
1 |
|
|
T23 |
490 |
|
T24 |
152 |
|
T1 |
44251 |
| auto[1] |
5487335 |
1 |
|
|
T1 |
37717 |
|
T11 |
134 |
|
T12 |
6 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2382411 |
1 |
|
|
T1 |
17512 |
|
T11 |
80 |
|
T12 |
6 |
| auto[1] |
auto[0] |
auto[1] |
347945 |
1 |
|
|
T1 |
2037 |
|
T11 |
8 |
|
T129 |
51 |
| auto[1] |
auto[1] |
auto[0] |
2403378 |
1 |
|
|
T1 |
16173 |
|
T11 |
43 |
|
T16 |
10 |
| auto[1] |
auto[1] |
auto[1] |
353601 |
1 |
|
|
T1 |
1995 |
|
T11 |
3 |
|
T16 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7476598 |
1 |
|
|
T23 |
490 |
|
T24 |
152 |
|
T1 |
45639 |
| auto[1] |
5486531 |
1 |
|
|
T1 |
36329 |
|
T11 |
149 |
|
T12 |
11 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12263060 |
1 |
|
|
T23 |
490 |
|
T24 |
152 |
|
T1 |
78225 |
| auto[1] |
700069 |
1 |
|
|
T1 |
3743 |
|
T11 |
9 |
|
T12 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7487075 |
1 |
|
|
T23 |
490 |
|
T24 |
152 |
|
T1 |
46243 |
| auto[1] |
5476054 |
1 |
|
|
T1 |
35725 |
|
T11 |
129 |
|
T12 |
16 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2402759 |
1 |
|
|
T1 |
16035 |
|
T11 |
46 |
|
T12 |
5 |
| auto[1] |
auto[0] |
auto[1] |
353273 |
1 |
|
|
T1 |
1884 |
|
T11 |
2 |
|
T12 |
1 |
| auto[1] |
auto[1] |
auto[0] |
2373226 |
1 |
|
|
T1 |
15947 |
|
T11 |
74 |
|
T12 |
10 |
| auto[1] |
auto[1] |
auto[1] |
346796 |
1 |
|
|
T1 |
1859 |
|
T11 |
7 |
|
T129 |
83 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7491741 |
1 |
|
|
T23 |
490 |
|
T24 |
152 |
|
T1 |
44899 |
| auto[1] |
5471388 |
1 |
|
|
T1 |
37069 |
|
T11 |
141 |
|
T12 |
11 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12258731 |
1 |
|
|
T23 |
490 |
|
T24 |
152 |
|
T1 |
77930 |
| auto[1] |
704398 |
1 |
|
|
T1 |
4038 |
|
T11 |
7 |
|
T12 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7465013 |
1 |
|
|
T23 |
490 |
|
T24 |
152 |
|
T1 |
45174 |
| auto[1] |
5498116 |
1 |
|
|
T1 |
36794 |
|
T11 |
156 |
|
T12 |
3 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2403746 |
1 |
|
|
T1 |
16590 |
|
T11 |
73 |
|
T12 |
2 |
| auto[1] |
auto[0] |
auto[1] |
353514 |
1 |
|
|
T1 |
2069 |
|
T11 |
3 |
|
T12 |
1 |
| auto[1] |
auto[1] |
auto[0] |
2389972 |
1 |
|
|
T1 |
16166 |
|
T11 |
76 |
|
T17 |
4 |
| auto[1] |
auto[1] |
auto[1] |
350884 |
1 |
|
|
T1 |
1969 |
|
T11 |
4 |
|
T129 |
71 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7490904 |
1 |
|
|
T23 |
490 |
|
T24 |
152 |
|
T1 |
46265 |
| auto[1] |
5472225 |
1 |
|
|
T1 |
35703 |
|
T11 |
92 |
|
T12 |
6 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12252895 |
1 |
|
|
T23 |
490 |
|
T24 |
152 |
|
T1 |
78107 |
| auto[1] |
710234 |
1 |
|
|
T1 |
3861 |
|
T11 |
11 |
|
T16 |
2 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7427562 |
1 |
|
|
T23 |
490 |
|
T24 |
152 |
|
T1 |
46227 |
| auto[1] |
5535567 |
1 |
|
|
T1 |
35741 |
|
T11 |
167 |
|
T12 |
6 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2412613 |
1 |
|
|
T1 |
16528 |
|
T11 |
106 |
|
T12 |
6 |
| auto[1] |
auto[0] |
auto[1] |
355223 |
1 |
|
|
T1 |
1983 |
|
T11 |
6 |
|
T16 |
2 |
| auto[1] |
auto[1] |
auto[0] |
2412720 |
1 |
|
|
T1 |
15352 |
|
T11 |
50 |
|
T16 |
8 |
| auto[1] |
auto[1] |
auto[1] |
355011 |
1 |
|
|
T1 |
1878 |
|
T11 |
5 |
|
T129 |
108 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7458067 |
1 |
|
|
T23 |
490 |
|
T24 |
152 |
|
T1 |
45462 |
| auto[1] |
5505062 |
1 |
|
|
T1 |
36506 |
|
T11 |
123 |
|
T12 |
11 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12264811 |
1 |
|
|
T23 |
490 |
|
T24 |
152 |
|
T1 |
78059 |
| auto[1] |
698318 |
1 |
|
|
T1 |
3909 |
|
T11 |
7 |
|
T16 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7503415 |
1 |
|
|
T23 |
490 |
|
T24 |
152 |
|
T1 |
45467 |
| auto[1] |
5459714 |
1 |
|
|
T1 |
36501 |
|
T11 |
145 |
|
T12 |
9 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2385520 |
1 |
|
|
T1 |
16389 |
|
T11 |
69 |
|
T12 |
9 |
| auto[1] |
auto[0] |
auto[1] |
350286 |
1 |
|
|
T1 |
2058 |
|
T11 |
6 |
|
T16 |
1 |
| auto[1] |
auto[1] |
auto[0] |
2375876 |
1 |
|
|
T1 |
16203 |
|
T11 |
69 |
|
T16 |
4 |
| auto[1] |
auto[1] |
auto[1] |
348032 |
1 |
|
|
T1 |
1851 |
|
T11 |
1 |
|
T129 |
86 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7471057 |
1 |
|
|
T23 |
490 |
|
T24 |
152 |
|
T1 |
43669 |
| auto[1] |
5492072 |
1 |
|
|
T1 |
38299 |
|
T11 |
82 |
|
T12 |
11 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12259062 |
1 |
|
|
T23 |
490 |
|
T24 |
152 |
|
T1 |
77957 |
| auto[1] |
704067 |
1 |
|
|
T1 |
4011 |
|
T11 |
13 |
|
T16 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7463044 |
1 |
|
|
T23 |
490 |
|
T24 |
152 |
|
T1 |
44885 |
| auto[1] |
5500085 |
1 |
|
|
T1 |
37083 |
|
T11 |
181 |
|
T12 |
16 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2409537 |
1 |
|
|
T1 |
15813 |
|
T11 |
122 |
|
T12 |
6 |
| auto[1] |
auto[0] |
auto[1] |
353009 |
1 |
|
|
T1 |
1904 |
|
T11 |
8 |
|
T129 |
117 |
| auto[1] |
auto[1] |
auto[0] |
2386481 |
1 |
|
|
T1 |
17259 |
|
T11 |
46 |
|
T12 |
10 |
| auto[1] |
auto[1] |
auto[1] |
351058 |
1 |
|
|
T1 |
2107 |
|
T11 |
5 |
|
T16 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7503188 |
1 |
|
|
T23 |
490 |
|
T24 |
152 |
|
T1 |
45674 |
| auto[1] |
5459941 |
1 |
|
|
T1 |
36294 |
|
T11 |
120 |
|
T12 |
5 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12265194 |
1 |
|
|
T23 |
490 |
|
T24 |
152 |
|
T1 |
78014 |
| auto[1] |
697935 |
1 |
|
|
T1 |
3954 |
|
T11 |
11 |
|
T16 |
3 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7505303 |
1 |
|
|
T23 |
490 |
|
T24 |
152 |
|
T1 |
45539 |
| auto[1] |
5457826 |
1 |
|
|
T1 |
36429 |
|
T11 |
151 |
|
T16 |
35 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2397124 |
1 |
|
|
T1 |
16586 |
|
T11 |
78 |
|
T16 |
12 |
| auto[1] |
auto[0] |
auto[1] |
352415 |
1 |
|
|
T1 |
1983 |
|
T11 |
8 |
|
T16 |
2 |
| auto[1] |
auto[1] |
auto[0] |
2362767 |
1 |
|
|
T1 |
15889 |
|
T11 |
62 |
|
T16 |
20 |
| auto[1] |
auto[1] |
auto[1] |
345520 |
1 |
|
|
T1 |
1971 |
|
T11 |
3 |
|
T16 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7442397 |
1 |
|
|
T23 |
490 |
|
T24 |
152 |
|
T1 |
46616 |
| auto[1] |
5520732 |
1 |
|
|
T1 |
35352 |
|
T11 |
163 |
|
T12 |
11 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12264437 |
1 |
|
|
T23 |
490 |
|
T24 |
152 |
|
T1 |
78018 |
| auto[1] |
698692 |
1 |
|
|
T1 |
3950 |
|
T11 |
7 |
|
T16 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7493136 |
1 |
|
|
T23 |
490 |
|
T24 |
152 |
|
T1 |
45384 |
| auto[1] |
5469993 |
1 |
|
|
T1 |
36584 |
|
T11 |
98 |
|
T16 |
31 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2381174 |
1 |
|
|
T1 |
16892 |
|
T11 |
37 |
|
T16 |
15 |
| auto[1] |
auto[0] |
auto[1] |
348211 |
1 |
|
|
T1 |
2024 |
|
T11 |
4 |
|
T16 |
1 |
| auto[1] |
auto[1] |
auto[0] |
2390127 |
1 |
|
|
T1 |
15742 |
|
T11 |
54 |
|
T16 |
15 |
| auto[1] |
auto[1] |
auto[1] |
350481 |
1 |
|
|
T1 |
1926 |
|
T11 |
3 |
|
T129 |
46 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7483314 |
1 |
|
|
T23 |
490 |
|
T24 |
152 |
|
T1 |
44495 |
| auto[1] |
5479815 |
1 |
|
|
T1 |
37473 |
|
T11 |
130 |
|
T12 |
6 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12262086 |
1 |
|
|
T23 |
490 |
|
T24 |
152 |
|
T1 |
78132 |
| auto[1] |
701043 |
1 |
|
|
T1 |
3836 |
|
T11 |
11 |
|
T16 |
3 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7489962 |
1 |
|
|
T23 |
490 |
|
T24 |
152 |
|
T1 |
46453 |
| auto[1] |
5473167 |
1 |
|
|
T1 |
35515 |
|
T11 |
137 |
|
T12 |
3 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2391054 |
1 |
|
|
T1 |
15882 |
|
T11 |
83 |
|
T12 |
3 |
| auto[1] |
auto[0] |
auto[1] |
351701 |
1 |
|
|
T1 |
1957 |
|
T11 |
8 |
|
T16 |
3 |
| auto[1] |
auto[1] |
auto[0] |
2381070 |
1 |
|
|
T1 |
15797 |
|
T11 |
43 |
|
T16 |
5 |
| auto[1] |
auto[1] |
auto[1] |
349342 |
1 |
|
|
T1 |
1879 |
|
T11 |
3 |
|
T129 |
75 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7500625 |
1 |
|
|
T23 |
490 |
|
T24 |
152 |
|
T1 |
45321 |
| auto[1] |
5462504 |
1 |
|
|
T1 |
36647 |
|
T11 |
144 |
|
T12 |
5 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12258804 |
1 |
|
|
T23 |
490 |
|
T24 |
152 |
|
T1 |
78003 |
| auto[1] |
704325 |
1 |
|
|
T1 |
3965 |
|
T11 |
8 |
|
T16 |
2 |