Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7471900 |
1 |
|
|
T23 |
490 |
|
T24 |
152 |
|
T1 |
47193 |
| auto[1] |
5491229 |
1 |
|
|
T1 |
34775 |
|
T11 |
115 |
|
T12 |
11 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12260703 |
1 |
|
|
T23 |
490 |
|
T24 |
152 |
|
T1 |
78058 |
| auto[1] |
702426 |
1 |
|
|
T1 |
3910 |
|
T11 |
11 |
|
T16 |
2 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7471298 |
1 |
|
|
T23 |
490 |
|
T24 |
152 |
|
T1 |
46917 |
| auto[1] |
5491831 |
1 |
|
|
T1 |
35051 |
|
T11 |
155 |
|
T12 |
6 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2389608 |
1 |
|
|
T1 |
16635 |
|
T11 |
78 |
|
T12 |
6 |
| auto[1] |
auto[0] |
auto[1] |
349880 |
1 |
|
|
T1 |
2137 |
|
T11 |
6 |
|
T16 |
1 |
| auto[1] |
auto[1] |
auto[0] |
2399797 |
1 |
|
|
T1 |
14506 |
|
T11 |
66 |
|
T16 |
16 |
| auto[1] |
auto[1] |
auto[1] |
352546 |
1 |
|
|
T1 |
1773 |
|
T11 |
5 |
|
T16 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |