Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7472785 |
1 |
|
|
T23 |
490 |
|
T24 |
152 |
|
T1 |
45453 |
| auto[1] |
5490344 |
1 |
|
|
T1 |
36515 |
|
T11 |
139 |
|
T12 |
6 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10651959 |
1 |
|
|
T23 |
490 |
|
T24 |
152 |
|
T1 |
69803 |
| auto[1] |
2311170 |
1 |
|
|
T1 |
12165 |
|
T11 |
50 |
|
T12 |
4 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7473238 |
1 |
|
|
T23 |
490 |
|
T24 |
152 |
|
T1 |
45577 |
| auto[1] |
5489891 |
1 |
|
|
T1 |
36391 |
|
T11 |
106 |
|
T12 |
4 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1580049 |
1 |
|
|
T1 |
12282 |
|
T11 |
21 |
|
T16 |
4 |
| auto[1] |
auto[0] |
auto[1] |
1149200 |
1 |
|
|
T1 |
6159 |
|
T11 |
14 |
|
T16 |
15 |
| auto[1] |
auto[1] |
auto[0] |
1598672 |
1 |
|
|
T1 |
11944 |
|
T11 |
35 |
|
T129 |
284 |
| auto[1] |
auto[1] |
auto[1] |
1161970 |
1 |
|
|
T1 |
6006 |
|
T11 |
36 |
|
T12 |
4 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |