Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7504076 |
1 |
|
|
T23 |
490 |
|
T24 |
152 |
|
T1 |
45326 |
| auto[1] |
5459053 |
1 |
|
|
T1 |
36642 |
|
T11 |
144 |
|
T12 |
11 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10661538 |
1 |
|
|
T23 |
490 |
|
T24 |
152 |
|
T1 |
69263 |
| auto[1] |
2301591 |
1 |
|
|
T1 |
12705 |
|
T11 |
89 |
|
T12 |
4 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7509128 |
1 |
|
|
T23 |
490 |
|
T24 |
152 |
|
T1 |
45147 |
| auto[1] |
5454001 |
1 |
|
|
T1 |
36821 |
|
T11 |
151 |
|
T12 |
4 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1586234 |
1 |
|
|
T1 |
12378 |
|
T11 |
31 |
|
T16 |
2 |
| auto[1] |
auto[0] |
auto[1] |
1157265 |
1 |
|
|
T1 |
6391 |
|
T11 |
36 |
|
T16 |
1 |
| auto[1] |
auto[1] |
auto[0] |
1566176 |
1 |
|
|
T1 |
11738 |
|
T11 |
31 |
|
T16 |
3 |
| auto[1] |
auto[1] |
auto[1] |
1144326 |
1 |
|
|
T1 |
6314 |
|
T11 |
53 |
|
T12 |
4 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |