Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7478013 |
1 |
|
|
T23 |
490 |
|
T24 |
152 |
|
T1 |
45682 |
| auto[1] |
5485116 |
1 |
|
|
T1 |
36286 |
|
T11 |
114 |
|
T12 |
6 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10647073 |
1 |
|
|
T23 |
490 |
|
T24 |
152 |
|
T1 |
69112 |
| auto[1] |
2316056 |
1 |
|
|
T1 |
12856 |
|
T11 |
69 |
|
T16 |
6 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7456768 |
1 |
|
|
T23 |
490 |
|
T24 |
152 |
|
T1 |
44939 |
| auto[1] |
5506361 |
1 |
|
|
T1 |
37029 |
|
T11 |
121 |
|
T12 |
8 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1615613 |
1 |
|
|
T1 |
12661 |
|
T11 |
27 |
|
T12 |
2 |
| auto[1] |
auto[0] |
auto[1] |
1164729 |
1 |
|
|
T1 |
6754 |
|
T11 |
51 |
|
T16 |
6 |
| auto[1] |
auto[1] |
auto[0] |
1574692 |
1 |
|
|
T1 |
11512 |
|
T11 |
25 |
|
T12 |
6 |
| auto[1] |
auto[1] |
auto[1] |
1151327 |
1 |
|
|
T1 |
6102 |
|
T11 |
18 |
|
T129 |
262 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |