Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7476985 |
1 |
|
|
T23 |
490 |
|
T24 |
152 |
|
T1 |
46005 |
| auto[1] |
5486144 |
1 |
|
|
T1 |
35963 |
|
T11 |
149 |
|
T12 |
5 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10650345 |
1 |
|
|
T23 |
490 |
|
T24 |
152 |
|
T1 |
69267 |
| auto[1] |
2312784 |
1 |
|
|
T1 |
12701 |
|
T11 |
81 |
|
T16 |
22 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7469432 |
1 |
|
|
T23 |
490 |
|
T24 |
152 |
|
T1 |
45557 |
| auto[1] |
5493697 |
1 |
|
|
T1 |
36411 |
|
T11 |
135 |
|
T12 |
4 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1588400 |
1 |
|
|
T1 |
12154 |
|
T11 |
20 |
|
T12 |
2 |
| auto[1] |
auto[0] |
auto[1] |
1152058 |
1 |
|
|
T1 |
6530 |
|
T11 |
20 |
|
T16 |
17 |
| auto[1] |
auto[1] |
auto[0] |
1592513 |
1 |
|
|
T1 |
11556 |
|
T11 |
34 |
|
T12 |
2 |
| auto[1] |
auto[1] |
auto[1] |
1160726 |
1 |
|
|
T1 |
6171 |
|
T11 |
61 |
|
T16 |
5 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |