Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7468173 |
1 |
|
|
T23 |
490 |
|
T24 |
152 |
|
T1 |
45357 |
| auto[1] |
5494956 |
1 |
|
|
T1 |
36611 |
|
T11 |
165 |
|
T12 |
6 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10652949 |
1 |
|
|
T23 |
490 |
|
T24 |
152 |
|
T1 |
68596 |
| auto[1] |
2310180 |
1 |
|
|
T1 |
13372 |
|
T11 |
71 |
|
T12 |
6 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7478768 |
1 |
|
|
T23 |
490 |
|
T24 |
152 |
|
T1 |
44008 |
| auto[1] |
5484361 |
1 |
|
|
T1 |
37960 |
|
T11 |
147 |
|
T12 |
8 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1582859 |
1 |
|
|
T1 |
12988 |
|
T11 |
31 |
|
T16 |
4 |
| auto[1] |
auto[0] |
auto[1] |
1156522 |
1 |
|
|
T1 |
6640 |
|
T11 |
29 |
|
T12 |
2 |
| auto[1] |
auto[1] |
auto[0] |
1591322 |
1 |
|
|
T1 |
11600 |
|
T11 |
45 |
|
T12 |
2 |
| auto[1] |
auto[1] |
auto[1] |
1153658 |
1 |
|
|
T1 |
6732 |
|
T11 |
42 |
|
T12 |
4 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |