Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7455117 |
1 |
|
|
T23 |
490 |
|
T24 |
152 |
|
T1 |
45218 |
| auto[1] |
5508012 |
1 |
|
|
T1 |
36750 |
|
T11 |
148 |
|
T12 |
6 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2416910 |
1 |
|
|
T1 |
16003 |
|
T11 |
74 |
|
T12 |
6 |
| auto[1] |
auto[0] |
auto[1] |
355519 |
1 |
|
|
T1 |
1921 |
|
T11 |
6 |
|
T16 |
2 |
| auto[1] |
auto[1] |
auto[0] |
2386777 |
1 |
|
|
T1 |
16782 |
|
T11 |
66 |
|
T16 |
11 |
| auto[1] |
auto[1] |
auto[1] |
348806 |
1 |
|
|
T1 |
2044 |
|
T11 |
2 |
|
T129 |
69 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |