Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7459212 |
1 |
|
|
T23 |
490 |
|
T24 |
152 |
|
T1 |
46551 |
| auto[1] |
5503917 |
1 |
|
|
T1 |
35417 |
|
T11 |
152 |
|
T16 |
50 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10664534 |
1 |
|
|
T23 |
490 |
|
T24 |
152 |
|
T1 |
69661 |
| auto[1] |
2298595 |
1 |
|
|
T1 |
12307 |
|
T11 |
88 |
|
T16 |
4 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7494168 |
1 |
|
|
T23 |
490 |
|
T24 |
152 |
|
T1 |
46469 |
| auto[1] |
5468961 |
1 |
|
|
T1 |
35499 |
|
T11 |
141 |
|
T12 |
8 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1588896 |
1 |
|
|
T1 |
12117 |
|
T11 |
25 |
|
T12 |
8 |
| auto[1] |
auto[0] |
auto[1] |
1151879 |
1 |
|
|
T1 |
6419 |
|
T11 |
48 |
|
T17 |
6 |
| auto[1] |
auto[1] |
auto[0] |
1581470 |
1 |
|
|
T1 |
11075 |
|
T11 |
28 |
|
T16 |
17 |
| auto[1] |
auto[1] |
auto[1] |
1146716 |
1 |
|
|
T1 |
5888 |
|
T11 |
40 |
|
T16 |
4 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |