Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7445512 |
1 |
|
|
T23 |
490 |
|
T24 |
152 |
|
T1 |
44570 |
| auto[1] |
5517617 |
1 |
|
|
T1 |
37398 |
|
T11 |
140 |
|
T12 |
6 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10647720 |
1 |
|
|
T23 |
490 |
|
T24 |
152 |
|
T1 |
68615 |
| auto[1] |
2315409 |
1 |
|
|
T1 |
13353 |
|
T11 |
67 |
|
T16 |
26 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7451840 |
1 |
|
|
T23 |
490 |
|
T24 |
152 |
|
T1 |
44092 |
| auto[1] |
5511289 |
1 |
|
|
T1 |
37876 |
|
T11 |
157 |
|
T12 |
4 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1597345 |
1 |
|
|
T1 |
12076 |
|
T11 |
33 |
|
T16 |
4 |
| auto[1] |
auto[0] |
auto[1] |
1155767 |
1 |
|
|
T1 |
6604 |
|
T11 |
39 |
|
T16 |
16 |
| auto[1] |
auto[1] |
auto[0] |
1598535 |
1 |
|
|
T1 |
12447 |
|
T11 |
57 |
|
T12 |
4 |
| auto[1] |
auto[1] |
auto[1] |
1159642 |
1 |
|
|
T1 |
6749 |
|
T11 |
28 |
|
T16 |
10 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |