Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7461528 |
1 |
|
|
T23 |
490 |
|
T24 |
152 |
|
T1 |
45332 |
| auto[1] |
5501601 |
1 |
|
|
T1 |
36636 |
|
T11 |
111 |
|
T12 |
11 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10653207 |
1 |
|
|
T23 |
490 |
|
T24 |
152 |
|
T1 |
69329 |
| auto[1] |
2309922 |
1 |
|
|
T1 |
12639 |
|
T11 |
91 |
|
T12 |
4 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7474271 |
1 |
|
|
T23 |
490 |
|
T24 |
152 |
|
T1 |
45199 |
| auto[1] |
5488858 |
1 |
|
|
T1 |
36769 |
|
T11 |
179 |
|
T12 |
4 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1586178 |
1 |
|
|
T1 |
12009 |
|
T11 |
39 |
|
T16 |
14 |
| auto[1] |
auto[0] |
auto[1] |
1152557 |
1 |
|
|
T1 |
6046 |
|
T11 |
68 |
|
T16 |
16 |
| auto[1] |
auto[1] |
auto[0] |
1592758 |
1 |
|
|
T1 |
12121 |
|
T11 |
49 |
|
T129 |
216 |
| auto[1] |
auto[1] |
auto[1] |
1157365 |
1 |
|
|
T1 |
6593 |
|
T11 |
23 |
|
T12 |
4 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |